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Dursun, Havva Ozlem. "Jump Detection With Power And Bipower Variation Processes." Master's thesis, METU, 2007. http://etd.lib.metu.edu.tr/upload/12608940/index.pdf.
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In this study, we show that realized bipower variation which is an extension of realized power variation is an alternative method that estimates integrated variance like realized variance. It is seen that realized bipower variation is robust to rare jumps. Robustness means that if we add rare jumps to a stochastic volatility process, realized bipower variation process continues to estimate integrated variance although realized variance estimates integrated variance plus the quadratic variation of the jump component. This robustness is crucial since it separates the discontinuous component of quadratic variation which comes from the jump part of the logarithmic price process. Thus, we demonstrate that if the logarithmic price process is in the class of stochastic volatility plus rare jumps processes then the difference between realized variance and realized bipower variation process estimates the discontinuous component of the quadratic variation. So, quadratic variation of the jump component can be estimated and jump detection can be achieved.
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Venkataraman, Ganesh. "Variation and power issues in VLSI clock networks." [College Station, Tex. : Texas A&M University, 2007. http://hdl.handle.net/1969.1/ETD-TAMU-1250.
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Hu, Fei. "Process variation-resistant dynamic power optimization of VLSI circuits." Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Fall/Dissertation/HU_FEI_35.pdf.
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Nduku, Nyaniso Prudent. "Development of methods for distribution network power quality variation monitoring." Thesis, Cape Peninsula University of Technology, 2009. http://hdl.handle.net/20.500.11838/1144.
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Thesis (MTech (Electrical Engineering))--Cape Peninsula University of Technology, 2009<br>The purpose of this project is to develop methods for distribution network power quality'
variations monitoring. Power quality (PO) has become a significant issue for both power
suppliers and customers. There have been important changes in power system regarding to
power quality requirements. "Power quality" is the combination at voltage quality and current
quality. The main research problem of the project is to investigate the power quality of a
distribution network by selection of proper measurement, applying and developing the
existing classic and modern signal conditioning methods for power disturbance's parameters
extracting and monitoring. The research objectives are:
To study the standard lEC 61000-4-30 requirements. to investigate the common
couplings in the distribution network.
To identity the points for measurement, to develop MySQL database for the data from
the measurement and to develop MATLAB software tor simulation of the network
To develop methods based on Fourier transforms for estimation of the parameters of
the disturbances.
To develop software for the methods implementation,
The influence of different loads on power quality disturbances are considered in the
distribution network. Points on the network and meters according to the lEC power quality
standards are investigated and applied for the CPUT Bellville campus distribution network.
The implementation of the power quality monitoring for the CPUT Bellville campus helps the
quality of power supply to be improved and the used power to be reduced.
MATLAB programs to communicate with the database and calculate the disturbances and
power quality parameters are developed.
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Lin, Yan. "Power, variation and reliability optimization for FPGAs in nanometer technologies." Diss., Restricted to subscribing institutions, 2007. http://proquest.umi.com/pqdweb?did=1495961611&sid=1&Fmt=2&clientId=1564&RQT=309&VName=PQD.
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Kakoee, Mohammad Reza <1978>. "Reliable and Variation-Tolerant Interconnection Network for Low Power MPSOCS." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2012. http://amsdottorato.unibo.it/4407/.
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Multi-Processor SoC (MPSOC) design brings to the foreground a large number of challenges, one of the most prominent of which is the design of the chip interconnection.
With a number of on-chip blocks presently ranging in the tens, and quickly approaching the hundreds, the novel issue of how to best provide on-chip communication resources is clearly felt.
Scaling down of process technologies has increased process and dynamic variations as well as transistor wearout. Because of this, delay variations increase and impact the performance of the MPSoCs. The interconnect architecture inMPSoCs becomes a single point of failure as it connects all other components of the system together. A faulty processing element may be shut down entirely, but the interconnect architecture must be able to tolerate partial failure and variations and operate with performance, power or latency overhead.
This dissertation focuses on techniques at different levels of abstraction to face with the reliability and variability issues in on-chip interconnection networks. By showing the test results of a GALS NoC testchip this dissertation motivates the need for techniques to detect and work around manufacturing faults and process variations in MPSoCs’ interconnection infrastructure. As a physical design technique, we propose the bundle routing framework as an effective way to route the Network on Chips’ global links. For architecture-level design, two cases are addressed: (I) Intra-cluster communication where we propose a low-latency interconnect with variability robustness (ii) Inter-cluster communication where an online functional testing with a reliable NoC configuration are proposed. We also propose dualVdd as an orthogonal way of compensating variability at the post-fabrication stage. This is an alternative strategy with respect to the design techniques, since it enforces the compensation at post silicon stage.
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Wells, Mark Simon. "The effects of power variation on cycling time-trial performance." Thesis, Liverpool Hope University, 2017. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.722172.
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Chae, Kwanyeob. "Design methodologies for robust low-power digital systems under static and dynamic variations." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/52174.
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Variability affects the performance and power of a circuit. Along with static variations, dynamic variations, which occur during chip operation, necessitate a safety margin. The safety margin makes it difficult to meet the target performance within a limited power budget. This research explores methodologies to minimize the safety margin, thereby improving the energy efficiency of a system. The safety margin can be reduced by either minimizing the variation or adapting to the variation. This research explores three different methods to compensate for variations efficiently. First, post-silicon tuning methods for minimizing variations in 3D ICs are presented. Design methodologies to apply adaptive voltage scaling and adaptive body biasing to 3D ICs and the associated circuit techniques are explored. Second, non-design-intrusive circuit techniques are proposed for adaptation to dynamic variations. This work includes adaptive clock modulation and bias-voltage generation techniques. Third, design-intrusive methods to eliminate the safety margin are proposed. The proposed methodologies can prevent timing-errors in advance with a minimized performance penalty. As a result, the methods presented in this thesis minimize static variations and adapt to dynamic variations, thereby, enabling robust low-power operation of digital systems.
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Casagrande, Anthony Joseph. "Robust, Low Power, Discrete Gate Sizing." Scholar Commons, 2015. http://scholarcommons.usf.edu/etd/5656.
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Ultra-deep submicron circuits require accurate modeling of gate delay in order to meetaggressive timing constraints. With the lack of statistical data, variability due to the mechanical manufacturing process and its chemical properties poses a challenging problem. Discrete gate sizing requires (i) accurate models that take into account random parametric variation and (ii) a fair allocation of resources to optimize the solution. The proposed GTFUZZ gate sizing algorithm handles both tasks. Gate sizing is modeled as a resource allocation problem using fuzzy game theory. Delay is modeled as a constraint and power is optimized in this algorithm. In GTFUZZ, delay is modeled as a fuzzy goal with fuzzy parameters to
capture the imprecision of gate delay early in the design phase when extensive empirical data is absent. Dynamic power is modeled as a fuzzy goal without varying coefficients. The fuzzy goals provide a flexible platform for multimetric optimization. The robust GTFUZZ algorithm is compared against fuzzy linear programming (FLP) and deterministic worst-case FLP (DWCFLP) algorithms. The benchmark circuits are first synthesized, placed, routed, and optimized for performance using the Synopsys University 32/28nm standard cell library and technology files. Operating at the optimized clock frequency, results show an average
power reduction of about 20% versus DWCFLP and 9% against variation-aware gate sizing with FLP. Timing and timing yield are verified by both Synopsys PrimeTime and Monte Carlo simulations of the critical paths using HSPICE.
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Lu, Yuanlin. "Power and performance optimization of static CMOS circuits with process variation." Auburn, Ala., 2007. http://repo.lib.auburn.edu/07M%20Dissertations/LU_YUANLIN_28.pdf.
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Ni, Chenxi. "Architectural level delay and leakage power modelling of manufacturing process variation." Thesis, University of Newcastle upon Tyne, 2013. http://hdl.handle.net/10443/1938.
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The effect of manufacturing process variations has become a major issue regarding the estimation of circuit delay and power dissipation, and will gain more importance in the future as device scaling continues in order to satisfy market place demands for circuits with greater performance and functionality per unit area. Statistical modelling and analysis approaches have been widely used to reflect the effects of a variety of variational process parameters on system performance factor which will be described as probability density functions (PDFs). At present most of the investigations into statistical models has been limited to small circuits such as a logic gate. However, the massive size of present day electronic systems precludes the use of design techniques which consider a system to comprise these basic gates, as this level of design is very inefficient and error prone. This thesis proposes a methodology to bring the effects of process variation from transistor level up to architectural level in terms of circuit delay and leakage power dissipation. Using a first order canonical model and statistical analysis approach, a statistical cell library has been built which comprises not only the basic gate cell models, but also more complex functional blocks such as registers, FIFOs, counters, ALUs etc. Furthermore, other sensitive factors to the overall system performance, such as input signal slope, output load capacitance, different signal switching cases and transition types are also taken into account for each cell in the library, which makes it adaptive to an incremental circuit design. The proposed methodology enables an efficient analysis of process variation effects on system performance with significantly reduced computation time compared to the Monte Carlo simulation approach. As a demonstration vehicle for this technique, the delay and leakage power distributions of a 2-stage asynchronous micropipeline circuit has been simulated using this cell library. The experimental results show that the proposed method can predict the delay and leakage power distribution with less than 5% error and at least 50,000 times faster computation time compare to 5000-sample SPICE based Monte Carlo simulation. The methodology presented here for modelling process variability plays a significant role in Design for Manufacturability (DFM) by quantifying the direct impact of process variations on system performance. The advantages of being able to undertake this analysis at a high level of abstraction and thus early in the design cycle are two fold. First, if the predicted effects of process variation render the circuit performance to be outwith specification, design modifications can be readily incorporated to rectify the situation. Second, knowing what the acceptable limits of process variation are to maintain design performance within its specification, informed choices can be made regarding the implementation technology and manufacturer selected to fabricate the design.
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DeLucia, Dominic. "A Parametric Study on Power Variation for Model Wind Turbine Arrays." PDXScholar, 2013. http://pdxscholar.library.pdx.edu/open_access_etds/1120.
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This thesis presents the results of wind tunnel experiments performed for various model wind turbine arrays. The aim is to understand how siting affects power output. To optimize wind farm efficiency the experiments vary the parameters of the model wind turbines and the layout of the wind turbine array. The parameters include the alignment, height, spacing, and the rotational direction of the model wind turbines. These experiments employ mechanical torque sensors to simultaneously measure the torque and rotor angular velocity, which yields a direct measurement of the fluid mechanical power extracted by the turbine at multiple locations. For a 4 × 3 array, the power is calculated at the center turbine in each of the rows. Variations in wind farm efficiency ranging from 55% to 90% are observed between the 13 different layouts tested. Modifications to the layout of the wind turbine array clearly affects the power output of the wind turbines downstream. The results of such experiments highlight the importance of studying the relationship between wind farm layout and power output.
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Samanta, Rupak. "Design methodologies for variation-aware integrated circuits." [College Station, Tex. : Texas A&M University, 2008. http://hdl.handle.net/1969.1/ETD-TAMU-3119.
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Vivekraja, Vignesh. "Low-Power, Stable and Secure On-Chip Identifiers Design." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/34854.
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Trustworthy authentication of an object is of extreme importance for secure protocols. Traditional methods of storing the identity of an object using non-volatile memory is insecure. Novel chip-identifiers called Silicon Physical Unclonable Functions (PUFs) extract the random process characteristics of an Integrated Circuit to establish the identity. Though such types of IC identifiers are difficult to clone and provide a secure, yet an area and power efficient authentication mechanism, they suffer from instability due to variations in environmental conditions and noise. The decreased stability imposes a penalty on the area of the PUF circuit and the corresponding error correcting hardware, when trying to generate error-free bits using a PUF.
In this thesis, we propose techniques to improve the popular delay-based PUF architectures holistically, with a focus on its stability. In the first part, we investigate the effectiveness of circuit-level optimizations of the delay based PUF architectures. We show that PUFs which operate in the subthreshold region, where the transistor supply voltage is maintained below the threshold voltage of CMOS, are inherently more stable than PUFs operating at nominal voltage because of the increased difference in characteristics of transistors at this region. Also, we show that subthreshold PUF enjoys higher energy and area efficiency. In the second part of the thesis, we propose a feedback-based supply voltage control mechanism and a corresponding architecture to improve the stability of delay-based PUFs against variations in temperature.<br>Master of Science
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Hansson, Martin. "Low-Power Clocking and Circuit Techniques for Leakage and Process Variation Compensation." Doctoral thesis, Linköpings universitet, Elektroniska komponenter, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-12495.
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Over the last four decades the integrated circuit industry has evolved in a tremendous pace. This success has been driven by the scaling of device sizes leading to higher and higher integration capability, which have enabled more functionality and higher performance. The impressive evolution of modern high-performance microprocessors have resulted in chips with over a billion transistors as well as multi-GHz clock frequencies. As the silicon integrated circuit industry moves further into the nanometer regime, scaling of device sizes is still predicted to continue at least into the near future. However, there are a number of challenges to overcome to be able to continue the increase of integration at the same pace. Three of the major challenges are increasing power dissipation due to clocking of synchronous circuit, increasing leakage currents causing growing static power dissipation and reduced circuit robustness, and finally increasing spread in circuit parameters due to physical limitations in the manufacturing process. This thesis presents a number of circuit techniques that aims to help in all three of the mentioned challenges.Power dissipation related to the clock generation and distribution is identified as the dominating contributor of the total active power dissipation for multi-GHz systems. As the complexity and size of synchronous systems continues to increase, clock power will also increase. This makes novel power reduction techniques absolutely crucial in future VLSI design. In this thesis an energy recovering clocking technique aimed at reducing the total chip clock power is presented. Based on theoretical analysis the technique is shown to enable considerable clock power savings. Moreover, the impact of the proposed technique on conventional flip-flop topologies is studied. Measurements on an experimental chip design proves the technique, and shows more than 56% lower clock power compared to conventional clock distribution techniques at clock frequencies up to 1.76 GHz.Static leakage power dissipation is a considerable contributor to the total power dissipation. This power is dissipated even for circuits that are idle and not contributing to the operation. Hence, with increasing number of transistors on each chip, circuit techniques which reduce the static leakage currents are necessary. In this thesis a technique is discussed which reduces the static leakage current in a microcode ROM resulting in 30% reduction of the leakage power with no area or performance penalty.Apart from increasing static power dissipation the increasing leakage currents also impact the robustness constraints of the circuits. This is important for regenerative circuits like flip-flops and latches where a changed state due to leakage will lead to loss of functionality. This is a serious issue especially for high-performance dynamic circuits, which are attractive in order to limit the clock load in the design. However, with the increasing leakage the robustness of dynamic circuits reduces dramatically. To improve the leakage robustness for sub-90 nm low clock load dynamic flip-flops, a novel keeper technique is proposed. The proposed keeper utilizes a scalable and simple leakage compensation technique, which is implemented on a reconfigurable flip-flop. At normal clock frequencies the flip-flop is configured in dynamic mode, and reduces the clock power by 25% due to the lower clock load. During any low-frequency operation, the flip-flop is configured as a static flip-flop retaining full functional robustness.As scaling continues further towards the fundamental atomistic limits, several challenges arise for continuing industrial device integration. Large inaccuracies in lithography process, impurities in manufacturing, and reduced control of dopant levels during implantation all cause increasing statistical spread of performance, power, and robustness of the devices. In order to compensate the impact of the increasingly large process variations on latches and flip-flops, a reconfigurable keeper technique is presented in this thesis. In contrast to the traditional design for worst-case process corners, a variable keeper circuit is utilized. The proposed reconfigurable keeper preserves the robustness of storage nodes across the process corners without degrading the overall chip performance.
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Indralingam, Maheswaran. "Sequential estimation, parameter variation and predictive power of econometric market response models." Thesis, Lancaster University, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.255352.
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Yamaoka, Masanao. "A study on low-power SRAM design under process variation of transistors." 京都大学 (Kyoto University), 2007. http://hdl.handle.net/2433/135974.
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Mi, Ning. "Statistical analysis for on-chip power grid networks and interconnects considering process variation." Diss., [Riverside, Calif.] : University of California, Riverside, 2009. http://proquest.umi.com/pqdweb?index=0&did=1957327591&SrchMode=2&sid=3&Fmt=2&VInst=PROD&VType=PQD&RQT=309&VName=PQD&TS=1268428568&clientId=48051.
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Thesis (Ph. D.)--University of California, Riverside, 2009.<br>Includes abstract. Available via ProQuest Digital Dissertations. Title from first page of PDF file (viewed March 12, 2010). Includes bibliographical references (p. 100-106). Also issued in print.
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Shvartsman, Phillip. "Side-Channel-Attack Resistant AES Design Based on Finite Field Construction Variation." The Ohio State University, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=osu1555438117106036.
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Srivastav, Meeta S. "Variation Aware Energy-Efficient Methodologies for Homogeneous Many-core Designs." Diss., Virginia Tech, 2015. http://hdl.handle.net/10919/51237.
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Earlier designs were driven by the goal of achieving higher performance, but lately, energy efficiency has emerged as an even more important design principle. Strong demand from the consumer electronics drives research in the low power and energy-efficient methodologies. Moreover, with exponential increase in the number of transistors on a chip and with further technology scaling, variability in the design is now of greater concern. Variations can make the design unreliable or the design may suffer from sub-optimal performance. Through the work in this thesis, we present a multi-dimensional investigation into the design of variation aware energy-efficient systems. Our overarching methodology is to use system-level decisions to mitigate undesired effects originating from device-level and circuit-level issues.
We first look into the impact of process variation (PV) on energy efficient, scalable throughput many-core DSP systems. In our proposed methodology, we leverage the benefits of aggressive voltage scaling (VS) for obtaining energy efficiency while compensating for the loss in performance by exploiting parallelism present in various DSP designs. We demonstrate this proposed methodology consumes 8% - 77% less power as compared to simple dynamic VS over different workload environments. Later, we show judicious system-level decisions, namely, number of cores, and their operating voltage can greatly mitigate the effects of PV and consequently, improve the energy efficiency of the design. We also present our analysis discussing the impact of aging on the proposed methodology. To validate our proposed system-level approach, design details of a prototype chip fabricated in the 90nm technology node and its findings are also presented. The chip consists of 8 homogeneous FIR cores, which are capable of running from near-threshold to nominal voltages. In the 20-chip population, we observe 7% variation in the speed at nominal voltage (0.9V) and 26% at near threshold voltage (0.55V) among all the cores. We also observe 54% variation in power consumption characteristics of the cores. The chip measurement results show that our proposed methodology of judiciously selecting the cores and their operating voltage can result in 6.27% - 28.15% more energy savings for various workload environments, as compared to globally voltage scaled systems. Furthermore, we present the impact of temperature variations on the energy-efficiency of the above systems.
We also study the problem of voltage variations in the integrated circuits. We first present the characteristics of a dynamic voltage noise as measured on a 28nm FPGA. We propose a fully digital on-chip sensor that can detect the fast voltage transients and alert the system of voltage emergency. A traditional approach to mitigate this problem is to use safety guardbands. We demonstrate that our proposed sensor system will be 6% - 27.5% more power efficient than the traditional approach.<br>Ph. D.
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Eppanapelli, Lavan Kumar. "Investigation of wind potential variation at three measurement sites based on atmospheric stability and power production." Thesis, KTH, Kraft- och värmeteknologi, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-136935.
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As tapping energy from wind expands rapidly worldwide, it is a common procedure to locate a practicable site to extract energy from abundant wind flow by building wind farms. Comprehensive understanding of wind resource at a site is important to perform the main activities say, wind flow modeling, wind turbines micro siting, annual energy yield calculation and cost of energy estimation. Wind measuring campaigns involve using of measuring instruments such as meteorological tower instrumented with anemometers, wind vanes and temperature sensors; remote sensing devices such as SoDAR, LiDAR. These meteorological devices provide detailed information on wind behavior with respect to the height, time and temperature. These systems were proven in providing promising wind measurements even though they are susceptible to certain weather conditions. The study progressed by focusing on the wind behavior at three locations to investigate the possible factors that varies the wind character. A location with one met mast and two AQ500 SoDAR systems was considered for this project where one AQ500 is 800m away and other AQ500 is 5515m away from the point of Met mast. The location is contemplated as a decent approach to the spatial analysis of the wind resource as there is a large scope to analyze the wind character between two nearby sites and two faraway sites. Monostatic 3-beam SoDAR systems from AQ System, Sweden and 100m meteorological tower with instruments are used in this project work for collecting the wind data. One-year worth of wind data at standard 10min intervals has been collected from the three systems. This report outlines the theoretical description of project location, AQ500 SoDAR and Met mast. A detailed explanation of the data quality control and filtering methods are discussed along with respective reasons. The conclusion is drawn after performing the statistical analysis between wind speed and other parameters such as turbulent intensity, wind direction, thermal stability and temperature. Mat lab is used for computing and analyzing the wind data from three systems.
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Schaefer, David. "Resource Variation in Social Exchange Networks: the Effects of Duplicability And Transferability on the Use of Power." Diss., The University of Arizona, 2006. http://hdl.handle.net/10150/194654.
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This dissertation presents a theory explaining how characteristics of the resources exchanged in networks influence the outcomes actors experience. I draw upon social exchange theory and social network research to identify valuable benefits provided by networks and relevant dimensions of resource variation. I identify control benefits and diversity benefits as important outcomes driven by network processes. Control benefits derive from exchanging at a favorable rate; diversity benefits are due to the variety of resources an actor receives through exchange. Both of these outcomes have structural foundations; thus actors' benefits are contingent upon their location in the network. I identify two dimensions of resource variation that alter whether resources can be used in multiple exchanges. Duplicability refers to whether a resource provider retains control of the resource and can use it in a subsequent exchange. Transferability refers to whether a resource recipient can utilize that resource in another exchange. Variation along these dimensions affects the mechanisms that produce benefits, such that the advantage of a position depends upon the type of resource exchanged. Hypotheses generated through this theoretical logic are tested in a laboratory experiment. Results provide strong support for the theory: Across the same network structure, resource variation alone produces fundamentally different distributions of control and diversity benefits. The theory successfully predicts how resource characteristics determine 1) variation in control benefits across relations, 2) ordering of diversity benefits across positions, and 3) the correlation of control and diversity benefits across resource types. Implications of these results for social exchange and social network theories are discussed.
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Bhavanam, Yaminidhar Reddy. "Combined power system planning and policy proposition for future electric vehicle charging infrastructure." Thesis, Brunel University, 2015. http://bura.brunel.ac.uk/handle/2438/11020.
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In order to achieve the UK Government’s legally bound framework of greenhouse gas reduction targets, the transport sector is undergoing drastic changes. The key action taken by the Department of Transport in addressing the issue was the introduction of Ultra-low emission vehicles (ULEV) concept. Office for Low Emission Vehicles (OLEV) was introduced to support early market for ULEV and development of efficient recharging network through Plugged-in Places programme. The massive deployment of EV charging stations across GB will have direct impact on GB power system as they require electricity supply for their operation. It is therefore deemed necessary to carry out investigations on the capacity of the network assets to handle this load and to develop policies to manage the future EV charging infrastructure efficiently. This thesis provides an overview of the EV technology introducing various technicalities behind EVs and the associated charging stations. The extended theory about interoperability between EVs and power networks is also presented. Investigation of an 11kV networked site and 66/11 kV networked area is performed to determine their potential in accommodating future EV charging infrastructure. A methodology has been proposed to carry out investigations in 11kV networked site. For analysis purpose both the real networks are modelled in detail using power system analysis software Electrical Transient Analyzer Programme (ETAP). Scottish and Southern Energy (SSE) and Northern Power Grid (NPG) are the owners of the distribution networks respectively. Collaboration with DNOs has taken place to collect the existing network data. Finally, a university based EV charging bays management policy has been proposed.
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Ghai, Dhruva V. "Variability-aware low-power techniques for nanoscale mixed-signal circuits." Thesis, University of North Texas, 2009. https://digital.library.unt.edu/ark:/67531/metadc9850/.
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New circuit design techniques that accommodate lower supply voltages necessary for portable systems need to be integrated into the semiconductor intellectual property (IP) core. Systems that once worked at 3.3 V or 2.5 V now need to work at 1.8 V or lower, without causing any performance degradation. Also, the fluctuation of device characteristics caused by process variation in nanometer technologies is seen as design yield loss. The numerous parasitic effects induced by layouts, especially for high-performance and high-speed circuits, pose a problem for IC design. Lack of exact layout information during circuit sizing leads to long design iterations involving time-consuming runs of complex tools. There is a strong need for low-power, high-performance, parasitic-aware and process-variation-tolerant circuit design. This dissertation proposes methodologies and techniques to achieve variability, power, performance, and parasitic-aware circuit designs. Three approaches are proposed: the single iteration automatic approach, the hybrid Monte Carlo and design of experiments (DOE) approach, and the corner-based approach. Widely used mixed-signal circuits such as analog-to-digital converter (ADC), voltage controlled oscillator (VCO), voltage level converter and active pixel sensor (APS) have been designed at nanoscale complementary metal oxide semiconductor (CMOS) and subjected to the proposed methodologies. The effectiveness of the proposed methodologies has been demonstrated through exhaustive simulations. Apart from these methodologies, the application of dual-oxide and dual-threshold techniques at circuit level in order to minimize power and leakage is also explored.
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Zois, Georgios. "Algorithmic problems in power management of computing systems." Thesis, Paris 6, 2014. http://www.theses.fr/2014PA066462/document.
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Cette thèse se focalise sur des algorithmes efficaces en énergie pour des problèmes d'ordonnancement de tâches sur des processeurs pouvant varier la vitesse d'exécution ainsi que sur des processeurs fonctionnant sous un mécanisme de réchauffement-refroidissement, où pour un budget d'énergie donné ou un seuil thermique, l'objectif consiste à optimiser un critère de Qualité de Service. Une partie de notre recherche concerne des problèmes d'ordonnancement de tâches apparaissant dans des environnements de traitement de grandes données. Dans ce contexte, nous nous focalisons sur le paradigme MapReduce en considérant des problèmes d'ordonnancement efficaces en énergie sur un ensemble de processeurs, ainsi que pour la version classique.Premièrement, nous proposons des résultats de complexité, des algorithmes optimaux et approchés pour différentes variantes du problème de la minimisation du retard maximal d'un ensemble de tâches sur un processeur pouvant varier la vitesse d'exécution. Ensuite, nous considérons le problème d'ordonnancement MapReduce dans les versions énergétique et classique sur des processeurs non-reliés où le but est de minimiser le temps d'achèvement pondéré. Nous étudions deux cas spéciaux et les généralisations de ces deux problèmes en proposant des algorithmes d'approximation constante. Enfin, nous étudions le problème d'ordonnancement dans lequel la température du processeur est en-dessous un seuil donné où chaque tâche contribue au réchauffement et le but est de maximiser le nombre de tâches exécutées. Nous considérons le cas où les tâches ont des durées unitaires et ayant la même date d'échéance et nous étudions le rapport d'approximation de ce problème<br>This thesis is focused on energy-efficient algorithms for job scheduling problems on speed-scalable processors, as well as on processors operating under a thermal and cooling mechanism, where, for a given budget of energy or a thermal threshold, the goal is to optimize a Quality of Service criterion. A part of our research concerns scheduling problems arising in large-data processing environments. In this context, we focus on the MapReduce paradigm and we consider problems of energy-efficient scheduling on multiple speed-scalable processors as well as classical scheduling on a set of unrelated processors.First, we propose complexity results, optimal and constant competitive algorithms for different energy-aware variants of the problem of minimizing the maximum lateness of a set of jobs on a single speed-scalable processor. Then, we consider energy-aware MapReduce scheduling as well as classical MapReduce scheduling (where energy is not our concern) on unrelated processors, where the goal is to minimize the total weighted completion time of a set of MapReduce jobs. We study special cases and generalizations of both problems and propose constant approximation algorithms. Finally, we study temperature-aware scheduling on a single processor that operates under a strict thermal threshold, where each job has its own heat contribution and the goal is to maximize the schedule's throughput. We consider the case of unit-length jobs with a common deadline and we study the approximability of the problem
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Hansson, Martin. "Low-Power Multi-GHz Circuit Techniques for On-chip Clocking." Licentiate thesis, Linköping : Linköping University, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7545.
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Zheng, Cong. "Loosely Coupled Transformer and Tuning Network Design for High-Efficiency Inductive Power Transfer Systems." Diss., Virginia Tech, 2015. http://hdl.handle.net/10919/52893.
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Transfer signal without wire has been widely accepted after the introduction of cellular technology and WiFi technology, hence the power cable is the last wire that has yet to be eliminated. Inductive power transfer (IPT) has drawn substantial interest in both academia and industry due to its advantages including convenience, nonexistence of cable and connector, no electric shock issue, ability to work under some extreme environment, and so on. After performing thorough literature review of IPT systems, two major drawbacks including low power efficiency and coil displacement sensitivity are identified as the main obstacles that have to be solved in order for these systems to reach full functionality and compete with existing wired solutions.
To address the limitations and design challenges in the IPT systems, a detailed electric circuit modeling of individual part of the IPT DC-DC stage is performed. Several resonant DC-AC inverters and output AC-DC rectifiers are compared based on their performance and feasibility in inductive charging applications. Different equivalent circuit models for the loosely coupled
transformer (LCT) are derived which allows for better understanding on how power is distributed among the circuit components. Five compensation networks to improve the power transfer efficiency are evaluated and their suitable application occasions are identified.
With comprehensive circuit model analysis, the influence of the resonant compensation tank parameters has been investigated carefully for efficient power transfer. A novel tuning network parameters design methodology is proposed based on multiple given requirement such as battery charging profile, geometry constraints and operating frequency range, with the aim of avoiding bifurcation phenomenon during the whole charging process and achieving decent efficiency. A 4-kW hardware prototype based on the proposed design approach is built and tested under different gap and load conditions. Peak IPT system DC-DC efficiencies of 98% and 96.6% are achieved with 4-cm and 8-cm air gap conditions, which is comparable to the conventional plug-in type or wired charging systems for EVs. A long-hour test with real EV batteries is conducted to verify the wireless signal transmission and CC/CV mode seamless transition during the whole charging profile without bifurcation.
To reduce the IPT system sensitivity to the gap variation or misalignment, a novel LCT design approach without additional complexity for the system is proposed. With the aid of FEA simulation software, the influence of coil relative position and geometry parameters on the flux distribution and coupling coefficient of the transmitter and receiver is studied from an electromagnetic perspective. An asymmetrical LCT based on the proposed design method is built to compare with a traditional symmetrical LCT. With fixed 10-mm gap and 0 to 40-mm misalignment variation, the coupling coefficient for the symmetrical LCT drops from 0.354 to 0.107, and the corresponding efficiency decrease is 16.6%. The operating frequency variation is nearly 100 kHz to maintain same input/output condition. When employing the proposed asymmetrical LCT, the coupling coefficient changes between 0.312 and 0.273, and the maximum efficiency deviation is kept within 0.67% over the entire 40-mm misalignment range. Moreover, the required frequency range to achieve same operation condition is less than 10 kHz.
Lastly, some design considerations to further improve the IPT system efficiency are proposed on the basis of the designed asymmetrical LCT geometry. For given circuit specifications and LCT coupling conditions, determination of the optimal primary winding turns number could help achieve minimal winding loss and core loss. For lower output power, the optimal primary winding turns number tends to be larger compared to that for higher output power IPT system. Two asymmetrical LCT with similar dimension but different number of turns are built and tested with a 100-W hardware prototype for laptop inductive charging. The proposed efficiency improvement methodology is validated by the winding loss and core loss from experimental results.<br>Ph. D.
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Glaser, Sven [Verfasser], Jeannette [Akademischer Betreuer] Woerner, and Michael [Gutachter] Voit. "Limit theorems of the power variation of fractional Lévy processes / Sven Glaser. Betreuer: Jeannette Woerner. Gutachter: Michael Voit." Dortmund : Universitätsbibliothek Dortmund, 2015. http://d-nb.info/1110893426/34.
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Farkas, Gergely. "Applications of Stochastic calculus in economy and statistics: Extensions of the Kyle-Back model. Ambit processes and power variation." Doctoral thesis, Universitat de Barcelona, 2014. http://hdl.handle.net/10803/145973.
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This thesis deals with three possible applications of stochastic calculus: modelling prices by supply and demand in a financial market where there is an informed trader, turbulence and financial models using ambit processes and the asymptotic analysis of certain power variation processes.
The thesis is organized as follows. Part I contains the basic facts and techniques of mathematics used in the latter parts. Part II deals with the markets with asymmetric information, Chapter 2 presents the basic models by Kyle and Back, and Chapter 3 presents the new results of Kyle’s model with L´evy noise: [Cor14b] and a General Model: [Cor14a], and also a short summary of other related models. Part III is dedicated to ambit processes. Chapter 4 introduces ambit fields and processes and bond markets, summarizes the new results of some applications of ambit processes on energy markets and turbulence: [CFV14], and on a short rate model: [CFSV13]. In Part IV, power variation processes are introduced and new results of [CF10] are summarized in Section 5.3. Finally, the above mentioned articles are included in the appendices.
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Kirk, Andrew J. "Seasonal Variation of Fish and Macroinvertebrate Biomass Spectra in Southern West Virginia Streams." VCU Scholars Compass, 2016. http://scholarscompass.vcu.edu/etd/4228.
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The biomass size spectrum - the power-law scaling relationship between average individual size and total biomass - has often been studied in lake and marine ecosystems, but rarely in lotic systems. The objective of this study was to test for characteristic biomass spectra in small temperate streams. Seasonal fish and macroinvertebrate data, including population abundance and biomass estimates, were collected in three wadeable, southern West Virginia streams from October 2013 to May 2015. Fish abundances were estimated with 3-pass electrofishing (depletion) surveys and individuals were weighed in the field. Macroinvertebrates were collected with a Hess sampler and returned to the lab for identification to the lowest practical level (usually genus). Published length-mass regressions were then used to estimate individual mass. All size spectra relationships (linear regression of log-log data) were highly significant (p<0.001). Size spectra intercepts were variable and may reflect seasonal differences in fish and invertebrate densities. Size spectra slopes were more consistent, with a mean slope of approximately -0.73, suggesting a common scaling relationship between stream consumers at differing trophic levels.
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Miller, Timothy Normand. "Architectural Solutions for Low-power, Low-voltage, and Unreliable Silicon Devices." The Ohio State University, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=osu1337612488.
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Priya, Kanu. "Study of Physical Unclonable Functions at Low Voltage on FPGA." Thesis, Virginia Tech, 2011. http://hdl.handle.net/10919/34709.
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Physical Unclonable Functions (PUFs) provide a secure, power efficient and non-volatile means of chip identification. These are analogous to one-way functions that are easy to create but impossible to duplicate. They offer solutions to many of the FPGA (Field Programmable Gate Array) issues like intellectual property, chip authentication, cryptographic key generation and trusted computing. Moreover, FPGA evolving as an important platform for flexible logic circuit, present an attractive medium for PUF implementation to ensure its security.
In this thesis, we explore the behavior of RO-PUF (Ring Oscillator Physical Unclonable Functions) on FPGA when subjected to low voltages. We investigate its stability by applying environmental variations, such as temperature changes to characterize its effectiveness. It is shown with the help of experiment results that the spread of frequencies of ROs widens with lowering of voltage and stability is expected. However, due to inherent circuit challenges of FPGA at low voltage, RO-PUF fails to generate a stable response. It is observed that more number of RO frequency crossover and counter value fluctuation at low voltage, lead to instability in PUF. We also explore different architectural components of FPGA to explain the unstable nature of RO-PUF. It is reasoned out that FPGA does not sustain data at low voltage giving out unreliable data. Thus a low voltage FPGA is required to verify the stability of RO-PUF. To emphasize our case, we look into the low power applications research being done on FPGA. We conclude that FPGA, though flexible, being power inefficient, requires optimization on architectural and circuit level to generate stable responses at low voltages.<br>Master of Science
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Sehil, Khaled. "A super-capacitor based energy storage for quick variation in stand-alone PV systems." Thesis, Brunel University, 2018. http://bura.brunel.ac.uk/handle/2438/16222.
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Photovoltaic (PV) system is one of the most prominent energy sources, producing electricity directly from sunlight. In additionally, it is easy to install and is supported financially by many governments as part of their strategy to reduce CO2 gas emissions, and to achieve their agreed set of reduction targets by 2020. In the meantime, researchers have been working on the PV system to make it more efficient, easy to maintain, reliable to use and cost effective. In the stand-alone PV system, a battery is required. This is due to the fluctuating nature of the output energy delivered by the PV arrays owing to the weather conditions and the unpredictable behaviour of uses with regard to the consumption of energy. During the hours of sunshine, the PV system is directly feeding the load and any surplus electrical energy is stored in the battery at a constant current. During the night, or during a period of low solar irradiation, the energy is supplied to the load from the battery. However, the stand-alone PV system is designed to provide an acceptable balance between reliability and cost, which is a major challenge to the designer owing to the approaches used to size the PV arrays and the battery bank. As a result, the unpredictable, quick daily changes on the PV output is not dependable. Moreover, battery performance, length of life and energy efficiency depends on the rate at which it is discharged. Therefore, it is essential to use other methods to deal with any quick variation in energy. In this thesis, a super capacitor is used to solve this problem, as it can deal with the fast-changing weather, or a rapid variation in the energy requirements of the customer. A critical evaluation with in-depth analysis of the placement and the implementation for the super-capacitor in the PV standalone system has been carried out. The results show, super-capacitor capacitance and the converter efficiency affect the delivered load energy. However, the bi-directional topology performs better than uni-directional under the same conditions. Finally, a further improvement of the system at component level, has been developed through an energy recovery snubber for the switching transition and achieved a recovery of energy for the resistive load, 94.44% for the turn on transition and 92.86% for the turn off transition. Moreover, for the inductive load, 78.33% and 97.33% of energy has been recovered for the turn on and for the turn off transition respectively.
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Hamel, Myriam. "Influence de la variation de la température ambiante sur les vibrations induites par effet de couronne /." Thèse, Chicoutimi : Université du Québec à Chicoutimi, 1991. http://theses.uqac.ca.
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Chen, Shuyu. "rf power amplifier and oscillator design for reliability and variability." Doctoral diss., University of Central Florida, 2013. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/5616.
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CMOS RF circuit design has been an ever-lasting research field. It gained so much attention since RF circuits have high mobility and wide band efficiency, while CMOS technology has the advantage of low cost and better capability of integration. At the same time, IC circuits never stopped scaling down for the recent many decades. Reliability issues with RF circuits have become more and more severe with device scaling down: reliability effects such as gate oxide break down, hot carrier injection, negative bias temperature instability, have been amplified as the device size shrinks. Process variability issues also become more predominant as the feature size decreases. With these insights provided, reliability and variability evaluations on typical RF circuits and possible compensation techniques are highly desirable. In this work, a class E power amplifier is designed and laid out using TSMC 0.18 &"181;m RF technology and the chip was fabricated. Oxide stress and hot electron tests were carried out at elevated supply voltage, fresh measurement results were compared with different stress conditions after 10 hours. Test results matched very well with mixed mode circuit simulations, proved that hot carrier effects degrades PA performances like output power, power efficiency, etc. Self- heating effects were examined on a class AB power amplifier since PA has high power operations. Device temperature simulation was done both in DC and mixed mode level. Different gate biasing techniques were analyzed and their abilities to compensate output power were compared. A simple gate biasing circuit turned out to be efficient to compensate self-heating effects under different localized heating situations. Process variation was studied on a classic Colpitts oscillator using Monte-Carlo simulation. Phase noise was examined since it is a key parameter in oscillator. Phase noise was modeled using analytical equations and supported by good match between MATLAB results and ADS simulation. An adaptive body biasing circuit was proposed to eliminate process variation. Results from probability density function simulation demonstrated its capability to relieve process variation on phase noise. Standard deviation of phase noise with adaptive body bias is much less than the one without compensation. Finally, a robust, adaptive design technique using PLL as on-chip sensor to reduce Process, Voltage, Temperature (P.V.T.) variations and other aging effects on RF PA was evaluated. The frequency and phase of ring oscillator need to be adjusted to follow the frequency and phase of input in PLL no matter how the working condition varies. As a result, the control signal of ring oscillator has to fluctuate according to the working condition, reflecting the P.V.T changes. RF circuits suffer from similar P.V.T. variations. The control signal of PLL is introduced to RF circuits and converted to the adaptive tuning voltage for substrate bias. Simulation results illustrate that the PA output power under different variations is more flat than the one with no compensation. Analytical equations show good support to what has been observed.<br>Ph.D.<br>Doctorate<br>Electrical Engineering and Computer Science<br>Engineering and Computer Science<br>Electrical Engineering
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Monjoly, Stéphanie. "Outils de prédiction pour la production d’électricité d’origine éolienne : application à l’optimisation du couplage aux réseaux de distributions d’électricité." Thesis, Antilles-Guyane, 2013. http://www.theses.fr/2013AGUY0679/document.
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La forte variabilité de la vitesse du vent fait que l'énergie produite par un parc éolien n'est pas constante dans le temps. Le gestionnaire ne peut donc pas dimensionner son réseau électrique en prenant intégralement ce type de production en compte. L' une des solutions préconisées pour permettre le développement de l' éolien et son intégration avec une plus grande sureté aux réseaux, est de développer et d'améliorer les outils de prévisions. Le travail de thèse consiste à améliorer les performances d'un outil de prédiction basé sur les réseaux de neurones bayesiens, permettant la prédiction de la puissance à très court terme . Le prédicteur fonctionne notamment par J'ajustement de paramètres, certain se détermine « automatiquement » via le mécanisme des réseaux de neurones bayesiens d' autres, que nous nommerons paramètres temporels, sont à l' appréciation de l'utilisateur. Le travail mené consiste à établir un protocole pour la fixation de ces paramètres tout en améliorant les performances du prédicteur . Nous avons donc décidé de conditionner leurs valeurs en fonction de la variabilité des séquences de puissance précédent l'instant de prévision. Tout d'abord nous avons classifié des séquences de puissance en fonction de leurs coefficients de variation en appliquant la méthode des C-moyennes floues. Puis, chaque classe formée a été testée sur plusieurs valeurs de paramètres, les valeurs associées aux meilleures prédictions ont été retenues. Enfin, ces résultats couplés au formalisme des Chaines de Markov, par le biais de la matrice de transition , ont perm is d'obtenir des taux d'amélioration par rapport à la persistance allant de 7,73 à 23,22 % selon l'horizon de prédiction considéré<br>The high variability of the wind speed has for conse quences that the energy produced by a wind farm is not constant over time. Therefore, the manager can't size the electrical network by takin g into account this type of production. One solution advocated for the development of wind energy and its integrati on with greater security at network, is to develop and improve fore casting tools. The thesi s objective is to improve the performance of a predi ction tool based on Bayesian neural networks, allowing the predi ction of wind power for short timescales. The predictor works, in part icular by the adjustment of parameters, sorne is determined "automatically" through the mechan ism of neural networks Bayesian other , which we cali temporal parameters are at the discretion of the user. The work involves establishing a protocol for the determination of these parameters and improving the performance of the predictor. So, we decided to condition their values depending on the sequence variability of wind power previous the moment of the forecast. First we classified sequences of power according to their coefficients of variation using the method of fuzzy C-means. Then, each formed class was tested for several parameters values, the values associated with the best predictions were selected. Finally , these result s coupled with the formalism of Markov chains , through the transition matrix allowed to obtain rates of improvement over the persistence ranging from 7.73 to 23.22 % depending on the prediction horizon considered
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Goodin, Jacob. "Comparison of External Kinetic and Kinematic Variables between High Barbell Back Squats and Low Barbell Back Squats across a Range of Loads." Digital Commons @ East Tennessee State University, 2015. https://dc.etsu.edu/etd/2539.
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This study compared peak force, peak power, peak velocity, impulse, work, and vertical displacement between the high bar back squat (HBBS) and low bar back squat (LBBS). Six trained males performed each using 20, 30, 40, 50, 60, 70, 80, and 90% of their recent training 1 repetition maximum. Dual force plates recorded force-time curve characteristics of ground reaction forces and four potentiometers tracked vertical and horizontal barbell displacement. Repeated–measures analysis of variance revealed a significant main effect for load (p<0.01) across all variables, but no significant effects for condition or interaction. The HBBS generated higher peak force in loads 20%–80%, higher peak power in loads 20%–60% and 80%–90%, higher peak velocity at every load, and greater vertical displacement at every load. The LBBS generated a larger impulse at loads 30%-90% and the HBBS generated more work at loads 20%, 40%, and 60%–90%.
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Mugisha, Dieudonne Manzi. "Exploiting Application Behaviors for Resilient Static Random Access Memory Arrays in the Near-Threshold Computing Regime." DigitalCommons@USU, 2015. https://digitalcommons.usu.edu/etd/4550.
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Near-Threshold Computing embodies an intriguing choice for mobile processors due to the promise of superior energy efficiency, extending the battery life of these devices while reducing the peak power draw. However, process, voltage, and temperature variations cause a significantly high failure rate of Level One cache cells in the near-threshold regime a stark contrast to designs in the super-threshold regime, where fault sites are rare.
This thesis work shows that faulty cells in the near-threshold regime are highly clustered in certain regions of the cache. In addition, popular mobile benchmarks are studied to investigate the impact of run-time workloads on timing faults manifestation. A technique to mitigate the run-time faults is proposed. This scheme maps frequently used data to healthy cache regions by exploiting the application cache behaviors. The results show up to 78% gain in performance over two other state-of-the-art techniques.
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Larsson, Lena C. "Disentangling small genetic differences in large Atlantic herring populations: comparing genetic markers and statistical power." Doctoral thesis, Stockholms universitet, Zoologiska institutionen, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:su:diva-8338.
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Genes are the foundation of evolution and biodiversity. The genetic structure of natural populations needs to be understood to maintain exploited resources rationally. This thesis focuses on genetic variability and methods to determine spatial and temporal genetic heterogeneities. Intense human exploitation generates particular challenges to conserve genetic diversity of fishes since it has genetic effects. My research concerns one of our most valuable fish species: the Atlantic herring (Clupea harengus). I analyzed Atlantic herring samples from the North and Baltic Seas. The objectives were to determine: 1) spatial genetic structure, 2) whether allozymes and microsatellites provide similar descriptions of the differentiation pattern, or 3) if they are influenced by selection, 4) factors affecting statistical power when testing for genetic differentiation, and 5) the temporal stability of the genetic structure. The results show: 1) very low levels of spatial genetic differentiation in Atlantic herring; a major component is a difference between the Baltic and North Seas, 2) a concordant pattern with allozymes and microsatellites, 3) that selection influences a microsatellite locus, which can be a low salinity adaptation, 4) that statistical power is substantial for frequently used sample sizes and markers; the difference in power between organelle and nuclear loci is partly dependent on the populations’ stage of divergence, and 5) no changes in amount of genetic variation or spatial genetic structure over a 24-year period; the selection pattern in one microsatellite locus remained. The notion that the large population sizes make herring unlikely to lose genetic diversity may be disputed. I found small local effective population sizes, and the evidence of selection hints of a distinct evolutionary lineage in the Baltic. When Atlantic herring is managed as very large units, there can be detrimental genetic effects if certain population segments are excessively harvested.
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Sen, Shreyas. "Design of process and environment adaptive ultra-low power wireless circuits and systems." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/45755.
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The objective of the proposed research is to investigate the design of Self-Aware Radio Frequency Circuits and Wireless Communication Systems that can adapt to environmental and process variations to always operate at minimum power levels possible, extending battery life.
The explosive growth of portable battery operated devices has mandated design of low power circuits and systems to prolong battery life. These devices fabricated in modern nanoscale CMOS technologies suffer from severe process variation due to the reduced controllability of the fabrication process, causing yield loss. This calls for integrated low power and process tolerant design techniques, or design of systems that can adapt to its process and environment to maintain its performance while minimizing power consumption.
Currently, most of the wireless circuits are designed to meet minimum quality-of-service requirements under worst-case wireless link conditions (interference, noise, multi-path effects), leading to high power consumption when the channel is better than worst-case. In this research, we develop a multi-dimensional adaptation approach for wireless transmitters and receivers that optimally trades-off power vs. performance across temporally changing operating conditions by concurrently tuning control parameters in the RF front end to lower power consumption. Tunable circuits (e.g. LNA) with built-in tuning knobs providing independent controllability of important specifications allow optimal adaptation. Process sensing using intelligent test and calibration facilitates yield improvement and the design of process tolerant environment adaptive systems.
Low cost testing methodologies are developed for identification of the health of the wireless circuit/system. These are used in conjunction with tuning algorithms that tune a wireless system under process variation to meet performance specifications and recover yield loss. This testing and adaptation is performed once during the post manufacture test/tune phase to compensate for manufacturing variations. This can also be applied periodically during in field operation of a device to account for performance degradation due to ageing. Finally, process tolerant environment adaptive systems are designed.
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Pan, Xiang. "Designing Future Low-Power and Secure Processors with Non-Volatile Memory." The Ohio State University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=osu1492631536670669.
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Banerjee, Debashis. "Intelligent real-time environment and process adaptive radio frequency front-ends for ultra low power applications." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/53882.
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In the thesis the design of process tolerant, use-aware radio-frequency front-ends were explored. First, the design of fuzzy logic and equation based controllers, which can adapt to multi-dimensional channel conditions, are proposed. Secondly, the thesis proves that adaptive systems can have multiple modes of operation depending upon the throughput requirements of the system. Two such modes were demonstrated: one optimizing the energy-per-bit (energy priority mode) and another achieving the lowest power consumption at the highest throughput (data priority mode). Finally, to achieve process tolerant channel adaptive operation a self-learning methodology is proposed which learns the optimal re-configuration setting for the system on-the-fly. Implications of the research are discussed and future avenues of further research are proposed.
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Gruson, François. "Modulation naturelle généralisée des convertisseurs matriciels pour la variation de vitesse." Thesis, Ecole centrale de Lille, 2010. http://www.theses.fr/2010ECLI0027/document.
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La variation de vitesse des machines électriques est une application très porteuse de l’électronique de puissance. La solution de conversion la plus répandue consiste à connecter en cascade deux convertisseurs statiques et d’effectuer une double conversion (AC/DC/AC). Une autre solution, faiblement répandue dans l’industrie, effectue une conversion directe AC/AC. Ce mémoire effectue une synthèse sur les solutions de conversion directe ainsi que sur les stratégies de modulation des convertisseurs matriciels et matriciels « double étage » dans le but de piloter des machines électriques triphasées à partir d’un réseau alternatif triphasé. Cette synthèse a permis de développer une modulation scalaire généralisée, associée à un modulateur par porteuse, équivalente à la modulation vectorielle et applicable aux différents convertisseurs matriciels. Les modulations, à nombre de commutation réduit par période de découpage, ont été approfondies. Cette généralisation a permis de mettre en évidence une solution réduisant les pertes et améliorant le comportement électromagnétique du dispositif comparativement aux modulations traditionnellement utilisées. La présentation des contraintes réelles (commande rapprochée des interrupteurs, Les protections ainsi que le filtrage) est abordée et a été utilisée pour développer une maquette laboratoire. Les stratégies de modulation ont été implantées expérimentalement et valident l’étude théorique. Enfin, un fonctionnement direct à la fréquence réseau, sans modulation donc à faibles pertes, est proposé. Un fonctionnement particulier est introduit, permettant d’effectuer le transitoire du mode modulé classique au fonctionnement direct non modulé<br>In the power electronics field, the adjustable speed drives is a growing application for electric motors control. The most common conversion solution is to connect in series two static converters and perform a double conversion (AC/DC/AC). Another solution, hardly proposed by industry, uses a direct AC/AC conversion. This thesis aims to make a direct conversion solutions and matrix converters and ‘‘two stage’’ matrix converters modulation strategies synthesis for the purpose to control three-phase electric motor with a three phase input network. This synthesis has developed a generalized scalar modulation, combined with a carrier wave modulator, equivalent to the space vector modulation and applied to matrix converters and the ‘‘two stage’’ matrix converters. Some attention has been done to reduced the switching number during the modulation period. The generalization allows to propose a modified modulation which reduces the losses and improves the electromagnetic performance compared to the traditional modulations used for these kind of converters. The practical constraint (switches control, protection system and filtering) are discussed and has been used to develop a laboratory prototype. The modulations strategies have been implemented experimentally and validate the theoretical study. Finally, a direct function mode with an equal frequency between the input and output network is proposed, without modulation and therefore low losses. In the last part, a particular operation mode is then introduced, permitting the transient operation between the modulated conventional mode to the direct mode without modulation
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Lee, Yew-Haur Jr. "Fisher Information Test of Normality." Diss., Virginia Tech, 1998. http://hdl.handle.net/10919/30725.
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An extremal property of normal distributions is that they have the smallest Fisher Information for location among all distributions with the same variance. A new test of normality proposed by Terrell (1995) utilizes the above property by finding that density of maximum likelihood constrained on having the expected Fisher Information under normality based on the sample variance. The test statistic is then constructed as a ratio of the resulting likelihood against that of normality.
Since the asymptotic distribution of this test statistic is not available, the critical values for n = 3 to 200 have been obtained by simulation and smoothed using polynomials. An extensive power study shows that the test has superior power against distributions that are symmetric and leptokurtic (long-tailed). Another advantage of the test over existing ones is the direct depiction of any deviation from normality in the form of a density estimate. This is evident when the test is applied to several real data sets.
Testing of normality in residuals is also investigated. Various approaches in dealing with residuals being possibly heteroscedastic and correlated suffer from a loss of power. The approach with the fewest undesirable features is to use the Ordinary Least Squares (OLS) residuals in place of independent observations. From simulations, it is shown that one has to be careful about the levels of the normality tests and also in generalizing the results.<br>Ph. D.
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Nascimento, Klaus Vieira do. "Metodologia de análise de variações de tensão causadas pela proteção anti-ilhamento de geradores síncronos distribuídos." Universidade de São Paulo, 2013. http://www.teses.usp.br/teses/disponiveis/18/18154/tde-26082013-133347/.
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Nos últimos anos, fatores como a reestruturação do setor de energia elétrica, a necessidade de aproveitamento de diferentes fontes primárias de energia, dificuldades na construção de grandes unidades geradoras e linhas de transmissão causadas por normas de proteção ambiental têm provocado o aumento considerável do interesse por geração distribuída. O conceito de geração distribuída tornou-se muito interessante, entretanto, sua aplicação pode provocar problemas de qualidade de energia elétrica, caso sua influência não seja devidamente estudada. Neste contexto, este documento caracteriza as variações de tensão causadas pela atuação da proteção anti-ilhamento de geradores síncronos distribuídos. Este problema pode ser considerado uma nova abordagem sobre os impactos dos geradores distribuídos na qualidade da energia elétrica, visto que as causas das variações de tensão são tipicamente relacionadas às tomadas ou alívios de grandes blocos carga, partidas de motores de indução, curtos-circuitos, desligamentos de linhas etc. Para estudar o problema, inicialmente foi feito um estudo sobre normatização técnica da área com um apanhado dos guias de diversas concessionárias. Posteriormente, simulações computacionais utilizando o programa SimPowerSystems e um sistema teste foram utilizados para que análises estáticas e dinâmicas do problema fossem feitas no intuito de investigar a natureza das variações de tensão e os fatores que influenciam suas magnitudes e durações. Índices para avaliar as variações de tensão foram criados, e um método para obtenção dos mesmos foi proposto. Tal método utiliza apenas ferramentas de análise estática (fluxo de carga) para a obtenção dos índices, evitando o uso de ferramentas dinâmicas (domínio do tempo) reduzindo o custo computacional e financeiro para análise do problema. Em seguida, o mesmo foi aplicado a um sistema que simula uma rede de distribuição real propondo-se a inserção de bancos de capacitores como medida mitigatória para o problema estudado neste trabalho.<br>In recent years, factors such as the restructuring of the electricity sector, the necessity to use different primary energy sources as a way to diversify sources of energy, barriers in the construction of large generating units and transmission lines caused by environmental protection standards, as well as technological advances in the generation of electricity, have caused a considerable increase in the interest for distributed generation. The concept of distributed generation has become very interesting; however, its application can result in poor power quality, if its influence is not well studied. In this context, this document characterizes voltage variations caused by the action of anti-islanding protection of distributed synchronous generators. This problem can be considered a new approach on the impact of distributed generators in power quality, since the cause of voltage variations are typically related load switching, induction motors start-up, short circuits, lines disconnection, etc. To investigate the problem, initially a study was carried out on technical standardization in the area with an overview of various utilities guides. Later, computer simulations using the SimPowerSystems software and a test system were employed for static and dynamic analysis of the problem, aiming at investigating the nature of voltage variations and the main factors that influence their magnitudes and durations. Indices to assess the voltage variations were created, and a method for obtaining them was proposed. This method uses only static approach tools (power flow calculations) to obtain the indices, avoiding the use of dynamic tools (time-domain simulations) and reducing computational and financial costs to analyses the problem. The proposed method was applied to a larger system and the insertion of capacitors bank was proposed as mitigating solution for the problem studied in this work.
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Näslund, Katarina, and Andrea Stafverfeldt. "Energioptimering genom samverkan : en nulägesrapport av sektorkoppling i Sverige." Thesis, KTH, Energiteknik, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-276420.
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För att Sverige ska uppnå de energimål som satts upp i enighet med Agenda 2030, är det av stor vikt att implementera mer förnybara resurser. Sektorkopplingsstrategier är en potentiell åtgärd vilket skulle optimera det svenska energisystemet. På sikt skulle det även kunna frigöra kapacitet, och därmed möjliggöra hantering av en större andel förnybara källor i elnätet. Syftet med den här studien är att bistå med en nulägesrapport av sektorkopplingsetablering i Sverige, med särskild fördjupning i region Gotland. Studien grundas i en omfattande litteraturstudie och kvalitativa intervjuer. Genom att studera tidigare litteratur inom området identifierades tekniker och metoder inom sektorkoppling, vars nuvarande utsträckning i Sverige kartlades. Den fördjupade datainsamlingen för studien var ostrukturerade kvalitativa intervjuer med projektledare och aktörer med relevans för Gotland. Resultatet från studien är en sammanställning av sektorkopplingtekniker samt hur dessa kan bidra till att öka flexibiliteten i energisystemet i allmänhet, och elnätet i synnerhet. Vidare kartlades projekt i Sverige som tillämpar dessa tekniker. Slutsatserna visar på att sektorkoppling redan är etablerat i Sverige, men befinner sig i ett tidigt stadium. Resultatet visade vidare att det krävs engagemang från kunder och aktörer, samt en viss standard i energisystemet för att möjliggöra en framgångsrik tillämpning av sektorkoppling i det svenska energisystemet. Resultaten belyser likväl att en fortsatt etablering av sektorkoppling kan komma att kräva ekonomiska incitament i form av bidrag och satsningar.<br>Including more renewable energy sources in the energy system is of great importance to enable Sweden to achieve its climate goals in unity of Agenda 2030. Sector coupling is a potential strategy for energy optimization, which in time could become a more established method to manage capacity issues, as well as permitting more renewable energy sources in the electricity grid. The purpose of this study is to compile a status report on current sector coupling in Sweden, with additional further investigation of region Gotland. The study is based on a comprehensive literature study as well as data collection through qualitative interviews with relevant stakeholders. Previous research and literature in the field enabled the identification of different technologies and methods relating to sector coupling. Qualitative data was gathered through unstructured interviews with represenatatives from companies and organizations having their focus set on energy planning in the Gotland region. The results consist of an assortment of various sector coupling technologies and their ability to increase the flexibility of the power grid and energy system in Sweden. In addition, several projects with diverse implementation of sector coupling strategies were also being mapped out. In conclusion, it became apparent that sector coupling is only at its earlier stages of implementation in Sweden. Further interest and commitment by customers and businesses is of great importance and needed to enable expansion of sector coupling technologies in Sweden. Moreover, the energy system requires standards, as well as financial incentives to promote further use of sector coupling in society.
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Möbus, Thiago Forell. "Comparação de modelos de previsão de volatilidade com dados diários e intradiários utilizando como função perda a lucratividade no mercado de derivativos." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/70010.
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Desde Markowitz (1952), a volatilidade tem ocupado um papel de grande importância dentro da moderna teoria das finanças. Durante muito tempo, a mensuração da volatilidade tem sido realizada a partir de dados diários. No entanto, a disponibilização de dados intradiários, somada à redução do custo de aquisição destes, tem permitido a criação de modelos baseados nestes dados, o que permite incorporar mais informação, e em teoria, proporcionar previsões mais eficientes em comparação aos modelos que incorporam dados diários apenas. Dessa forma, o objetivo foi verificar se a modelagem da volatilidade a partir da utilização de dados diários é mais eficiente que a modelagem a partir de dados diários em termos de previsão da volatilidade futura. Utilizou-se, para comparar os modelos, a lucratividade de operações estruturadas no mercado de derivativos entre janeiro e abril de 2011. Os resultados demonstram que tantos os modelos baseados em dados diários como intradiarios apresentaram resultados satisfatórios em termos de previsão da volatilidade futura, tendo, entretanto, os modelos intradiários apresentado mais consistentes se comparado aos modelos diários, além de serem mais simples de serem estimados.<br>Since Markowitz (1952), volatility has played a major role in modern finance theory. For a long time, the measurement of volatility has been made from daily data. However, the availability of intraday data, added to reduce of the cost of these has allowed the creation of models based on these data, which allows to incorporate more information, and, in theory, provide more efficient forecasts compared to models that incorporate daily data only. Thus, the objective was to verify if the modeling of volatility from the use of daily data is more efficient than the model from daily data in terms of forecasting future volatility. Was used to compare the models, the profitability of structured transactions in the derivatives market between January and April 2011. The results show that both daily and intraday models showed satisfactory results in terms of forecasting future volatility, with, however, higher consistent of intraday models compared to daily models, being simpler to estimated them too.
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Eriksson, Pernilla, and Martin Sundell. "EXPLORING MARKET FORCES FOR TRANSMISSION EXPANSION AND GRID STORAGE INTEGRATION : A technical-economic thesis about variation moderators for intermittent renewable power generation in the developed country of Sweden and the developing country of China." Thesis, Mälardalens högskola, Akademin för ekonomi, samhälle och teknik, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-28560.
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Aramane, Pranav. "Stability Analysis and Design of a Tracking Filter for Variable Frequency Applications." UKnowledge, 2018. https://uknowledge.uky.edu/ece_etds/117.
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The work presented in this thesis is a frequency adaptive tracking filter that can be used in exact tracking of power frequencies and rejection of unwanted harmonics introduced during power disturbances. The power synchronization process includes power converters and other equipment that have many non-linear components that introduce unwanted harmonics. This new design is motivated by the requirement of a filter that can filter all the harmonics and exactly track a rapidly varying fundamental frequency with little time delay and phase error. This thesis analyzes the proposed filter mathematically based on Lyapunov theory and simulations are presented to show the performance of the design in rapid frequency variations.
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Banerjee, Aritra. "Design of digitally assisted adaptive analog and RF circuits and systems." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/52919.
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With more and more integration of analog and RF circuits in scaled CMOS technologies, process variation is playing a critical role which makes it difficult to achieve all the performance specifications across all the process corners. Moreover, at scaled technology nodes, due to lower voltage and current handling capabilities of the devices, they suffer from reliability issues that reduce the overall lifetime of the system. Finally, traditional static style of designing analog and RF circuits does not result in optimal performance of the system. A new design paradigm is emerging toward digitally assisted analog and RF circuits and systems aiming to leverage digital correction and calibration techniques to detect and compensate for the manufacturing imperfections and improve the analog and RF performance offering a high level of integration. The objective of the proposed research is to design digital friendly and performance tunable adaptive analog/RF circuits and systems with digital enhancement techniques for higher performance, better process variation tolerance, and more reliable operation and developing strategy for testing the proposed adaptive systems. An adaptation framework is developed for process variation tolerant RF systems which has two parts – optimized test stimulus driven diagnosis of individual modules and power optimal system level tuning. Another direct tuning approach is developed and demonstrated on a carbon nanotube based analog circuit. An adaptive switched mode power amplifier is designed which is more digital-intensive in nature and has higher efficiency, improved reliability and better process resiliency. Finally, a testing strategy for adaptive RF systems is shown which reduces test time and test cost compared to traditional testing.