Relevant bibliographies by topics / Prefetch techniques

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Prefetch techniques'

Author: Grafiati
Published: 10 December 2022
Last updated: 31 July 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Prefetch techniques.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Prefetch techniques"

1

VERMA, SANTHOSH, and DAVID M. KOPPELMAN. "THE INTERACTION AND RELATIVE EFFECTIVENESS OF HARDWARE AND SOFTWARE DATA PREFETCH." Journal of Circuits, Systems and Computers 21, no. 02 (2012): 1240002. http://dx.doi.org/10.1142/s0218126612400026.

Full text
Abstract:
A major performance limiter in modern processors is the long latencies caused by data cache misses. Both compiler- and hardware-based prefetching schemes help hide these latencies and so improve performance. Compiler techniques infer memory access patterns through code analysis, and insert appropriate prefetch instructions. Hardware prefetching techniques work independently from the compiler by monitoring an access stream, detecting patterns in this stream and issuing prefetches based on these patterns. This paper looks at the interplay between compiler and hardware architecture-based prefetch
APA, Harvard, Vancouver, ISO, and other styles
2

Srivastava, Swapnita, and P. K. Singh. "ADDP: The Data Prefetching Protocol for Monitoring Capacity Misses." ADCAIJ: Advances in Distributed Computing and Artificial Intelligence Journal 14 (April 11, 2025): e31782. https://doi.org/10.14201/adcaij.31782.

Full text
Abstract:
Prefetching is essential to minimizing the number of misses in cache and improving processor performance. Many prefetchers have been proposed, including simple but highly effective stream-based prefetchers and prefetchers that predict complex access patterns based on structures such as history buffers and bit vectors. However, many cache misses still occur in many applications. After analyzing the various techniques in Instruction and Data Prefetcher, several key features were extracted which impact system performance. Data prefetching is an essential technique used in all commercial processor
APA, Harvard, Vancouver, ISO, and other styles
3

Deb, Dipika, and John Jose. "ZPP: A Dynamic Technique to Eliminate Cache Pollution in NoC based MPSoCs." ACM Transactions on Embedded Computing Systems 22, no. 5s (2023): 1–25. http://dx.doi.org/10.1145/3609113.

Full text
Abstract:
Data prefetching efficiently reduces the memory access latency in NUCA architectures as the Last Level Cache (LLC) is shared and distributed across multiple cores. But cache pollution generated by prefetcher reduces its efficiency by causing contention for shared resources such as LLC and the underlying network. The paper proposes Zero Pollution Prefetcher (ZPP) that eliminates cache pollution for NUCA architecture. For this purpose, ZPP uses L1 prefetcher and places the prefetched blocks in the data locations of LLC where modified blocks are stored. Since modified blocks in LLC are stale and
APA, Harvard, Vancouver, ISO, and other styles
4

Alves, Ricardo, Stefanos Kaxiras, and David Black-Schaffer. "Early Address Prediction." ACM Transactions on Architecture and Code Optimization 18, no. 3 (2021): 1–22. http://dx.doi.org/10.1145/3458883.

Full text
Abstract:
Achieving low load-to-use latency with low energy and storage overheads is critical for performance. Existing techniques either prefetch into the pipeline (via address prediction and validation) or provide data reuse in the pipeline (via register sharing or L0 caches). These techniques provide a range of tradeoffs between latency, reuse, and overhead. In this work, we present a pipeline prefetching technique that achieves state-of-the-art performance and data reuse without additional data storage, data movement, or validation overheads by adding address tags to the register file. Our addition
APA, Harvard, Vancouver, ISO, and other styles
5

Bishwa Ranjan Roy, Purnendu Das, Nurulla Mansur Barbhuiya,. "PP-Bridge: Establishing a Bridge between the Prefetching and Cache Partitioning." International Journal on Recent and Innovation Trends in Computing and Communication 11, no. 9 (2023): 897–906. http://dx.doi.org/10.17762/ijritcc.v11i9.8982.

Full text
Abstract:
— Modern computer processors are equipped with multiple cores, each boasting its own dedicated cache memory, while collectively sharing a generously sized Last Level Cache (LLC). To ensure equitable utilization of the LLC space and bolster system security, partitioning techniques have been introduced to allocate the shared LLC space among the applications running on different cores. This partition dynamically adapts to the requirements of these applications. Prefetching plays a vital role in enhancing cache performance by proactively loading data into the cache before it get requested explicit
APA, Harvard, Vancouver, ISO, and other styles
6

Hariharan, I., and M. Kannan. "Efficient Use of On-Chip Memories and Scheduling Techniques to Eliminate the Reconfiguration Overheads in Reconfigurable Systems." Journal of Circuits, Systems and Computers 28, no. 14 (2019): 1950246. http://dx.doi.org/10.1142/s0218126619502463.

Full text
Abstract:
Modern embedded systems are packed with dedicated Field Programmable Gate Arrays (FPGAs) to accelerate the overall system performance. However, the FPGAs are susceptible to reconfiguration overheads. The reconfiguration overheads are mainly because of the configuration data being fetched from the off-chip memory at run-time and also due to the improper management of tasks during execution. To reduce these overheads, our proposed methodology mainly focuses on the prefetch heuristic, reuse technique, and the available memory hierarchy to provide an efficient mapping of tasks over the available m
APA, Harvard, Vancouver, ISO, and other styles
7

Liang, Ye. "Big Data Storage Method in Wireless Communication Environment." Advanced Materials Research 756-759 (September 2013): 899–904. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.899.

Full text
Abstract:
Big data phenomenon refers to the practice of collection and processing of very large data sets and associated systems and algorithms used to analyze these massive data sets. Big data service is very attractive in the field of wireless communication environment, especially when we face the spatial applications, which are typical applications of big data. Because of the complexity to ingest, store and analyze geographical information data, this paper reflects on a few of the technical problems presented by the exploration of big data, and puts forward an effective storage method in wireless com
APA, Harvard, Vancouver, ISO, and other styles
8

NATARAJAN, RAGAVENDRA, VINEETH MEKKAT, WEI-CHUNG HSU, and ANTONIA ZHAI. "EFFECTIVENESS OF COMPILER-DIRECTED PREFETCHING ON DATA MINING BENCHMARKS." Journal of Circuits, Systems and Computers 21, no. 02 (2012): 1240006. http://dx.doi.org/10.1142/s0218126612400063.

Full text
Abstract:
For today's increasingly power-constrained multicore systems, integrating simpler and more energy-efficient in-order cores becomes attractive. However, since in-order processors lack complex hardware support for tolerating long-latency memory accesses, developing compiler technologies to hide such latencies becomes critical. Compiler-directed prefetching has been demonstrated effective on some applications. On the application side, a large class of data centric applications has emerged to explore the underlying properties of the explosively growing data. These applications, in contrast to trad
APA, Harvard, Vancouver, ISO, and other styles
9

T.M, Veeragangadhara swamy, and Raju G.T. "A Novel Prefetching Technique through Frequent Sequential Patterns from Web Usage Data." COMPUSOFT: An International Journal of Advanced Computer Technology 04, no. 06 (2015): 1826–36. https://doi.org/10.5281/zenodo.14785813.

Full text
Abstract:
Frequent sequential patterns (fsp) from web usage data (wud) are very important for analyzing and understanding users behavior to improve the quality of services offered by the world wide web(www). Web prefetching is one of the techniques for reducing the web latency there by improve the web retrieval process. This technique makes use of prefetching rules that are derived from fsps. In this paper, we explore the different fsp mining algorithms such as spm, fp growth, and spade for extraction of fsps from wud of an academic website for a period that varies from weekly to quarterly. Performance
APA, Harvard, Vancouver, ISO, and other styles
10

Li, Haoyu, Qizhi Chen, Yixin Zhang, Tong Yang, and Bin Cui. "Stingy sketch." Proceedings of the VLDB Endowment 15, no. 7 (2022): 1426–38. http://dx.doi.org/10.14778/3523210.3523220.

Full text
Abstract:
Recording the frequency of items in highly skewed data streams is a fundamental and hot problem in recent years. The literature demonstrates that sketch is the most promising solution. The typical metrics to measure a sketch are accuracy and speed, but existing sketches make only trade-offs between the two dimensions. Our proposed solution is a new sketch framework called Stingy sketch with two key techniques: Bit-pinching Counter Tree ( BCTree ) and Prophet Queue ( PQueue ) which optimizes both the accuracy and speed. The key idea of BCTree is to split a large fixed-size counter into many sma
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "Prefetch techniques"

1

Chang, Nelson Yen-Chung, and 張彥中. "Cache Prefetch Techniques and Bus Bridge Design in SOC." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/01054116522540066658.

Full text
Abstract:
碩士<br>國立交通大學<br>電子工程系<br>90<br>Cache prefetching has long been known in reducing cache miss rate, and in hiding memory access latencies seen by the processor in a processor-based system. This provides a chance to implement a smaller cache with prefetch mechanism to achieve same miss rate with larger cache without prefetching, hence reducing the cache hardware cost. Though reducing the miss rate improves the performance of a cache, the extra prefetch memory requests increases the overall system bus traffics. The increased bus traffic sometimes diminishes the overall performance of a
APA, Harvard, Vancouver, ISO, and other styles
2

Jen, Hsung, and 任軒. "Reconfiguration Overhead Reduction Using Prefetch and Merge Techniques in Run-Time Reconfigurable System." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/21085391635759437079.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Huang, Hsuan-Woei, and 黃宣偉. "A Study on Prefetch and Compiler Assistant Techniques for Clustering Multiprocessor System Design and Implementation of Its Simulation and Evaluation Environment." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/20226792088898404435.

Full text
Abstract:
碩士<br>國立交通大學<br>資訊工程學系<br>86<br>Recently, shared-memory multiprocessor systems have become one of the design trends in computer system architectures. As the increasingly need of computation, multiprocessor system with more processors on it becomes an unavoidable trend. Thus, clustering multiprocessor system has indeed played an important role due to its high scalability and data locality. We had developed a simulation and evaluation environment for clustering multiprocessor system, which ai
APA, Harvard, Vancouver, ISO, and other styles
4

Cai, Jie. "Region-based techniques for modeling and enhancing cluster OpenMP performance." Phd thesis, 2011. http://hdl.handle.net/1885/8865.

Full text
Abstract:
Cluster OpenMP enables the use of the OpenMP shared memory programming clusters. Intel has released a cluster OpenMP implementation called Intel Cluster OpenMP (CLOMP). While this offers better programmability than message passing alternatives such as the Message Passing Interface (MPI), such convenience comes with overheads resulting from having to maintain the consistency of underlying shared memory abstractions. CLOMP is no exception. This thesis introduces models for understanding these overheads of cluster OpenMP implementations like CLOMP and proposes techniques for enhancing their perfo
APA, Harvard, Vancouver, ISO, and other styles

Book chapters on the topic "Prefetch techniques"

1

Hong, Maria, Euisun Kang, Sungmin Um, Dongho Kim, and Younghwan Lim. "A Transcode and Prefetch Technique of Multimedia Presentations for Mobile Terminals." In Computational Science and Its Applications – ICCSA 2004. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-24707-4_8.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Gupta, Ajay Kumar, and Udai Shanker. "An Efficient Markov Chain Model Development based Prefetching in Location-Based Services." In Privacy and Security Challenges in Location Aware Computing. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-7756-1.ch005.

Full text
Abstract:
A quite significant issue with the current location-based services application is to securely store information for users on the network in order to quickly access the data items. One way to do this is to store data items that have a high likelihood of subsequent request. This strategy is known as proactive caching or prefetching. It is a technique in which selected information is cached before it is actually needed. In comparison, past constructive caching strategies showed high data overhead in terms of computing costs. Therefore, with the use of Markov chain model, the aim of this work is t
APA, Harvard, Vancouver, ISO, and other styles
3

Huang, Shi-Ming, Binshan Lin, and Qun-Shi Deng. "Intelligent Cache Management for Mobile Data Warehouse Systems." In Data Warehousing and Mining. IGI Global, 2008. http://dx.doi.org/10.4018/978-1-59904-951-9.ch088.

Full text
Abstract:
This research proposes an intelligent cache mechanism for a data warehouse system in a mobile environment. Because mobile devices can often be disconnected from the host server and due to the low bandwidth of wireless networks, it is more efficient to store query results from a mobile device in the cache. For more personal use of mobile devices, we use a data mining technique to determine the pattern from a record of previous queries. Then the data, which will be retrieved by the user, are prefetched and stored in the cache, thus, improving the query efficiency. We demonstrate the feasibility
APA, Harvard, Vancouver, ISO, and other styles
4

Macmaster, Neil. "The Arzew Camp." In War in the Mountains. Oxford University Press, 2020. http://dx.doi.org/10.1093/oso/9780198860211.003.0019.

Full text
Abstract:
The chapter examines the success of the forms of psychological warfare deployed during Opération Pilote. A key element of Servier’s plan was to recruit peasants to undertake a crash training programme in the COIN centre at Arzew, so that they could be secretly reinserted in the douars to act as future political leaders. The first cohort proved to be of mediocre ability, and their placement in the douars, known to the FLN, proved to be perilous. The army turned to other techniques of mass brainwashing of the rural population, who were either subjected to propaganda teams or, at Warnier in the C
APA, Harvard, Vancouver, ISO, and other styles
5

Prakash, Amit. "Imperial Sentinels." In Empire on the Seine. Oxford University Press, 2022. http://dx.doi.org/10.1093/oso/9780192898876.003.0005.

Full text
Abstract:
In 1958, the new Prefect of Police, Maurice Papon, grew and coordinated the constellation of police services dedicated to Algerians but often swept up Tunisians, Moroccans, and, in some cases, nationals from South American countries. The flagrant, often violent, racialized surveillance of Paris was conceived by police officials as necessary to preserve the empire. In effect, the Paris police acted as sentinels on the imperial ramparts, their activity characterized by growing militarization and the introduction counterinsurgency techniques borne of the wars in Indo-China and Algeria. In additio
APA, Harvard, Vancouver, ISO, and other styles
6

House, Jim, and Neil Macmaster. "Papon and the Colonial Origins of Police Violence." In Paris 1961: Algerians, State Terror, and Memory. Oxford University PressOxford, 2006. http://dx.doi.org/10.1093/oso/9780199247257.003.0003.

Full text
Abstract:
Abstract In March 1958 the French government, faced with a crisis in the Paris police force, flew Maurice Papon from Algeria into the capital to provide strong leadership to the Prefecture of Police and to accelerate the battle against the Front de libération nationale. During the remaining four years of the Algerian War Papon was the architect of a novel and far-reaching police and intelligence system. The purpose of this chapter is to examine the origins of this ‘Papon System’ by following the career of the Prefect from Vichy through the politically unstable years of the Fourth Republic. The
APA, Harvard, Vancouver, ISO, and other styles
7

Guo Yong Zhen, Ramamohanarao Kotagiri, and Park Laurence A. F. "Web Page Prediction Based on Conditional Random Fields." In Frontiers in Artificial Intelligence and Applications. IOS Press, 2008. https://doi.org/10.3233/978-1-58603-891-5-251.

Full text
Abstract:
Web page prefetching is used to reduce the access latency of the Internet. However, if most prefetched Web pages are not visited by the users in their subsequent accesses, the limited network bandwidth and server resources will not be used efficiently and may worsen the access delay problem. Therefore, it is critical that we have an accurate prediction method during prefetching. Conditional Random Fields (CRFs), which are popular sequential learning models, have already been successfully used for many Natural Language Processing (NLP) tasks such as POS tagging, name entity recognition (NER) an
APA, Harvard, Vancouver, ISO, and other styles
8

Fleming, James R. "Joseph Fourier’s Theory of Terrestrial Temperatures." In Historical Perspectives on Climate Change. Oxford University Press, 1998. http://dx.doi.org/10.1093/oso/9780195078701.003.0010.

Full text
Abstract:
The concept of the greenhouse effect has yet to receive adequate historical attention. Although most writing ahout the subject is concerned with current scientific or policy issues, a small but growing fraction of the literature contains at least some historical material, which, as this chapter shows for the case of Joseph Fourier, is largely unreliable. Jean Baptiste Joseph Fourier is best known today for his Fourier series, a widely used mathematical technique in which complex functions can be represented by a series of sines and cosines. He is known among physicists and historians of physic
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Prefetch techniques"

1

Heirman, Wim, Kristof Du Bois, Yves Vandriessche, Stijn Eyerman, and Ibrahim Hur. "Near-side prefetch throttling." In PACT '18: International conference on Parallel Architectures and Compilation Techniques. ACM, 2018. http://dx.doi.org/10.1145/3243176.3243181.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Cai, Jie, Peter E. Strazdins, and Alistair P. Rendell. "Region-Based Prefetch Techniques for Software Distributed Shared Memory Systems." In 2010 10th IEEE/ACM International Conference on Cluster, Cloud and Grid Computing. IEEE, 2010. http://dx.doi.org/10.1109/ccgrid.2010.16.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Holtryd, Nadja Ramhoj, Madhavan Manivannan, Per Stenstrom, and Miquel Pericas. "CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling." In 2021 30th International Conference on Parallel Architectures and Compilation Techniques (PACT). IEEE, 2021. http://dx.doi.org/10.1109/pact52795.2021.00023.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Qu, Wenxin, Xiaoya Fan, Ying Hu, Yong Xia, and Fuyuan Hu. "New Prefetch Technique Design for L2 Cache." In TENCON 2006 - 2006 IEEE Region 10 Conference. IEEE, 2006. http://dx.doi.org/10.1109/tencon.2006.344002.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Choi, Hong Jun, Dong Oh Son, Cheol Hong Kim, and Jong Myron Kim Kim. "A Novel Prefetch Technique for High Performance Embedded System." In 2014 International Conference on IT Convergence and Security (ICITCS). IEEE, 2014. http://dx.doi.org/10.1109/icitcs.2014.7021713.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Yuan He, Hiroshi Sasaki, Shinobu Miwa, and Hiroshi Nakamura. "TCPT: thread criticality-driven prefetcher throttling." In 22nd International Conference on Parallel Architectures and Compilation Techniques (PACT). IEEE, 2013. http://dx.doi.org/10.1109/pact.2013.6618828.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Panda, Biswabandan, and Shankar Balachandran. "TCPT - Thread criticality-driven prefetcher throttling." In 2013 22nd International Conference on Parallel Architectures and Compilation Techniques (PACT). IEEE, 2013. http://dx.doi.org/10.1109/pact.2013.6618835.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Mohapatra, Shubdeep, and Biswabandan Panda. "Drishyam: An Image is Worth a Data Prefetcher." In 2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT). IEEE, 2023. http://dx.doi.org/10.1109/pact58117.2023.00013.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Cai, Jie, and Peter E. Strazdins. "An Accurate Prefetch Technique for Dynamic Paging Behaviour for Software Distributed Shared Memory." In 2012 41st International Conference on Parallel Processing (ICPP). IEEE, 2012. http://dx.doi.org/10.1109/icpp.2012.16.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Irie, Hidetsugu, Takefumi Miyoshi, Goki Honjo, Kei Hiraki, and Tsutomu Yoshinaga. "CCCPO: Robust Prefetcher Optimization Technique Based on Cache Convection." In 2011 Second International Conference on Networking and Computing (ICNC). IEEE, 2011. http://dx.doi.org/10.1109/icnc.2011.26.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'Prefetch techniques' for particular source types:
Journal articles
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography