Relevant bibliographies by topics / Programmable array logic

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Programmable array logic'

Author: Grafiati
Published: 4 June 2021
Last updated: 16 July 2025

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Journal articles on the topic "Programmable array logic"

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Kim, Kyosun, Sangho Shin, and Sung-Mo Kang. "Field Programmable Stateful Logic Array." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30, no. 12 (2011): 1800–1813. http://dx.doi.org/10.1109/tcad.2011.2165067.

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Marchand, J. F. P. "An alterable programmable logic array." IEEE Journal of Solid-State Circuits 20, no. 5 (1985): 1061–66. http://dx.doi.org/10.1109/jssc.1985.1052437.

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Kim, Kyosun. "Fabric Mapping and Placement of Field Programmable Stateful Logic Array." Journal of the Institute of Electronics and Information Engineers 49, no. 12 (2012): 209–18. http://dx.doi.org/10.5573/ieek.2012.49.12.209.

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TAYARI, MAHSHID, and MOHAMMAD ESHGHI. "DESIGN OF 3-INPUT REVERSIBLE PROGRAMMABLE LOGIC ARRAY." Journal of Circuits, Systems and Computers 20, no. 02 (2011): 283–97. http://dx.doi.org/10.1142/s0218126611007256.

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In this paper, for the first time a design for a Reversible Programmable Logic Array (RPLA) is introduced. This is the first RPLA design because the reversible PLA design, presented in previous research, is not a programmable circuit. In our presented RPLAs, four reversible AND array designs with different specifications are proposed. A reversible OR array, which can be programmed to generate any Boolean function, is also designed. This reversible and programmable OR array is also cascadable. That is, it produces a copy of inputted midterms at its outputs to be fed to another OR array in order
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Hiluf, Dawit. "All optical programmable logic array (PLA)." Journal of Physics: Conference Series 987 (March 2018): 012033. http://dx.doi.org/10.1088/1742-6596/987/1/012033.

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Li, Yao, and George Eichmann. "Nonabsorptive binary optical programmable logic array." Optics Communications 76, no. 2 (1990): 107–10. http://dx.doi.org/10.1016/0030-4018(90)90302-a.

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Hu, T. C., and Y. S. Kuo. "Graph folding and programmable logic array." Networks 17, no. 1 (1987): 19–37. http://dx.doi.org/10.1002/net.3230170103.

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Pradeep, Singla. "POWER GATING STRUCTURE FOR REVERSIBLE PROGRAMMABLE LOGIC ARRAY." Electrical & Computer Engineering: An International Journal (ECIJ) 4, no. 3 (2015): 01–14. https://doi.org/10.5281/zenodo.3568776.

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Throughout the world, the numbers of researchers or hardware designer struggle for the reducing of power dissipation in low power VLSI systems. This paper presented an idea of using the power gating structure for reducing the sub threshold leakage in the reversible system. This concept presented in the paper is entirely new and presented in the literature of reversible logics. By using the reversible logics for the digital systems, the energy can be saved up to the gate level implementation. But at the physical level designing of the reversible logics by the modern CMOS technology the heat or
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Dettmer, Roger. "User programmable logic: chasing the gate array." IEE Review 36, no. 5 (1990): 181. http://dx.doi.org/10.1049/ir:19900074.

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Mottalib, M. A., R. V. S. K. Prasad, and P. Dasgupta. "Function dependent fully testable programmable logic array." Electronics Letters 27, no. 6 (1991): 495. http://dx.doi.org/10.1049/el:19910311.

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Dissertations / Theses on the topic "Programmable array logic"

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Pearce, Maureen. "Logic synthesis for programmable devices." Thesis, University of Bristol, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.357911.

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Han, Yi. "Development of nonlinear reconfigurable control of reconfigurable plants using the FPGA technology." Thesis, [S.l. : s.n.], 2008. http://dk.cput.ac.za/cgi/viewcontent.cgi?article=1011&context=td_cput.

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Malik, Usama Computer Science &amp Engineering Faculty of Engineering UNSW. "Configuration encoding techniques for fast FPGA reconfiguration." Awarded by:University of New South Wales. School of Computer Science and Engineering, 2006. http://handle.unsw.edu.au/1959.4/26212.

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This thesis examines the problem of reducing reconfiguration time of an island-style FPGA at its configuration memory level. The approach followed is to examine configuration encoding techniques in order to reduce the size of the bitstream that must be loaded onto the device to perform a reconfiguration. A detailed analysis of a set of benchmark circuits on various island-style FPGAs shows that a typical circuit randomly changes a small number of bits in the {\it null} or default configuration state of the device. This feature is exploited by developing efficient encoding schemes for configur
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Koh, Shannon Computer Science &amp Engineering Faculty of Engineering UNSW. "Generating the communication infrastracture for module-based dynamic reconfiguration of FPGas." Publisher:University of New South Wales. Computer Science & Engineering, 2008. http://handle.unsw.edu.au/1959.4/41418.

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Current approaches to supporting module-based FPGA reconfiguration focus on various aspects and sub-problems in the area but do not combine to form a coherent, top-down methodology that factors low-level device parameters into every step of the design flow. This thesis proposes such a top-down methodology from application specification to low-level implementation, centered around examining the problem of generating a point-to-point communications infrastructure to support the changing interfaces of dynamically placed modules. Low-level implementation parameters are considered at every stage to
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Wood, Christopher Landon. "Runtime partial FPGA reconfiguration." Thesis, Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15051.

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Galindo, Juan Manuel. "A novel partial reconfiguration methodology for FPGAs of multichip systems /." Online version of thesis, 2008. http://hdl.handle.net/1850/7784.

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Rajagopalan, Kamal. "An FPGA architecture for improved arithmetic performance /." St. Lucia, Qld, 2001. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe16460.pdf.

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Sharma, Akshay. "Place and route techniques for FPGA architecture advancement /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6108.

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Treuer, Robert. "A new design of built-in self-testing programmable logic arrays with high fault coverage and low overhead /." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63215.

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Mak, Wai-kei. "Partitioning and routing for multi-FPGA systems /." Digital version accessible at:, 1998. http://wwwlib.umi.com/cr/utexas/main.

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Books on the topic "Programmable array logic"

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1955-, Trimberger Stephen, ed. Field-programmable gate array technology. Kluwer Academic Publishers, 1994.

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Murgai, Rajeev. Logic synthesis for field-programmable gate arrays. Kluwer Academic Publishers, 1995.

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Inc, Xilinx. The programmable gate array data book. XILINX, Inc., 1988.

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ACM International Symposium on Field-Programmable Gate Arrays (4th 1996 Monterey, Calif.). FPGA '96: 1996 ACM Fourth International Symposium on Field Programmable Gate Arrays : February 11-13, 1996, Monterey Beach Hotel, Monterey, California, USA. ACM Press, 1996.

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Ukeiley, Richard Larry. Field programmable gate arrays (FPGAs): The 3000 series. PTR Prentice Hall, 1993.

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F, Whapshott G., ed. Programmable logic PLDs and FPGAs. Macmillan, 1997.

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ACM, International Symposium on Field-Programmable Gate Arrays (17th 2009 Monterey Calif ). FPGA'09: Proceedings of the Seventeenth ACM SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, California, USA, February 22-24, 2009. Association for Computing Machinery, 2009.

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ACM, International Symposium on Field-Programmable Gate Arrays (12th 2004 Monterey Calif ). FPGA 2004: ACM/SIGDA Twelfth ACM International Symposium on Field-Programmable Gate Arrays, Monterey Beach Hotel, Monterey, California, USA : February 22-24, 2004. Association for Computing Machinery, 2004.

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ACM, International Symposium on Field-Programmable Gate Arrays (7th 1999 Monterey Calif ). FPGA '99: ACM/SIGDA International Symposium on Field Programmable Gate Arrays. ACM Press, 1999.

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ACM, International Symposium on Field-Programmable Gate Arrays (3rd 1995 Monterey Calif ). FPGA '95: 1995 ACM Third International Sympsosium on Field-Programmable Gate Arrays : February 12-14, 1995, Monterey Marriott, Monterey, California, USA. ACM Press, 1995.

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Book chapters on the topic "Programmable array logic"

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Weik, Martin H. "programmable logic array." In Computer Science and Communications Dictionary. Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_14866.

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Hartmann, Robert. "Erasable Programmable Logic Devices." In Field-Programmable Gate Array Technology. Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2742-8_4.

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Akter, Fatema, Tamanna Tabassum, and Mohammed Nasir Uddin. "Programmable Logic Array in Quantum Computing." In Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering. Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-34622-4_35.

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Bramer, B., D. Chauhan, M. K. Ibrahim, and A. Aggoun. "Virtual radix array processors (V-RaAP)." In Field-Programmable Logic and Applications. Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/3-540-63465-7_240.

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Jebelean, Tudor. "Auto-configurable array for GCD computation." In Field-Programmable Logic and Applications. Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/3-540-63465-7_251.

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Khawam, Sami, Tughrul Arslan, and Fred Westall. "Domain-Specific Reconfigurable Array for Distributed Arithmetic." In Field Programmable Logic and Application. Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-45234-8_139.

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Chaudhuri, Anjit Sekhar, Peter Y. K. Cheung, and Wayne Luk. "A reconfigurable data-localised array for morphological algorithms." In Field-Programmable Logic and Applications. Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/3-540-63465-7_239.

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Xicotencatl, Juan M., and Miguel Arias-Estrada. "FPGA Based High Density Spiking Neural Network Array." In Field Programmable Logic and Application. Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-45234-8_118.

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Sidahao, Nalin. "Optimized Field Programmable Gate Array Based Function Evaluation." In Field Programmable Logic and Application. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30117-2_171.

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Ristimäki, T., and J. Nurmi. "Virtualizing the Dimensions of a Coarse-Grained Reconfigurable Array." In Field Programmable Logic and Application. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30117-2_146.

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Conference papers on the topic "Programmable array logic"

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Yang, Geng, Jie Lei, Zhenman Fang, et al. "SA4: A Comprehensive Analysis and Optimization of Systolic Array Architecture for 4-bit Convolutions." In 2024 34th International Conference on Field-Programmable Logic and Applications (FPL). IEEE, 2024. http://dx.doi.org/10.1109/fpl64840.2024.00036.

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Derstine, M. W., W. R. Babbitt, J. A. Bell, and B. A. Capron. "S-SEED based programmable logic array." In OSA Annual Meeting. Optica Publishing Group, 1991. http://dx.doi.org/10.1364/oam.1991.fdd2.

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A promising candidate for logic arrays in optical cellular logic image processors is the symmetric self-electrooptic effect device (S-SEED). We describe the operation of an 8 × 16 array of S-SEEDs as programmable logic gates operating using the time sequential scheme described by Lentine et al.1 with a space multiplexed beam combination technique.2 The programmable gate operates at an effective rate >10 kHz which is limited by the speed of the computer drive, and >80% of the gates operate correctly simultaneously. The beam combination scheme used in this system requires that several diff
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Ichioka, Yoshiki. "Optical programmable array logic." In Critical Review Collection, edited by R. Athale. SPIE, 1990. http://dx.doi.org/10.1117/12.2283577.

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Li, Yao, Andrew Kostrzewski, Dai Hyun Kim, and George Eichmann. "Compact free-space optical programmable logic array." In OSA Annual Meeting. Optica Publishing Group, 1988. http://dx.doi.org/10.1364/oam.1988.mt6.

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To implement a parallel optical digital computer, in addition to the two variables, multiple variable optical logic gates are needed. One way to implement a generalized multiple variable optical logic device is to use an optical programmable logic array. We propose a new method to realize a medium scale, compact, and free-space optical programmable logic array. Using either a 2-D or an array of 1-D optical spatial light modulators inside a lens-based multiple-beam path cavity, an array of optical multiple variable logic product (AND gate) term is generated. This device, together with a program
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Rajendran, Jeyavijayan, Harika Manem, Ramesh Karri, and Garrett S. Rose. "Memristor based programmable threshold logic array." In 2010 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). IEEE, 2010. http://dx.doi.org/10.1109/nanoarch.2010.5510933.

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Krestinskaya, Olga, Akshay Kumar Maan, and Alex Pappachen James. "Programmable Memristive Threshold Logic Gate Array." In 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). IEEE, 2018. http://dx.doi.org/10.1109/apccas.2018.8605646.

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Zeise, EE, and P. S. Guilfoyle. "Programmable Emulation with the Optical Reconfigurable Logic Array." In Optical Computing. Optica Publishing Group, 1989. http://dx.doi.org/10.1364/optcomp.1989.tui1.

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Walker, A. C., R. G. A. Craig, D. J. McKnight, et al. "Design and Construction of a Programmable Optical 16x16 Array Processor." In Optical Computing. Optica Publishing Group, 1991. http://dx.doi.org/10.1364/optcomp.1991.tua4.

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There have been a number of significant advances in digital optical computing research over recent years. Experimental demonstrations of optical restoring logic1, the lock-and clock control of data flow2, a programmable optical logic unit3, optical switching networks4, and parallel logic modules5 have shown that the basic building blocks for a parallel digital optical computing system now exist. This paper describes recent work carried out at Heriot-Watt University in which such a demonstration optical processor has been constructed.
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Donghyeok Bae, Jaehong Park, Maengkyu Kim, Yongsik Jeong, and Kyounghoon Yang. "RTD-based reconfigurable logic gates for programmable logic array applications." In 2016 Compound Semiconductor Week (CSW) [Includes 28th International Conference on Indium Phosphide & Related Materials (IPRM) & 43rd International Symposium on Compound Semiconductors (ISCS)]. IEEE, 2016. http://dx.doi.org/10.1109/iciprm.2016.7528573.

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Perin, Guilherme, Daniel G. Mesquita, Fernando L. Herrmann, and Joao Baptista Martins. "Montgomery modular multiplication on reconfigurable hardware: Fully systolic array vs parallel implementation." In VI Southern Programmable Logic Conference (SPL). IEEE, 2010. http://dx.doi.org/10.1109/spl.2010.5483003.

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Reports on the topic "Programmable array logic"

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Trotter, J. D., and A. K. R. Naini. Bulk CMOS VLSI Technology Studies. Part 1. Scalable CMOS Design Rules. Part 2. CMOS Approaches to PLA (Programmable Logic Array) Design. Defense Technical Information Center, 1985. http://dx.doi.org/10.21236/ada158367.

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Schafer, Ingo. Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping. Portland State University Library, 2000. http://dx.doi.org/10.15760/etd.1338.

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Tirumalai, Parthasarathy, and Jon T. Butler. Analysis of Minimization Algorithms for Multiple-Valued Programmable Logic Arrays. Defense Technical Information Center, 1988. http://dx.doi.org/10.21236/ada605376.

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Rose, Jonathan, Robert J. Francis, Paul Chow, and David Lewis. The Effect of Logic Block Complexity on Area of Programmable Gate Arrays. Defense Technical Information Center, 1987. http://dx.doi.org/10.21236/ada207172.

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Wu, Lifei. Minimization of Permuted Reed-Muller Trees and Reed-Muller Trees for Cellular Logic Programmable Gate Arrays. Portland State University Library, 2000. http://dx.doi.org/10.15760/etd.6629.

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