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Journal articles on the topic 'Programmable array logic'

Author: Grafiati

Published: 4 June 2021

Last updated: 29 July 2024

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1

Kim, Kyosun, Sangho Shin, and Sung-Mo Kang. "Field Programmable Stateful Logic Array." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30, no. 12 (December 2011): 1800–1813. http://dx.doi.org/10.1109/tcad.2011.2165067.

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2

Marchand, J. F. P. "An alterable programmable logic array." IEEE Journal of Solid-State Circuits 20, no. 5 (October 1985): 1061–66. http://dx.doi.org/10.1109/jssc.1985.1052437.

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3

Kim, Kyosun. "Fabric Mapping and Placement of Field Programmable Stateful Logic Array." Journal of the Institute of Electronics and Information Engineers 49, no. 12 (December 25, 2012): 209–18. http://dx.doi.org/10.5573/ieek.2012.49.12.209.

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4

TAYARI, MAHSHID, and MOHAMMAD ESHGHI. "DESIGN OF 3-INPUT REVERSIBLE PROGRAMMABLE LOGIC ARRAY." Journal of Circuits, Systems and Computers 20, no. 02 (April 2011): 283–97. http://dx.doi.org/10.1142/s0218126611007256.

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In this paper, for the first time a design for a Reversible Programmable Logic Array (RPLA) is introduced. This is the first RPLA design because the reversible PLA design, presented in previous research, is not a programmable circuit. In our presented RPLAs, four reversible AND array designs with different specifications are proposed. A reversible OR array, which can be programmed to generate any Boolean function, is also designed. This reversible and programmable OR array is also cascadable. That is, it produces a copy of inputted midterms at its outputs to be fed to another OR array in order to design another Boolean function, with no need for another AND array. The proposed 3-input RPLA is programmed to design three reversible circuits, a 1-bit full adder, a 1-bit full subtractor, and a 2-to-1 line multiplexer. Five figures of merit, including number of gates, number of constant inputs, number of garbage outputs, depth and quantum cost of the circuit are considered to evaluate and compare the designs. A comparison between the proposed reversible AND arrays and the same circuit presented in previous research, against these figures of merit, shows a better performance of our proposed designs. The proposed RPLAs are also evaluated, using these five figures of merit.

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5

Hiluf, Dawit. "All optical programmable logic array (PLA)." Journal of Physics: Conference Series 987 (March 2018): 012033. http://dx.doi.org/10.1088/1742-6596/987/1/012033.

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6

Li, Yao, and George Eichmann. "Nonabsorptive binary optical programmable logic array." Optics Communications 76, no. 2 (April 1990): 107–10. http://dx.doi.org/10.1016/0030-4018(90)90302-a.

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7

Hu, T. C., and Y. S. Kuo. "Graph folding and programmable logic array." Networks 17, no. 1 (1987): 19–37. http://dx.doi.org/10.1002/net.3230170103.

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8

Dettmer, Roger. "User programmable logic: chasing the gate array." IEE Review 36, no. 5 (1990): 181. http://dx.doi.org/10.1049/ir:19900074.

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9

Mottalib, M. A., R. V. S. K. Prasad, and P. Dasgupta. "Function dependent fully testable programmable logic array." Electronics Letters 27, no. 6 (1991): 495. http://dx.doi.org/10.1049/el:19910311.

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10

Barre, Claude. "4506363 Programmable logic array in ECL technology." Microelectronics Reliability 25, no. 4 (January 1985): 814. http://dx.doi.org/10.1016/0026-2714(85)90430-5.

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11

Flak, Jacek, and Mika Laiho. "Fault-tolerant programmable logic array for nanoelectronics." International Journal of Circuit Theory and Applications 40, no. 12 (March 27, 2012): 1233–47. http://dx.doi.org/10.1002/cta.1795.

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12

Li, Yao, Andrew Kostrzewski, Dai Hyun Kim, and George Eichmann. "Free-space folded-path optical programmable logic array." Optics Letters 13, no. 10 (October 1, 1988): 895. http://dx.doi.org/10.1364/ol.13.000895.

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13

Macleod, Todd C., and Fat Duen Ho. "Design of a Ferroelectric Programmable Logic Gate Array." Integrated Ferroelectrics 56, no. 1 (June 2003): 1013–21. http://dx.doi.org/10.1080/10584580390259506.

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14

Barkalov, A. A. "Multilevel programmable logic array schemes for microprogrammed automata." Cybernetics and Systems Analysis 30, no. 4 (July 1994): 489–95. http://dx.doi.org/10.1007/bf02366558.

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15

Lau, K. T., and F. Liu. "IAPDL-based low-power adiabatic programmable logic array." Microelectronics Journal 31, no. 4 (April 2000): 235–38. http://dx.doi.org/10.1016/s0026-2692(99)00105-6.

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16

Liu, Liren, Xiaoben Liu, and Bo Cui. "Optical programmable cellular logic array for image processing." Applied Optics 30, no. 8 (March 10, 1991): 943. http://dx.doi.org/10.1364/ao.30.000943.

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17

Singla, Pradeep. "Power Gating Structure for Reversible Programmable Logic Array." Electrical & Computer Engineering: An International Journal 4, no. 3 (September 30, 2015): 1–14. http://dx.doi.org/10.14810/ecij.2015.4301.

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18

Bahtin, Vadim, Ivan A. Podlesnykh, and Sergey F. Tyurin. "Investigation of a Neural Network Decomposition by Proteus Design Suite." Вестник Пермского университета. Математика. Механика. Информатика, no. 2(57) (2022): 73–80. http://dx.doi.org/10.17072/1993-0550-2022-2-73-80.

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The division of a monolithic neural network into blocks with their implementation on programmable logic within the framework of the Fog computing concept is considered. It is assumed that considering possible reconfiguration the implementation of blocks is performed on programmable logic: field-programmable gate array, FPGA (complex programmable logic device, CPLD), System-on-a-Chip, SoC or System-in-Package, SiP. The article explores such an implementation in the Proteus Design Suite based on ATMega32 microcontrollers. Modeling confirms the efficiency of the developed decomposition method. The research was carried out under the RFBR grant 20-37-90036 (Method of synthesizing neural network recognition devices for implementing the Fog computing mode).

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19

Patel, Dhruv, Jignesh Bhatt, and Sanjay Trivedi. "Programmable logic controller performance enhancement by field programmable gate array based design." ISA Transactions 54 (January 2015): 156–68. http://dx.doi.org/10.1016/j.isatra.2014.08.019.

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20

Jaafar, Anuar, Norhayati Soin, Sharifah F. Wan Muhamad Hatta, Sani Irwan Salim, and Zahriladha Zakaria. "Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance." Applied Sciences 11, no. 14 (July 12, 2021): 6417. http://dx.doi.org/10.3390/app11146417.

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The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier injection and negative bias temperature instability degradation effects. The multipoint detection technique also assisted in signaling the aging effect on the field-programmable gate array caused by the delay occurrence. The multipoint detection technique was also integrated with a method to optimize the performance of the field-programmable gate array via an automatic clock correction scheme, which could provide the best clock signal for prolonging the field-programmable gate array performance that degraded due to the degradation effect. The delay degradation effect ranged from 0° to 360° phase shifts that happened in the field-programmable gate array as an input feeder into the multipoint detection technique. With the ability to provide closed-loop feedback, the proposed multipoint detection technique offered the best clock signal to prolong the field-programmable gate array performance. The results obtained using the multipoint detection technique could detect the remaining lifetime of the field-programmable gate array and propose the best possible signal to prolong the field-programmable gate array’s performance. The validation showed that the multipoint detection technique could prolong the performance of the degraded field-programmable gate array by 13.89%. With the improvement shown using the multipoint detection technique, it was shown that compensating for the degradation effect of the field-programmable gate array with the best clock signal prolonged the performances.

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21

Liu, Cheng, Zhe Li, and Jia Jia Hou. "Simulation and Application of PLD in Electric Power System Circuit." Applied Mechanics and Materials 241-244 (December 2012): 1931–35. http://dx.doi.org/10.4028/www.scientific.net/amm.241-244.1931.

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Programmable Logic Device(PLD) has been widely used in hardware circuit, and it has evolved into two types: Complex Programmable Logic Device(CPLD) and Field Programmable Gate Array(FPGA). This paper takes small current grounding in electric power system as background, uses xc95144, a representative CPLD of Xilinx Company in the signal collecting circuit to collect voltage and current signals, and do some other operations to spare circuit board area. This paper also tries to translate the schematic into VHDL-described text and do simulation to the text.

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22

Rose, Garrett S., and Mircea R. Stan. "A Programmable Majority Logic Array Using Molecular Scale Electronics." IEEE Transactions on Circuits and Systems I: Regular Papers 54, no. 11 (November 2007): 2380–90. http://dx.doi.org/10.1109/tcsi.2007.907860.

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23

Millhollan, M. S., and C. Sung. "A 3.6-ns ECL field programmable array logic device." IEEE Journal of Solid-State Circuits 20, no. 5 (October 1985): 1036–42. http://dx.doi.org/10.1109/jssc.1985.1052433.

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24

Yang, W. J., Y. Zhou, and K. T. Lau. "Low power adiabatic programmable logic array with APDL-2." Electronics Letters 39, no. 21 (2003): 1501. http://dx.doi.org/10.1049/el:20030994.

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25

De, Debashis, Tamoghna Purkayastha, and Tanay Chattopadhyay. "Design of QCA based Programmable Logic Array using decoder." Microelectronics Journal 55 (September 2016): 92–107. http://dx.doi.org/10.1016/j.mejo.2016.06.005.

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26

WEI, K. C., J. J. SHEU, and B. D. LIU. "Low overhead design for programmable logic array with testability." International Journal of Electronics 77, no. 2 (August 1994): 241–50. http://dx.doi.org/10.1080/00207219408926053.

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27

Avdeev, N. A., and P. N. Bibilo. "Determination of the delay of a programmable logic array." Russian Microelectronics 39, no. 4 (July 2010): 288–98. http://dx.doi.org/10.1134/s1063739710040074.

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28

Gokhale, M., W. Holmes, A. Kopser, S. Lucas, R. Minnich, D. Sweely, and D. Lopresti. "Building and using a highly parallel programmable logic array." Computer 24, no. 1 (January 1991): 81–89. http://dx.doi.org/10.1109/2.67197.

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29

Singla, Pradeep, and Naveen Kr. Malik. "A Cost- Effective Design of Reversible Programmable Logic Array." International Journal of Computer Applications 41, no. 15 (March 31, 2012): 41–46. http://dx.doi.org/10.5120/5619-7911.

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30

Ravi, S. S., and Errol L. Lloyd. "The Complexity of Near-Optimal Programmable Logic Array Folding." SIAM Journal on Computing 17, no. 4 (August 1988): 696–710. http://dx.doi.org/10.1137/0217045.

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31

Khvatov, V. M., and M. A. Zapletina. "The Method of Dynamic Characterization of Standard Cell Libraries for Field Programmable Gate Arrays." Informacionnye Tehnologii 29, no. 11 (November 13, 2023): 583–87. http://dx.doi.org/10.17587/it.29.583-587.

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In this paper, the problem of accelerating the development of standard cells libraries for field programmable gate arrays is solved. The target libraries contain the timing characteristics of cells, which are various configurations for the logic element of a field programmable gate array. The method of dynamic characterization of standard cells libraries for solving the problem is proposed. It is based on three stages. The first stage is the decomposition of the logic element. The second stage is the preliminary characterization of the logic element components. The third stage is the cell library generation based on the results obtained after the logical synthesis of the designed circuit. The method allows not to perform calculations for all possible logic element configurations, which significantly reduces the characterization time. The method also considers all structural changes in the element and makes it possible to perform static timing analysis of the designed circuit without a critical loss of accuracy.

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32

Ruiz-Rosero, Juan, Gustavo Ramirez-Gonzalez, and Rahul Khanna. "Field Programmable Gate Array Applications—A Scientometric Review." Computation 7, no. 4 (November 11, 2019): 63. http://dx.doi.org/10.3390/computation7040063.

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Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

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33

Wang, Nuocheng. "HDL Synthesis, Inference and Technology Mapping Algorithms for FPGA Configuration." International Journal of Engineering and Technology 16, no. 1 (2024): 32–38. http://dx.doi.org/10.7763/ijet.2024.v16.1251.

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This paper introduces the logic control flow of Field-Programmable Gate Array (FPGA). The process from analyzing a digital circuit description to component mapping on FPGA is described thoroughly. This transforming process is partitioned into three major stages: combinational logic synthesis, sequential logic inference, and technology mapping. Specific algorithms are discussed for each stage.

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34

Ghosh, Arpita, Amit Jain, and Subir Kumar Sarkar. "Design and Simulation of Single Electron Threshold Logic Gate based Programmable Logic Array." Procedia Technology 10 (2013): 866–74. http://dx.doi.org/10.1016/j.protcy.2013.12.432.

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35

YANG, W. J., Y. ZHOU, and K. T. LAU. "LOW POWER ADIABATIC PROGRAMMABLE LOGIC ARRAY WITH SINGLE CLOCK IAPDL." Journal of Circuits, Systems and Computers 17, no. 02 (April 2008): 211–19. http://dx.doi.org/10.1142/s0218126608004307.

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A novel implementation of a low power adiabatic PLA with a single power clock (IAPDL-SC PLA) is presented. The isolation transistor in the AND array is removed. The power clock is shared by the AND array and the OR array. In this way, the proposed PLA not only saves the device components but also reduces the power consumption. For 3 V VDD and 200 MHz power clock frequency, the simulation results using Hspice show that the power saving is 79.48% compared to dynamic CMOS PLA, 69.34% compared to APDL PLA, and 40.40% compared to IAPDL PLA. For the 5 × 8 × 4 PLA design, the device saving is 30.77% compared to APDL PLA and 12.90% compared to IAPDL PLA. The diodes are the critical components for all the technology designs. Current simulation is based on 0.8 μm process and the power consumption can be further reduced using the more downsized technology designs.

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36

Kania, Dariusz. "Logic Decomposition for PAL-Based CPLDs." Journal of Circuits, Systems and Computers 24, no. 03 (February 10, 2015): 1550042. http://dx.doi.org/10.1142/s0218126615500425.

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The Programmable Array Logic (PAL)-based logic block is the core of the great majority of Complex Programmable Logic Devices (CPLDs). The purpose of this paper is to compare two models of decomposition dedicated to PAL-based devices. Non-standard usage of decomposition, which leads to the reduction of used PAL-based logic blocks in a programmable structure, is the aim of the presented methods. Each decomposition step is optimized for implementation in a PAL-based structure that is characterized by a PAL-based logic block. The essence of decomposition models is oriented towards minimizing the number of PAL-based logic blocks used and adjusting the designed circuit to fit the structures of PAL-based blocks best. In the experimental section, a comparison of two decomposition models with the classical implementation approach is presented. Results of the experiments prove that the proposed methods lead to a significant reduction of chip area in relation to the classical approach, especially if CPLD structures consist of PAL-based blocks containing a relatively small number of product terms.

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37

John, Lizy Kurian. "Memory Chips with Adjustable Configurations." VLSI Design 10, no. 2 (January 1, 1999): 203–15. http://dx.doi.org/10.1155/1999/62801.

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In this paper, we present the concept of Field Programmable Memory Cell Arrays (FPMCAs) as the memory counterpart to Field Programmable Gate Arrays which have proved their utility in design and rapid prototyping. Principles of dynamic reconfigurability using programmable logic and programmable interconnect are incorporated into random access memories to achieve this flexibility. We first present the design of a variable width RAM (VaWiRAM) which is a simple example of a Field Programmable Memory Cell Array. The configuration of VaWiRAMs can be adjusted by setting a few configuration pins on the memory chip. A VaWiRAM reconfigurable between widths 1 and Wmax⁡ can be constructed with the extra cost of Wmax⁡ – 1 pass gates, (Wmax⁡/2) 2-to-1 multiplexers, and ⌈log⁡2[log⁡2(k) + 1]⌉ mode pins. A novel scheme to overlap the address pins with mode control pins and achieve the mode control with only one extra pin is also presented. The paper discusses the architecture of the proposed VaWiRAMs in detail, analyzes the design tradeoffs and introduces the concept of FPMCAs.

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38

Shin, Youngsoo, Insup Shin, Donkyu Baek, Duckhwan Kim, and Seungwhun Paik. "HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning." IEEE Transactions on Circuits and Systems I: Regular Papers 61, no. 1 (January 2014): 146–59. http://dx.doi.org/10.1109/tcsi.2013.2264690.

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39

Wey, C., M. Vai, and F. Lombardi. "On the design of a redundant programmable logic array (RPLA)." IEEE Journal of Solid-State Circuits 22, no. 1 (February 1987): 114–17. http://dx.doi.org/10.1109/jssc.1987.1052682.

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40

Xu, Guo Sheng. "Design of Data Acquisition System Based on FPGA." Advanced Materials Research 403-408 (November 2011): 1592–95. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.1592.

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A new kind of data acquisition system is introduced in this paper, in which the multi-channel synchronized real-time data acquisition under the coordinate control of field-programmable gate array(FPGA) is realized. The design uses field programmable gate arrays(FPGA) for the data processing and logic control. For high speed CCD image data processing, the paper adopts regional parallel processing based on FPGA. The FPGA inner block RAM is used to build high speed image data buffer is put into operation to achieve high speed image data integration and real-time processing. The proposed data acquisition system has characteristics of stable performance, flexible expansion, high real-timeness and integration

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41

Truong, Nhu, Anthony De Souza-Daw, Robert Ross, Thang Manh Hoang, and Tien Dzung Nguyen. "SELF-HEALING MEMORY HARDWARE ARCHITECTURE ON FIELD PROGRAMMABLE GATE ARRAY." ASEAN Engineering Journal 5, no. 1 (February 20, 2014): 39–55. http://dx.doi.org/10.11113/aej.v5.15454.

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Hardware Fault-Tolerance is the set of techniques to remain operational after a fault by design. Programmable Logic Devices are good platforms to implement Hardware Fault-Tolerant techniques by utilizing abundant resources and facilitating self healing operations. In this paper we propose a hardware fault-tolerant architecture to duplicate components in order to replace faulty ones. The proposed architecture is markedly different from other works that mostly focuses on reconfiguring and evolving logic units rather than our evolvable memory units. The self-reparation process for a memory failure is the reallocation and synchronization of memory content. The internal flip-flops form an abundant reconfigurable resource and are reconfigured to work as newly created memory. The proposed architecture has been downloaded and tested on a real FPGA development board and has satisfied all of its pre-defined specifications.

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42

Ruckman, L., and D. Doering. "100 Gb/s High Throughput Serial Protocol (HTSP) for data acquisition systems with interleaved streaming." Journal of Instrumentation 17, no. 07 (July 1, 2022): P07026. http://dx.doi.org/10.1088/1748-0221/17/07/p07026.

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Abstract Demands on Field-Programmable Gate Array (FPGA) data transport have been increasing over the years as frame sizes and refresh rates increase. As the bandwidths requirements increase the ability to implement data transport protocol layers using “soft” programmable logic becomes harder and start to require harden IP blocks implementation. To reduce the number of physical links and interconnects, it is common for data acquisition systems to require interleaving of streams on the same link (e.g. streaming data and streaming register access). This paper presents a way to leverage existing FPGA harden IP blocks to achieve a robust, low latency 100 Gb/s point-to-point link with minimal programmable logic overhead geared towards the needs of data acquisition systems with interleaved streaming requirements.

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43

Zhang, Hai Yan. "IP Core Design of 8253 Based on Quartus II." Applied Mechanics and Materials 380-384 (August 2013): 2941–44. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.2941.

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Provided by ALTERA FPGA/CPLD Quartus II development software development platform. programmable timer/counter 8253s functions and internal circuitry as the basis, combined with programmable gate array (FPGA) products FLEX10KE characteristics, using VHDL hardware description language and schematic Figure two ways 8253 for hierarchical, modular, parameterized logic design. The completed design will be configured to the chip of FLEX10KE,and Proved to be correct.

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44

Ghosh, Arpita, Amit Jain, N. Basanta Singh, and Subir Kumar Sarkar. "Reliability Aspects and Performance Analysis of Single Electron Threshold Logic Based Programmable Logic Array." Journal of Computational and Theoretical Nanoscience 12, no. 9 (September 1, 2015): 2405–14. http://dx.doi.org/10.1166/jctn.2015.4040.

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45

Lei, Lei, Jianji Dong, Bingrong Zou, Zhao Wu, Wenchan Dong, and Xinliang Zhang. "Expanded all-optical programmable logic array based on multi-input/output canonical logic units." Optics Express 22, no. 8 (April 17, 2014): 9959. http://dx.doi.org/10.1364/oe.22.009959.

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46

You, Bao Shan, Kai Feng Liu, Feng Lian Zeng, and Li Ying Pei. "A FPGA-Based Motion Control IC for X-Y Table." Applied Mechanics and Materials 88-89 (August 2011): 67–71. http://dx.doi.org/10.4028/www.scientific.net/amm.88-89.67.

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The new generation of Field Programmable Gate Array (FPGA) technology enables to embed a processor to construct a System on a Programmable Chip( SoPC). A stepper motion control IC for X-Y table using SoPC technology is proposed in this thesis. The proposed motion control IC contains two modules. One module performs the functions of schedule and logic control. Due to the need of complicated control algorithm, it is implemented by software using Nios II embedded processor. The other module performs the functions of interpolation, acceleration and deceleration. Due to the need of high performance, this module is implemented by Programmable Logic Device (PLD) in FPGA. The use of SoPC technology can make the motion control IC of X-Y table more compact, high performance and low cost .

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47

张, 惟玥. "Integrated All-Optical Programmable Logic Array Based on Cross Gain Modulation." Hans Journal of Wireless Communications 09, no. 01 (2019): 14–19. http://dx.doi.org/10.12677/hjwc.2019.91003.

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48

Dong, Wenchan, Zhuyang Huang, Jie Hou, Rui Santos, and Xinliang Zhang. "Integrated all-optical programmable logic array based on semiconductor optical amplifiers." Optics Letters 43, no. 9 (April 27, 2018): 2150. http://dx.doi.org/10.1364/ol.43.002150.

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49

Cheng, J. "Monolithic optical switching technology for a programmable optical logic gate array." Optics & Laser Technology 26, no. 4 (August 1994): 239–49. http://dx.doi.org/10.1016/0030-3992(94)90108-2.

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50

Lee, Kwan-Hee, Sang-Jin Lee, Seok-Man Kim, and Kyoungrok Cho. "Memristor-Based Programmable Logic Array (PLA) and Analysis as Memristive Networks." Journal of Nanoscience and Nanotechnology 13, no. 5 (May 1, 2013): 3265–69. http://dx.doi.org/10.1166/jnn.2013.7260.

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