Relevant bibliographies by topics / Programmable Gate Array

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Programmable Gate Array'

Author: Grafiati
Published: 4 June 2021
Last updated: 27 July 2025

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Journal articles on the topic "Programmable Gate Array"

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Jaafar, Anuar, Norhayati Soin, Sharifah F. Wan Muhamad Hatta, Sani Irwan Salim, and Zahriladha Zakaria. "Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance." Applied Sciences 11, no. 14 (2021): 6417. http://dx.doi.org/10.3390/app11146417.

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The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier inje
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Harris, M. S. "Field-programmable gate array technology." Microelectronics Journal 25, no. 5 (1994): 404. http://dx.doi.org/10.1016/0026-2692(94)90094-9.

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Fourie, C. J., and H. van Heerden. "An RSFQ Superconductive Programmable Gate Array." IEEE Transactions on Applied Superconductivity 17, no. 2 (2007): 538–41. http://dx.doi.org/10.1109/tasc.2007.897387.

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Katam, Naveen Kumar, Oleg A. Mukhanov, and Massoud Pedram. "Superconducting Magnetic Field Programmable Gate Array." IEEE Transactions on Applied Superconductivity 28, no. 2 (2018): 1–12. http://dx.doi.org/10.1109/tasc.2018.2797262.

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VENKATESWARAN, N., S. PATTABIRAMAN, J. DESOUZA, et al. "A DESIGN METHODOLOGY FOR VERY LARGE ARRAY PROCESSORS-PART 2: PACUBE VLSI ARRAYS." International Journal of Pattern Recognition and Artificial Intelligence 09, no. 02 (1995): 263–301. http://dx.doi.org/10.1142/s0218001495000134.

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The types of functional VLSI chips needed for general and special purpose (computationally intensive) applications are wide ranging, Hence, to reduce the turn-around time of these VLSI chips, mask/field programmable PLAs, gate arrays SLAs and FPGAs are available. However these VLSI arrays are unsuitable for designing ultrahigh performance special purpose VLSI chips. There is a strong need for developing a suitable mask programmable VLSI structures exclusively for designing ultrahigh performance and cost-effective special purpose systems. For this purpose, a macro cell based mask programmable P
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Ibraimov, M. K. "IMPLEMENTATION OF FUNCTIONAL BLOCK RADIO UNIT BASED ON SYSTEM-ON-CHIP." Eurasian Physical Technical Journal 20, no. 4 (46) (2023): 74–80. http://dx.doi.org/10.31489/2023no4/74-80.

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This article discusses the implementation of the Radio Unit functional block based on the System-on-Chip. The primary focus was on integrating Radio Unit blocks such as modulation and Fast Fourier Transform on Field-Programmable Gate Array. Technical aspects of design, module testing, and Radio Unit block performance optimization are thoroughly examined. The results demonstrate that when separating the functionality of the 7.3 technology Fifth Generation (5G) radio block, the modulation module uses the minimum Field-Programmable Gate Array resources compared to other blocks. The Fast Fourier T
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Stepaniak, Michael J., Maarten Uijt de Haag, and Frank van Graas. "Field Programmable Gate Array-Based Attitude Stabilization." Journal of Aerospace Computing, Information, and Communication 6, no. 7 (2009): 451–63. http://dx.doi.org/10.2514/1.39707.

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., Karthik S. "REMOTE FIELD-PROGRAMMABLE GATE ARRAY (FPGA) LAB." International Journal of Research in Engineering and Technology 03, no. 04 (2014): 842–45. http://dx.doi.org/10.15623/ijret.2014.0304149.

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Dettmer, Roger. "User programmable logic: chasing the gate array." IEE Review 36, no. 5 (1990): 181. http://dx.doi.org/10.1049/ir:19900074.

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Hyodo, Kazuhito, Hirokazu Noborisaka, Keijiro Yamamoto, and Takashi Yada. "Development of a Portable Multipurpose Controller for Mechatronics Education." Journal of Robotics and Mechatronics 19, no. 2 (2007): 223–31. http://dx.doi.org/10.20965/jrm.2007.p0223.

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The control module we developed for mechatronics education, consists of a Field-programmable gate array (FPGA), a Programmable System-On-Chip (PSoC) and Game Boy Advance (GBA). The FPGA and PSoC provide a reconfigurable peripheral module and the GBA provides computational power and an interactive user interface. The interactive user interface is very useful for developing educational materials, and the control module enables educators to develop a variety of educational materials.
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Dissertations / Theses on the topic "Programmable Gate Array"

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Sharma, Akshay. "Place and route techniques for FPGA architecture advancement /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6108.

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Hall, Tyson Stuart. "Field-Programmable Analog Arrays: A Floating-Gate Approach." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-07122004-124607/unrestricted/hall%5Ftyson%5Fs%5F200407%5Fphd.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. Directed by David Anderson.<br>Prvulovic, Milos, Committee Member ; Citrin, David, Committee Member ; Lanterman, Aaron, Committee Member ; Yalamanchili, Sudhakar, Committee Member ; Hasler, Paul, Committee Member ; Anderson, David, Committee Chair. Includes bibliographical references.
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Han, Yi. "Development of nonlinear reconfigurable control of reconfigurable plants using the FPGA technology." Thesis, [S.l. : s.n.], 2008. http://dk.cput.ac.za/cgi/viewcontent.cgi?article=1011&context=td_cput.

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Malik, Usama Computer Science &amp Engineering Faculty of Engineering UNSW. "Configuration encoding techniques for fast FPGA reconfiguration." Awarded by:University of New South Wales. School of Computer Science and Engineering, 2006. http://handle.unsw.edu.au/1959.4/26212.

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This thesis examines the problem of reducing reconfiguration time of an island-style FPGA at its configuration memory level. The approach followed is to examine configuration encoding techniques in order to reduce the size of the bitstream that must be loaded onto the device to perform a reconfiguration. A detailed analysis of a set of benchmark circuits on various island-style FPGAs shows that a typical circuit randomly changes a small number of bits in the {\it null} or default configuration state of the device. This feature is exploited by developing efficient encoding schemes for configur
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Koh, Shannon Computer Science &amp Engineering Faculty of Engineering UNSW. "Generating the communication infrastracture for module-based dynamic reconfiguration of FPGas." Publisher:University of New South Wales. Computer Science & Engineering, 2008. http://handle.unsw.edu.au/1959.4/41418.

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Current approaches to supporting module-based FPGA reconfiguration focus on various aspects and sub-problems in the area but do not combine to form a coherent, top-down methodology that factors low-level device parameters into every step of the design flow. This thesis proposes such a top-down methodology from application specification to low-level implementation, centered around examining the problem of generating a point-to-point communications infrastructure to support the changing interfaces of dynamically placed modules. Low-level implementation parameters are considered at every stage to
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Wood, Christopher Landon. "Runtime partial FPGA reconfiguration." Thesis, Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15051.

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Galindo, Juan Manuel. "A novel partial reconfiguration methodology for FPGAs of multichip systems /." Online version of thesis, 2008. http://hdl.handle.net/1850/7784.

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Rajagopalan, Kamal. "An FPGA architecture for improved arithmetic performance /." St. Lucia, Qld, 2001. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe16460.pdf.

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Chen, Derrick. "TSFPGA, a time-switched field-programmable gate array." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/41373.

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Jeffrey, Goeders. "Power estimation for diverse field programmable gate array architectures." Thesis, University of British Columbia, 2012. http://hdl.handle.net/2429/43488.

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This thesis presents a new power model, which is capable of modelling the power usage of many different field-programmable gate array (FPGA) architectures. FPGA power models have been developed in the past; however, they were designed for a single, simple architecture, with known circuitry. This work explores a method for estimating power usage for many different user-created architectures. This requires a fundamentally new technique. Although the user specifies the functionality of the FPGA architecture, the physical circuitry is not specified. Central to this work is an algorithm which trans
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Books on the topic "Programmable Gate Array"

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1955-, Trimberger Stephen, ed. Field-programmable gate array technology. Kluwer Academic Publishers, 1994.

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Instruments, Texas. Field programmable gate array. Texas Instruments, 1994.

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Trimberger, Stephen M., ed. Field-Programmable Gate Array Technology. Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2742-8.

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Trimberger, Stephen M. Field-Programmable Gate Array Technology. Springer US, 1994.

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Murgai, Rajeev. Logic synthesis for field-programmable gate arrays. Kluwer Academic Publishers, 1995.

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ACM, International Symposium on Field-Programmable Gate Arrays (17th 2009 Monterey Calif ). FPGA'09: Proceedings of the Seventeenth ACM SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, California, USA, February 22-24, 2009. Association for Computing Machinery, 2009.

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ACM, International Symposium on Field-Programmable Gate Arrays (12th 2004 Monterey Calif ). FPGA 2004: ACM/SIGDA Twelfth ACM International Symposium on Field-Programmable Gate Arrays, Monterey Beach Hotel, Monterey, California, USA : February 22-24, 2004. Association for Computing Machinery, 2004.

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ACM, International Symposium on Field-Programmable Gate Arrays (7th 1999 Monterey Calif ). FPGA '99: ACM/SIGDA International Symposium on Field Programmable Gate Arrays. ACM Press, 1999.

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ACM, International Symposium on Field-Programmable Gate Arrays (3rd 1995 Monterey Calif ). FPGA '95: 1995 ACM Third International Sympsosium on Field-Programmable Gate Arrays : February 12-14, 1995, Monterey Marriott, Monterey, California, USA. ACM Press, 1995.

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ACM Special Interest Group on Design Automation, ed. FPGA '13: Proceedings of the 2013 ACM SIGDA International Symposium on Field Programmable Gate Arrays : February 11-13, 2013, Monterey, California, USA. Association for Computing Machinery, 2013.

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Book chapters on the topic "Programmable Gate Array"

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Weik, Martin H. "field-programmable gate array." In Computer Science and Communications Dictionary. Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_7086.

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Trimberger, Steve. "SRAM Programmable FPGAs." In Field-Programmable Gate Array Technology. Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2742-8_2.

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Hartmann, Robert. "Erasable Programmable Logic Devices." In Field-Programmable Gate Array Technology. Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2742-8_4.

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Boutros, Andrew, and Vaughn Betz. "Field-Programmable Gate Array Architecture." In Handbook of Computer Architecture. Springer Nature Singapore, 2024. https://doi.org/10.1007/978-981-97-9314-3_49.

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Boutros, Andrew, and Vaughn Betz. "Field-Programmable Gate Array Architecture." In Handbook of Computer Architecture. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-15-6401-7_49-1.

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Bindal, Ahmet, and Sotoudeh Hamedi-Hagh. "Field-Programmable-Gate-Array (FPGA)." In Silicon Nanowire Transistors. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-27177-4_7.

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Trimberger, Stephen M. "Introduction." In Field-Programmable Gate Array Technology. Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2742-8_1.

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McCarty, Dennis, and Telle Whitney. "Antifuse Programmed FPGAs." In Field-Programmable Gate Array Technology. Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2742-8_3.

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Sanchez, Eduardo. "Field programmable gate array (FPGA) circuits." In Towards Evolvable Hardware. Springer Berlin Heidelberg, 1996. http://dx.doi.org/10.1007/3-540-61093-6_1.

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Yamamoto, Yota. "Basics of Field-Programmable Gate Array." In Hardware Acceleration of Computational Holography. Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-1938-3_7.

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Conference papers on the topic "Programmable Gate Array"

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Chahine, Imad, David Pommerenke, Moncef Kadi, Poorna Ravva, Anne Louis, and Belahcene Mazari. "Immunity Investigation on a Prototype Field Programmable Gate Array." In 2006_EMC-Europe_Barcelona. IEEE, 2006. https://doi.org/10.23919/emc.2006.10813131.

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Mumbru, Jose, George Panotopoulos, Demetri Psaltis, et al. "Optically programmable gate array." In 2000 International Topical Meeting on Optics in Computing (OC2000), edited by Roger A. Lessard and Tigran V. Galstian. SPIE, 2000. http://dx.doi.org/10.1117/12.386900.

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Derstine, M. W., W. R. Babbitt, J. A. Bell, and B. A. Capron. "S-SEED based programmable logic array." In OSA Annual Meeting. Optica Publishing Group, 1991. http://dx.doi.org/10.1364/oam.1991.fdd2.

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A promising candidate for logic arrays in optical cellular logic image processors is the symmetric self-electrooptic effect device (S-SEED). We describe the operation of an 8 × 16 array of S-SEEDs as programmable logic gates operating using the time sequential scheme described by Lentine et al.1 with a space multiplexed beam combination technique.2 The programmable gate operates at an effective rate &gt;10 kHz which is limited by the speed of the computer drive, and &gt;80% of the gates operate correctly simultaneously. The beam combination scheme used in this system requires that several diff
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Mumbra, Jose M., Demetri Psaltis, Gan Zhou, Xin An, and Fai Mok. "Optically Programmable Gate Array (OPGA)." In Optics in Computing. OSA, 1999. http://dx.doi.org/10.1364/oc.1999.othb4.

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Krestinskaya, Olga, Akshay Kumar Maan, and Alex Pappachen James. "Programmable Memristive Threshold Logic Gate Array." In 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). IEEE, 2018. http://dx.doi.org/10.1109/apccas.2018.8605646.

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Chow, P., P. G. Gulak, and P. Chow. "A Field-Programmable Mixed-Analog-Digital Array." In Third International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1995. http://dx.doi.org/10.1109/fpga.1995.242048.

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Nakajima, Mao, and Minoru Watanabe. "An 11,424-gate dynamic optically reconfigurable gate array VLSI." In 2008 International Conference on Field-Programmable Technology (FPT). IEEE, 2008. http://dx.doi.org/10.1109/fpt.2008.4762401.

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Li, Yao, Andrew Kostrzewski, Dai Hyun Kim, and George Eichmann. "Compact free-space optical programmable logic array." In OSA Annual Meeting. Optica Publishing Group, 1988. http://dx.doi.org/10.1364/oam.1988.mt6.

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To implement a parallel optical digital computer, in addition to the two variables, multiple variable optical logic gates are needed. One way to implement a generalized multiple variable optical logic device is to use an optical programmable logic array. We propose a new method to realize a medium scale, compact, and free-space optical programmable logic array. Using either a 2-D or an array of 1-D optical spatial light modulators inside a lens-based multiple-beam path cavity, an array of optical multiple variable logic product (AND gate) term is generated. This device, together with a program
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Selavo, Leo, Steven P. Levitan, and Donald M. Chiarulli. "An Optically Reconfigurable Field Programmable Gate Array*." In Optics in Computing. OSA, 1999. http://dx.doi.org/10.1364/oc.1999.othb2.

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Kubota, Shinya, and Minoru Watanabe. "A programmable dynamic optically reconfigurable gate array." In 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA). IEEE, 2009. http://dx.doi.org/10.1109/newcas.2009.5290410.

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Reports on the topic "Programmable Gate Array"

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Stepaniak, Michael J., Maarten Uijt de Haag, and Frank Van Graas. Field Programmable Gate Array-Based Attitude Stabilization. Defense Technical Information Center, 2008. http://dx.doi.org/10.21236/ada485525.

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Manohar, Rajit. Experimental 3D Asynchronous Field Programmable Gate Array (FPGA). Defense Technical Information Center, 2015. http://dx.doi.org/10.21236/ada614130.

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Wawrzynek, J., and K. Asanovic. Field-Programmable Gate Array (FPGA) Emulation for Computer Architecture. Defense Technical Information Center, 2009. http://dx.doi.org/10.21236/ada519578.

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Wirthlin, Michael, Brent Nelson, Brad Hutchings, Peter Athanas, and Shawn Bohner. Future Field Programmable Gate Array (FPGA) Design Methodologies and Tool Flows. Defense Technical Information Center, 2008. http://dx.doi.org/10.21236/ada492273.

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Manohar, Rajit. A Secure and Reliable High-Performance Field Programmable Gate Array for Information Processing. Defense Technical Information Center, 2012. http://dx.doi.org/10.21236/ada559184.

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Learn, Mark Walter. Evaluation of soft-core processors on a Xilinx Virtex-5 field programmable gate array. Office of Scientific and Technical Information (OSTI), 2011. http://dx.doi.org/10.2172/1013229.

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Don, Michael, and Mitchell Grabner. A Field-Programmable Gate Array (FPGA)-Based Instrumentation System for an Embedded Flight Controller. DEVCOM Army Research Laboratory, 2022. http://dx.doi.org/10.21236/ad1156875.

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Lin, Chun-Shin. High Speed Publication Subscription Brokering Through Highly Parallel Processing on Field Programmable Gate Array (FPGA). Defense Technical Information Center, 2010. http://dx.doi.org/10.21236/ada514601.

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Bobrek, Miljko, Don Bouldin, David Eugene Holcomb, Stephen M. Killough, Stephen Fulton Smith, and Christina D. Ward. Survey of Field Programmable Gate Array Design Guides and Experience Relevant to Nuclear Power Plant Applications. Office of Scientific and Technical Information (OSTI), 2007. http://dx.doi.org/10.2172/991174.

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Chang, Chen, and Kevin Camera. Exploring Field-Programmable Gate Array (FPGA)-Based Emulation Technologies for Accelerating Computer Architecture Development and Evaluation. Defense Technical Information Center, 2009. http://dx.doi.org/10.21236/ada511786.

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