Dissertations / Theses on the topic 'Programmable Gate Array'
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Sharma, Akshay. "Place and route techniques for FPGA architecture advancement /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6108.
Full textHall, Tyson Stuart. "Field-Programmable Analog Arrays: A Floating-Gate Approach." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-07122004-124607/unrestricted/hall%5Ftyson%5Fs%5F200407%5Fphd.pdf.
Full textHan, Yi. "Development of nonlinear reconfigurable control of reconfigurable plants using the FPGA technology." Thesis, [S.l. : s.n.], 2008. http://dk.cput.ac.za/cgi/viewcontent.cgi?article=1011&context=td_cput.
Full textMalik, Usama Computer Science & Engineering Faculty of Engineering UNSW. "Configuration encoding techniques for fast FPGA reconfiguration." Awarded by:University of New South Wales. School of Computer Science and Engineering, 2006. http://handle.unsw.edu.au/1959.4/26212.
Full textKoh, Shannon Computer Science & Engineering Faculty of Engineering UNSW. "Generating the communication infrastracture for module-based dynamic reconfiguration of FPGas." Publisher:University of New South Wales. Computer Science & Engineering, 2008. http://handle.unsw.edu.au/1959.4/41418.
Full textWood, Christopher Landon. "Runtime partial FPGA reconfiguration." Thesis, Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15051.
Full textGalindo, Juan Manuel. "A novel partial reconfiguration methodology for FPGAs of multichip systems /." Online version of thesis, 2008. http://hdl.handle.net/1850/7784.
Full textRajagopalan, Kamal. "An FPGA architecture for improved arithmetic performance /." St. Lucia, Qld, 2001. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe16460.pdf.
Full textChen, Derrick. "TSFPGA, a time-switched field-programmable gate array." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/41373.
Full textJeffrey, Goeders. "Power estimation for diverse field programmable gate array architectures." Thesis, University of British Columbia, 2012. http://hdl.handle.net/2429/43488.
Full textTau, Edward F. (Edward Feiward). "Testing of a first-generation dynamically programmable gate array." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/40201.
Full textFong, Ryan Joseph Lim. "Improving Field-Programmable Gate Array Scaling Through Wire Emulation." Thesis, Virginia Tech, 2004. http://hdl.handle.net/10919/35086.
Full textVan, Heerden Hein. "The design and testing of a superconducting programmable gate array." Thesis, Stellenbosch : University of Stellenbosch, 2006. http://hdl.handle.net/10019.1/1644.
Full textHAWK, CHRISTOPHER J. "DESIGN OF A PROGRAMMABLE ROUTING FRAMEWORK FOR MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1076114416.
Full textMak, Wai-kei. "Partitioning and routing for multi-FPGA systems /." Digital version accessible at:, 1998. http://wwwlib.umi.com/cr/utexas/main.
Full textChang, Mark L. "Variable precision analysis for FPGA synthesis /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/5901.
Full textHawk, Christopher. "Design of a programmable routing framework for a multi-technology field programmable gate array." Cincinnati, Ohio : University of Cincinnati, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=ucin1076114416.
Full textKucic, Matthew R. "Analog programmable filters using floating-gate arrays." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/13755.
Full textLund, John J. "Field programmable gate array hysteresis control of parallel connected inverters." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2006. http://library.nps.navy.mil/uhtbin/hyperion/06Jun%5FLund.pdf.
Full textMekala, Priyanka. "Field Programmable Gate Array Based Target Detection and Gesture Recognition." FIU Digital Commons, 2012. http://digitalcommons.fiu.edu/etd/723.
Full textPerez, Christopher E. "Variation-aware placement tool for Field Programmable Gate Array devices." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/41664.
Full textShekhar, Richa. "Modular Field Programmable Gate Array Implementation of a MIMO Transmitter." International Foundation for Telemetering, 2010. http://hdl.handle.net/10150/605974.
Full textMountney, John M. "Particle Filtering Programmable Gate Array Architecture for Brain Machine Interfaces." Diss., Temple University Libraries, 2011. http://cdm16002.contentdm.oclc.org/cdm/ref/collection/p245801coll10/id/140741.
Full textSubramanian, Prasad. "A Field Programmable Gate Array Based Finite-Domain Constraint Solver." DigitalCommons@USU, 2008. https://digitalcommons.usu.edu/etd/99.
Full textKallam, Ramachandra. "Accelerated Frame Data Relocation on Xilinx Field Programmable Gate Array." DigitalCommons@USU, 2010. https://digitalcommons.usu.edu/etd/655.
Full textSudarsanam, Arvind. "Analysis of Field Programmable Gate Array-Based Kalman Filter Architectures." DigitalCommons@USU, 2010. https://digitalcommons.usu.edu/etd/788.
Full textSchlottmann, Craig Richard. "Analog signal processing on a reconfigurable platform." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29623.
Full textBalog, Michael Rosen Warren A. "The automated compilation of comprehensive hardware design search spaces of algorithmic-based implementations for FPGA design exploration /." Philadelphia, Pa. : Drexel University, 2007. http://hdl.handle.net/1860/1770.
Full textGray, Jordan D. "Application of Floating-Gate Transistors in Field Programmable Analog Arrays." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7540.
Full textWolz, Frank. "Ein generisches Konzept zur Modellierung und Bewertung feldprogrammierbarer Architekturen." [S.l.] : [s.n.], 2004. http://deposit.ddb.de/cgi-bin/dokserv?idn=971588953.
Full textSedaghat, Maman Reza. "Fault emulation reconfigurable hardware based fault simulation using logic emulation systems with optimized mapping /." [S.l. : s.n.], 1999. http://deposit.ddb.de/cgi-bin/dokserv?idn=95853893X.
Full textKornmesser, Klaus. "Das FPGA-Entwicklungssystem CHDL eine vollständige, C++-basierte Entwicklungsumgebung für FPGA-Koprozessoren /." [S.l. : s.n.], 2004. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB11612006.
Full textSimmler, Harald C. "Preemptive multitasking auf FPGA-Prozessoren : ein Betriebssystem für FPGA-Prozessoren /." [S.l. : s.n.], 2001. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB9460961.
Full textRaghavan, Anup Kumar. "JPG : a partial bitstream generation tool to support partial reconfiguration in Virtex FPGAs /." [St. Lucia, Qld.], 2004. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe17691.pdf.
Full textKrantz, Emil. "Utvärdering av Field-Programmable Gate Array (FPGA) som hjälpprocessor för prestandaökning." Thesis, University of Gävle, Department of Mathematics, Natural and Computer Sciences, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-586.
Full textShannon, Lesley. "Impact of intellectual property cores on field programmable gate array designs." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/MQ58799.pdf.
Full textO'Connor, Joseph E. "Field programmable gate array control of systems in graduate student laboratories." Thesis, Monterey, Calif. : Naval Postgraduate School, 2008. http://bosun.nps.edu/uhtbin/hyperion-image.exe/08Mar%5FOConnor.pdf.
Full textBrown, Jarrod P. "Field Programmable Gate Array Application for Decoding IRIG-B Time Code." International Foundation for Telemetering, 2013. http://hdl.handle.net/10150/579691.
Full textCarlson, Charles. "Low-power packet synchronization scheme implemented on field programmable gate array." Thesis, Kansas State University, 2015. http://hdl.handle.net/2097/20423.
Full textWang, Fei Dr. "A Field Programmable Gate Array Architecture for Two-Dimensional Partial Reconfiguration." Wright State University / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=wright1166735848.
Full textWright, Durke A. "Field programmable gate array (FPGA) based software defined radio (SDR) design." Thesis, Monterey, Calif. : Naval Postgraduate School, 2009. http://edocs.nps.edu/npspubs/scholarly/theses/2009/March/09Mar%5FWright.pdf.
Full textShen, Ying. "Compiling a synchronous programming language into field programmable gate arrays." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0029/MQ47476.pdf.
Full textStevenson, Jeremy C. Duren Russell Walker Thompson Michael Wayne. "A comparison of field programmable gate arrays and digital signal processors in acoustic array processing." Waco, Tex. : Baylor University, 2006. http://hdl.handle.net/2104/4186.
Full textDe, la Cruz Juan Alberto. "Field-Programmable Gate Array Implementation of a Scalable Integral Image Architecture Based on Systolic Arrays." DigitalCommons@USU, 2011. https://digitalcommons.usu.edu/etd/854.
Full textZhuo, Yue. "Timing and Congestion Driven Algorithms for FPGA Placement." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5423/.
Full textCevik, Ulus. "Design of an FPGA based parallel architecture processor for displaying CSG volumes and surfaces." Thesis, University of Sussex, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.321348.
Full textDonachy, Paul. "Design and implementation of a high level image processing machine using reconfigurable hardware." Thesis, Queen's University Belfast, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.337688.
Full textMartin, Peter N. "Genetic programming in hardware." Thesis, University of Essex, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.272585.
Full textMacBeth, John Stuart. "Dynamically reconfigurable intellectual property cores." Thesis, University of Strathclyde, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.273843.
Full textKhomich, Andrei. "Using FPGA Co-processors for Improving the execution Speed of Pattern Recognition Algorithms in ATLAS LVL2 Trigger." [S.l. : s.n.], 2006. http://nbn-resolving.de/urn:nbn:de:bsz:180-madoc-13332.
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