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Dissertations / Theses on the topic 'Programmable Gate Array'

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Published: 4 June 2021

Last updated: 27 July 2025

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1

Sharma, Akshay. "Place and route techniques for FPGA architecture advancement /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6108.

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2

Hall, Tyson Stuart. "Field-Programmable Analog Arrays: A Floating-Gate Approach." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-07122004-124607/unrestricted/hall%5Ftyson%5Fs%5F200407%5Fphd.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. Directed by David Anderson.<br>Prvulovic, Milos, Committee Member ; Citrin, David, Committee Member ; Lanterman, Aaron, Committee Member ; Yalamanchili, Sudhakar, Committee Member ; Hasler, Paul, Committee Member ; Anderson, David, Committee Chair. Includes bibliographical references.

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3

Han, Yi. "Development of nonlinear reconfigurable control of reconfigurable plants using the FPGA technology." Thesis, [S.l. : s.n.], 2008. http://dk.cput.ac.za/cgi/viewcontent.cgi?article=1011&context=td_cput.

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4

Malik, Usama Computer Science &amp Engineering Faculty of Engineering UNSW. "Configuration encoding techniques for fast FPGA reconfiguration." Awarded by:University of New South Wales. School of Computer Science and Engineering, 2006. http://handle.unsw.edu.au/1959.4/26212.

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This thesis examines the problem of reducing reconfiguration time of an island-style FPGA at its configuration memory level. The approach followed is to examine configuration encoding techniques in order to reduce the size of the bitstream that must be loaded onto the device to perform a reconfiguration. A detailed analysis of a set of benchmark circuits on various island-style FPGAs shows that a typical circuit randomly changes a small number of bits in the {\it null} or default configuration state of the device. This feature is exploited by developing efficient encoding schemes for configur

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5

Koh, Shannon Computer Science &amp Engineering Faculty of Engineering UNSW. "Generating the communication infrastracture for module-based dynamic reconfiguration of FPGas." Publisher:University of New South Wales. Computer Science & Engineering, 2008. http://handle.unsw.edu.au/1959.4/41418.

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Current approaches to supporting module-based FPGA reconfiguration focus on various aspects and sub-problems in the area but do not combine to form a coherent, top-down methodology that factors low-level device parameters into every step of the design flow. This thesis proposes such a top-down methodology from application specification to low-level implementation, centered around examining the problem of generating a point-to-point communications infrastructure to support the changing interfaces of dynamically placed modules. Low-level implementation parameters are considered at every stage to

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6

Wood, Christopher Landon. "Runtime partial FPGA reconfiguration." Thesis, Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15051.

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7

Galindo, Juan Manuel. "A novel partial reconfiguration methodology for FPGAs of multichip systems /." Online version of thesis, 2008. http://hdl.handle.net/1850/7784.

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8

Rajagopalan, Kamal. "An FPGA architecture for improved arithmetic performance /." St. Lucia, Qld, 2001. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe16460.pdf.

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9

Chen, Derrick. "TSFPGA, a time-switched field-programmable gate array." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/41373.

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10

Jeffrey, Goeders. "Power estimation for diverse field programmable gate array architectures." Thesis, University of British Columbia, 2012. http://hdl.handle.net/2429/43488.

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This thesis presents a new power model, which is capable of modelling the power usage of many different field-programmable gate array (FPGA) architectures. FPGA power models have been developed in the past; however, they were designed for a single, simple architecture, with known circuitry. This work explores a method for estimating power usage for many different user-created architectures. This requires a fundamentally new technique. Although the user specifies the functionality of the FPGA architecture, the physical circuitry is not specified. Central to this work is an algorithm which trans

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11

Tau, Edward F. (Edward Feiward). "Testing of a first-generation dynamically programmable gate array." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/40201.

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12

Fong, Ryan Joseph Lim. "Improving Field-Programmable Gate Array Scaling Through Wire Emulation." Thesis, Virginia Tech, 2004. http://hdl.handle.net/10919/35086.

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Field-programmable gate arrays (FPGAs) are excellent devices for high-performance computing, system-on-chip realization, and rapid system prototyping. While FPGAs offer flexibility and performance, they continue to lag behind application specific integrated circuit (ASIC) performance and power consumption. As manufacturing technology improves and IC feature size decreases, FPGAs may further lag behind ASICs due to interconnection scalability issues. To improve FPGA scalability, this thesis proposes an architectural enhancement to improve global communications in large FPGAs, where chip-leng

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13

Van, Heerden Hein. "The design and testing of a superconducting programmable gate array." Thesis, Stellenbosch : University of Stellenbosch, 2006. http://hdl.handle.net/10019.1/1644.

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Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2006.<br>This thesis investigates to the design, analysis and testing of a Superconducting Programmable Gate Array (SPGA). The objective was to apply existing programmable logic concepts to RSFQ circuits and in the process develop a working prototype of a superconducting programmable logic device. Various programmable logic technologies and architectures were examined and compared to find the best solution. Using Rapid Single Flux Quantum (RSFQ) circuits as building blocks, a complete functional design wa

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14

HAWK, CHRISTOPHER J. "DESIGN OF A PROGRAMMABLE ROUTING FRAMEWORK FOR MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1076114416.

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15

Mak, Wai-kei. "Partitioning and routing for multi-FPGA systems /." Digital version accessible at:, 1998. http://wwwlib.umi.com/cr/utexas/main.

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16

Chang, Mark L. "Variable precision analysis for FPGA synthesis /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/5901.

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17

Hawk, Christopher. "Design of a programmable routing framework for a multi-technology field programmable gate array." Cincinnati, Ohio : University of Cincinnati, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=ucin1076114416.

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18

Kucic, Matthew R. "Analog programmable filters using floating-gate arrays." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/13755.

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19

Lund, John J. "Field programmable gate array hysteresis control of parallel connected inverters." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2006. http://library.nps.navy.mil/uhtbin/hyperion/06Jun%5FLund.pdf.

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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, June 2006.<br>Thesis Advisor(s): Robert Ashton. "June 2006." Includes bibliographical references (p.105-106). Also available in print.

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20

Mekala, Priyanka. "Field Programmable Gate Array Based Target Detection and Gesture Recognition." FIU Digital Commons, 2012. http://digitalcommons.fiu.edu/etd/723.

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The move from Standard Definition (SD) to High Definition (HD) represents a six times increases in data, which needs to be processed. With expanding resolutions and evolving compression, there is a need for high performance with flexible architectures to allow for quick upgrade ability. The technology advances in image display resolutions, advanced compression techniques, and video intelligence. Software implementation of these systems can attain accuracy with tradeoffs among processing performance (to achieve specified frame rates, working on large image data sets), power and cost constraints

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21

Perez, Christopher E. "Variation-aware placement tool for Field Programmable Gate Array devices." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/41664.

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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.<br>Includes bibliographical references (p. 97-98).<br>Introduction: As semiconductor technologies become more advanced, process variations within microelectronic devices, including variations in channel length or in oxide thickness, play a much more important role with regards to circuit delay and leakage power dissipation. These process variations cause variability in circuit performance characteristics that can be minimized by improving process control techniques, resulting in

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22

Shekhar, Richa. "Modular Field Programmable Gate Array Implementation of a MIMO Transmitter." International Foundation for Telemetering, 2010. http://hdl.handle.net/10150/605974.

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ITC/USA 2010 Conference Proceedings / The Forty-Sixth Annual International Telemetering Conference and Technical Exhibition / October 25-28, 2010 / Town and Country Resort & Convention Center, San Diego, California<br>Multiple-Input Multiple-Output (MIMO) systems have at least two transmitting antennas, each generating unique signals. However some applications may require three, four, or more transmitting devices to achieve the desired system performance. This paper describes the design of a scalable MIMO transmitter, based on field programmable gate array (FPGA) technology. Each module contai

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23

Mountney, John M. "Particle Filtering Programmable Gate Array Architecture for Brain Machine Interfaces." Diss., Temple University Libraries, 2011. http://cdm16002.contentdm.oclc.org/cdm/ref/collection/p245801coll10/id/140741.

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Electrical Engineering<br>Ph.D.<br>Decoding algorithms for brain machine interfaces map neural firing times to the underlying biological output signal through dynamic tuning functions. In order to maintain an accurate estimate of the biological signal, the state of the tuning function parameters must be tracked simultaneously. The evolution of this system state is often estimated by an adaptive filter. Recent work demonstrates that the Bayesian auxiliary particle filter (BAPF) offers improved estimates of the system state and underlying output signal over existing techniques. Performance of th

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24

Subramanian, Prasad. "A Field Programmable Gate Array Based Finite-Domain Constraint Solver." DigitalCommons@USU, 2008. https://digitalcommons.usu.edu/etd/99.

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Constraint satisfaction and optimization techniques are commonly employed in scheduling problems, industrial manufacturing, and automation processes. Constraint Satisfaction Problem (CSP) also finds use in the design, synthesis, and optimization of embedded systems. In recent years online constraint solving techniques have been employed in embedded systems for dynamic system adaptation. In embedded systems, online constraint solving techniques are primarily used as on-board control software. Using CSP techniques for scheduling algorithms provides intelligent scheduling. This thesis discusses t

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25

Kallam, Ramachandra. "Accelerated Frame Data Relocation on Xilinx Field Programmable Gate Array." DigitalCommons@USU, 2010. https://digitalcommons.usu.edu/etd/655.

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Emerging reconfiguration techniques that include partial dynamic reconfiguration and partial bitstream relocation have been addressed in the past in order to expose the flexibility of field programmable gate array at runtime. Partial bitstream relocation is a technique used to target a partial bitstream of a partial reconfigurable region (PRR) onto other identical reconfigurable regions inside an FPGA, while partial dynamic reconfiguration is used to target a single reconfigurable region. Prior works in this domain aim to minimize "relocation time" with the help of on-chip or on-line processin

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26

Sudarsanam, Arvind. "Analysis of Field Programmable Gate Array-Based Kalman Filter Architectures." DigitalCommons@USU, 2010. https://digitalcommons.usu.edu/etd/788.

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A Field Programmable Gate Array (FPGA)-based Polymorphic Faddeev Systolic Array (PolyFSA) architecture is proposed to accelerate an Extended Kalman Filter (EKF) algorithm. A system architecture comprising a software processor as the host processor, a hardware controller, a cache-based memory sub-system, and the proposed PolyFSA as co-processor, is presented. PolyFSA-based system architecture is implemented on a Xilinx Virtex 4 family of FPGAs. Results indicate significant speed-ups for the proposed architecture when compared against a space-based software processor. This dissertation proposes

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27

Schlottmann, Craig Richard. "Analog signal processing on a reconfigurable platform." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29623.

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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.<br>Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Ghovanloo, Maysam. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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28

Balog, Michael Rosen Warren A. "The automated compilation of comprehensive hardware design search spaces of algorithmic-based implementations for FPGA design exploration /." Philadelphia, Pa. : Drexel University, 2007. http://hdl.handle.net/1860/1770.

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29

Gray, Jordan D. "Application of Floating-Gate Transistors in Field Programmable Analog Arrays." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7540.

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Floating-gate transistors similar to those used in FLASH and EEPROM can be used to build reconfigurable analog arrays. The charge on the floating gate can be modified to pass or block a signal in a cross-bar switch matrix, or it can be finely tuned to eliminate a threshold difference across a chip or set a bias. By using such a compact and versatile reconfigurable analog memory element, the number of analog circuit components included on an integrated circuit that is field-programmable is significantly higher. As a result, large-scale FPAAs can be built with the same impact on analog design

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30

Wolz, Frank. "Ein generisches Konzept zur Modellierung und Bewertung feldprogrammierbarer Architekturen." [S.l.] : [s.n.], 2004. http://deposit.ddb.de/cgi-bin/dokserv?idn=971588953.

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31

Sedaghat, Maman Reza. "Fault emulation reconfigurable hardware based fault simulation using logic emulation systems with optimized mapping /." [S.l. : s.n.], 1999. http://deposit.ddb.de/cgi-bin/dokserv?idn=95853893X.

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32

Kornmesser, Klaus. "Das FPGA-Entwicklungssystem CHDL eine vollständige, C++-basierte Entwicklungsumgebung für FPGA-Koprozessoren /." [S.l. : s.n.], 2004. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB11612006.

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33

Simmler, Harald C. "Preemptive multitasking auf FPGA-Prozessoren : ein Betriebssystem für FPGA-Prozessoren /." [S.l. : s.n.], 2001. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB9460961.

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34

Raghavan, Anup Kumar. "JPG : a partial bitstream generation tool to support partial reconfiguration in Virtex FPGAs /." [St. Lucia, Qld.], 2004. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe17691.pdf.

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35

Krantz, Emil. "Utvärdering av Field-Programmable Gate Array (FPGA) som hjälpprocessor för prestandaökning." Thesis, University of Gävle, Department of Mathematics, Natural and Computer Sciences, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-586.

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<p>Det här arbetet är en utvärdering om huruvida det finns problem som kan få en prestandavinst då man använder en Field-Programmable Gate Array (FPGA) som hjälpprocessor till en mikroprocessor i jämförelse men att enbart använda en mikro-processor. För att avgöra detta implementerades algoritmen gaussfiltrering dels på en mikroprocessor med språket C och dels för en FPGA med hårdvarubeskrivningsspråket Very-High-Speed Integrated Circuits Hardware Description Language (VHDL). Simuleringar gjordes för dessa två implementationer och resultatet visade att det var möjligt att få en prestandaökning

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36

Shannon, Lesley. "Impact of intellectual property cores on field programmable gate array designs." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/MQ58799.pdf.

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37

O'Connor, Joseph E. "Field programmable gate array control of systems in graduate student laboratories." Thesis, Monterey, Calif. : Naval Postgraduate School, 2008. http://bosun.nps.edu/uhtbin/hyperion-image.exe/08Mar%5FOConnor.pdf.

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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, March 2008.<br>Thesis Advisor(s): Julian, Alexander L. "March 2008." Description based on title screen as viewed on May 5, 2008. Includes bibliographical references (p. 73-75). Also available in print.

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38

Brown, Jarrod P. "Field Programmable Gate Array Application for Decoding IRIG-B Time Code." International Foundation for Telemetering, 2013. http://hdl.handle.net/10150/579691.

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ITC/USA 2013 Conference Proceedings / The Forty-Ninth Annual International Telemetering Conference and Technical Exhibition / October 21-24, 2013 / Bally's Hotel & Convention Center, Las Vegas, NV<br>A field programmable gate array (FPGA) is used to decode Inter-Range Instrumentation Group (IRIG) time code for a PC-based Time-Space-Position Information (TSPI) acquisition. The FPGA architecture can latch time via an external event trigger or a programmable periodic internal event. By syncing time with an external IRIG Group Type B (IRIG-B) signal and using an 8 megahertz (MHz) internal clock, c

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39

Carlson, Charles. "Low-power packet synchronization scheme implemented on field programmable gate array." Thesis, Kansas State University, 2015. http://hdl.handle.net/2097/20423.

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Master of Science<br>Electrical and Computer Engineering<br>Dwight D. Day<br>Synchronization is one of the most critical steps in a wireless communication system. With the system having limited energy resources, low power devices and designs are key aspects of the design process. Digital communication and decoding is discussed along with how synchronization is part of communication. The parameters for wireless communication are outlined and how the system can be simplified in order to reduce power consumption for the network is investigated. The background for the Body Area Network Board which

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40

Wang, Fei Dr. "A Field Programmable Gate Array Architecture for Two-Dimensional Partial Reconfiguration." Wright State University / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=wright1166735848.

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41

Wright, Durke A. "Field programmable gate array (FPGA) based software defined radio (SDR) design." Thesis, Monterey, Calif. : Naval Postgraduate School, 2009. http://edocs.nps.edu/npspubs/scholarly/theses/2009/March/09Mar%5FWright.pdf.

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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, March 2009.<br>Thesis Advisor(s): Kragh, Frank ; Loomis, Herschel. "March 2009." Description based on title screen as viewed on April 24, 2009. Author(s) subject terms: Software Defined Radio, SDR, Field Programmable Gate Array, FPGA, Signal Compression. Includes bibliographical references (p. 105-106). Also available in print.

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42

Shen, Ying. "Compiling a synchronous programming language into field programmable gate arrays." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0029/MQ47476.pdf.

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43

Stevenson, Jeremy C. Duren Russell Walker Thompson Michael Wayne. "A comparison of field programmable gate arrays and digital signal processors in acoustic array processing." Waco, Tex. : Baylor University, 2006. http://hdl.handle.net/2104/4186.

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44

De, la Cruz Juan Alberto. "Field-Programmable Gate Array Implementation of a Scalable Integral Image Architecture Based on Systolic Arrays." DigitalCommons@USU, 2011. https://digitalcommons.usu.edu/etd/854.

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The integral image representation of an image is important for a large number of modern image processing algorithms. Integral image representations can reduce computation and increase the operating speed of certain algorithms, improving real-time performance. Due to increasing demand for real-time image processing performance, an integral image architecture capable of accelerating the calculation based on the amount of available resources is presented. Use of the proposed accelerator allows for subsequent stages of a design to have data sooner and execute in parallel. It is shown here how, wit

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45

Zhuo, Yue. "Timing and Congestion Driven Algorithms for FPGA Placement." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5423/.

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Placement is one of the most important steps in physical design for VLSI circuits. For field programmable gate arrays (FPGAs), the placement step determines the location of each logic block. I present novel timing and congestion driven placement algorithms for FPGAs with minimal runtime overhead. By predicting the post-routing timing-critical edges and estimating congestion accurately, this algorithm is able to simultaneously reduce the critical path delay and the minimum number of routing tracks. The core of the algorithm consists of a criticality-history record of connection edges and a cong

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46

Cevik, Ulus. "Design of an FPGA based parallel architecture processor for displaying CSG volumes and surfaces." Thesis, University of Sussex, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.321348.

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47

Donachy, Paul. "Design and implementation of a high level image processing machine using reconfigurable hardware." Thesis, Queen's University Belfast, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.337688.

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48

Martin, Peter N. "Genetic programming in hardware." Thesis, University of Essex, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.272585.

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49

MacBeth, John Stuart. "Dynamically reconfigurable intellectual property cores." Thesis, University of Strathclyde, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.273843.

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Khomich, Andrei. "Using FPGA Co-processors for Improving the execution Speed of Pattern Recognition Algorithms in ATLAS LVL2 Trigger." [S.l. : s.n.], 2006. http://nbn-resolving.de/urn:nbn:de:bsz:180-madoc-13332.

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