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Journal articles on the topic 'Programmable Gate Array'

Author: Grafiati

Published: 4 June 2021

Last updated: 27 July 2025

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1

Jaafar, Anuar, Norhayati Soin, Sharifah F. Wan Muhamad Hatta, Sani Irwan Salim, and Zahriladha Zakaria. "Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance." Applied Sciences 11, no. 14 (2021): 6417. http://dx.doi.org/10.3390/app11146417.

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The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier inje

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2

Harris, M. S. "Field-programmable gate array technology." Microelectronics Journal 25, no. 5 (1994): 404. http://dx.doi.org/10.1016/0026-2692(94)90094-9.

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3

Fourie, C. J., and H. van Heerden. "An RSFQ Superconductive Programmable Gate Array." IEEE Transactions on Applied Superconductivity 17, no. 2 (2007): 538–41. http://dx.doi.org/10.1109/tasc.2007.897387.

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4

Katam, Naveen Kumar, Oleg A. Mukhanov, and Massoud Pedram. "Superconducting Magnetic Field Programmable Gate Array." IEEE Transactions on Applied Superconductivity 28, no. 2 (2018): 1–12. http://dx.doi.org/10.1109/tasc.2018.2797262.

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5

VENKATESWARAN, N., S. PATTABIRAMAN, J. DESOUZA, et al. "A DESIGN METHODOLOGY FOR VERY LARGE ARRAY PROCESSORS-PART 2: PACUBE VLSI ARRAYS." International Journal of Pattern Recognition and Artificial Intelligence 09, no. 02 (1995): 263–301. http://dx.doi.org/10.1142/s0218001495000134.

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The types of functional VLSI chips needed for general and special purpose (computationally intensive) applications are wide ranging, Hence, to reduce the turn-around time of these VLSI chips, mask/field programmable PLAs, gate arrays SLAs and FPGAs are available. However these VLSI arrays are unsuitable for designing ultrahigh performance special purpose VLSI chips. There is a strong need for developing a suitable mask programmable VLSI structures exclusively for designing ultrahigh performance and cost-effective special purpose systems. For this purpose, a macro cell based mask programmable P

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6

Ibraimov, M. K. "IMPLEMENTATION OF FUNCTIONAL BLOCK RADIO UNIT BASED ON SYSTEM-ON-CHIP." Eurasian Physical Technical Journal 20, no. 4 (46) (2023): 74–80. http://dx.doi.org/10.31489/2023no4/74-80.

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This article discusses the implementation of the Radio Unit functional block based on the System-on-Chip. The primary focus was on integrating Radio Unit blocks such as modulation and Fast Fourier Transform on Field-Programmable Gate Array. Technical aspects of design, module testing, and Radio Unit block performance optimization are thoroughly examined. The results demonstrate that when separating the functionality of the 7.3 technology Fifth Generation (5G) radio block, the modulation module uses the minimum Field-Programmable Gate Array resources compared to other blocks. The Fast Fourier T

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7

Stepaniak, Michael J., Maarten Uijt de Haag, and Frank van Graas. "Field Programmable Gate Array-Based Attitude Stabilization." Journal of Aerospace Computing, Information, and Communication 6, no. 7 (2009): 451–63. http://dx.doi.org/10.2514/1.39707.

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8

., Karthik S. "REMOTE FIELD-PROGRAMMABLE GATE ARRAY (FPGA) LAB." International Journal of Research in Engineering and Technology 03, no. 04 (2014): 842–45. http://dx.doi.org/10.15623/ijret.2014.0304149.

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9

Dettmer, Roger. "User programmable logic: chasing the gate array." IEE Review 36, no. 5 (1990): 181. http://dx.doi.org/10.1049/ir:19900074.

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10

Hyodo, Kazuhito, Hirokazu Noborisaka, Keijiro Yamamoto, and Takashi Yada. "Development of a Portable Multipurpose Controller for Mechatronics Education." Journal of Robotics and Mechatronics 19, no. 2 (2007): 223–31. http://dx.doi.org/10.20965/jrm.2007.p0223.

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The control module we developed for mechatronics education, consists of a Field-programmable gate array (FPGA), a Programmable System-On-Chip (PSoC) and Game Boy Advance (GBA). The FPGA and PSoC provide a reconfigurable peripheral module and the GBA provides computational power and an interactive user interface. The interactive user interface is very useful for developing educational materials, and the control module enables educators to develop a variety of educational materials.

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11

Chen, Yonghao, Tianrui Li, Xiaojie Chen, ZhiGang Cai, and Tao Su. "High-Frequency Systolic Array-Based Transformer Accelerator on Field Programmable Gate Arrays." Electronics 12, no. 4 (2023): 822. http://dx.doi.org/10.3390/electronics12040822.

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The systolic array is frequently used in accelerators for neural networks, including Transformer models that have recently achieved remarkable progress in natural language processing (NLP) and machine translation. Due to the constraints of FPGA EDA (Field Programmable Gate Array Electronic Design Automation) tools and the limitations of design methodology, existing systolic array accelerators for FPGA deployment often cannot achieve high frequency. In this work, we propose a well-designed high-frequency systolic array for an FPGA-based Transformer accelerator, which is capable of performing th

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12

Parikh, Raj S. "Alarm System Implementation on Field Programmable Gate Array." International Journal for Research in Applied Science and Engineering Technology 6 (January 31, 2018): 1084–88. http://dx.doi.org/10.22214/ijraset.2018.1164.

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13

Ruiz-Rosero, Juan, Gustavo Ramirez-Gonzalez, and Rahul Khanna. "Field Programmable Gate Array Applications—A Scientometric Review." Computation 7, no. 4 (2019): 63. http://dx.doi.org/10.3390/computation7040063.

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Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram

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14

Qi, Xing Guang, Yan Min Zhang, Qing Hua Li, and Ning Wang. "Photon Correlator Implemented by Field Programmable Gate Array." Applied Mechanics and Materials 513-517 (February 2014): 4171–74. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.4171.

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Photon correlation technique is an effective method for measuring the particle size of sub-micron particles and nanoparticles. This technology has a good prospect and commercial value. Photon correlator is used in photon correlation spectroscopy experiment to gain the photon correlation function. In order to obtain the accurate values of the photon correlation, efficient and accurate photon correlator must be designed. This paper presents one kind of photon correlator implemented by FPGA. The programming language used is Verilog HDL. The software design and system simulation are completed in t

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15

Bhuvaneswari, Thangavel, Nor Hidayati Abdul Aziz, Jakir Hossen, and Chinthakunta Venkataseshaiah. "Field Programmable Gate Array (FPGA) Based Microwave Oven." Applied Mechanics and Materials 892 (June 2019): 120–26. http://dx.doi.org/10.4028/www.scientific.net/amm.892.120.

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In this paper, an FPGA-based microwave oven controller design which can be implemented using Altera DE1 development board is presented. The motivation for this work is to explore FPGA for real time applications. First, a microwave oven controller design architecture that could fit into Altera DE1 board, utilizing on-board peripherals is developed. Then, using the proposed architecture, the design is implemented using Verilog HDL. The microwave oven functionalities are demonstrated using Altera DE1 development board by means of Quartus II 13.0 software. The testbenches are created and waveforms

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16

Pochet, L. M., M. L. Linderman, S. L. Drager, and R. L. Kohler. "Field-Programmable Gate-Array-Based Graph Coloring Accelerator." Journal of Spacecraft and Rockets 39, no. 4 (2002): 474–80. http://dx.doi.org/10.2514/2.3852.

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17

LI, XIAOYING, and ENHUA WU. "RELIEF TEXTURE MAPPING ON FIELD PROGRAMMABLE GATE ARRAY." International Journal of Image and Graphics 06, no. 04 (2006): 641–55. http://dx.doi.org/10.1142/s021946780600246x.

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Relief texture mapping is an image-based rendering technique which can successfully support the representation of 3D surface details and view motion parallax. It has the potential to significantly increase visual realism of rendered geometry while keeping system load constant. In this paper, FPGA (Field Programmable Gate Array) chip technology is applied to this three-dimensional image warping method. A relief texture mapping system has been implemented on a reprogrammable and reconfigurable FPGA board. The algorithm is optimized for the specific architecture and the framework is customized fo

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18

Phang, A. P. Y., R. E. Challis, V. G. Ivchenko, and A. N. Kalashnikov. "A field programmable gate array-based ultrasonic spectrometer." Measurement Science and Technology 19, no. 4 (2008): 045802. http://dx.doi.org/10.1088/0957-0233/19/4/045802.

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19

Agarwal, A., and V. Agarwal. "Field programmable gate array-based delta-modulated cycloinverter." IET Power Electronics 5, no. 9 (2012): 1793–803. http://dx.doi.org/10.1049/iet-pel.2011.0476.

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20

Macleod, Todd C., and Fat Duen Ho. "Design of a Ferroelectric Programmable Logic Gate Array." Integrated Ferroelectrics 56, no. 1 (2003): 1013–21. http://dx.doi.org/10.1080/10584580390259506.

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21

Li, Xu, Xing Guang Qi, Qing Hua Li, Ning Wang, and Li Peng Wang. "Photon Counter Implemented by Field Programmable Gate Array." Advanced Materials Research 591-593 (November 2012): 1396–99. http://dx.doi.org/10.4028/www.scientific.net/amr.591-593.1396.

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Photon correlation technique is an effective method for measuring the particle size of sub-micron particles and nanoparticles. This tenchnology has a good prospect and commerical value. Photon counter is used in photon correlation spectroscopy experiment to gain the intensity of photon. In order to obtain the accurate values of the photon correlation, efficient and accurate photon counter must be designed. This paper presents two kinds of photon counters implemented by FPGA. The programming language used is Verilog HDL. The software design and system simulation are completed in the integration

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22

Basu, Arindam, Stephen Brink, Craig Schlottmann, et al. "A Floating-Gate-Based Field-Programmable Analog Array." IEEE Journal of Solid-State Circuits 45, no. 9 (2010): 1781–94. http://dx.doi.org/10.1109/jssc.2010.2056832.

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23

Vásquez, José L., Santiago T. Pérez, Carlos M. Travieso, and Jesús B. Alonso. "Meteorological Prediction Implemented on Field-Programmable Gate Array." Cognitive Computation 5, no. 4 (2012): 551–57. http://dx.doi.org/10.1007/s12559-012-9158-z.

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24

Haines, Andrew. "Field-programmable gate array with non-volatile configuration." Microprocessors and Microsystems 13, no. 5 (1989): 305–12. http://dx.doi.org/10.1016/0141-9331(89)90086-0.

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25

Wunderlich, Richard B., Farhan Adil, and Paul Hasler. "Floating Gate-Based Field Programmable Mixed-Signal Array." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 8 (2013): 1496–505. http://dx.doi.org/10.1109/tvlsi.2012.2211049.

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26

Nazar, Gabriel Luca, Leonardo Pereira Santos, and Luigi Carro. "Fine-Grained Fast Field-Programmable Gate Array Scrubbing." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, no. 5 (2015): 893–904. http://dx.doi.org/10.1109/tvlsi.2014.2330742.

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27

El-Medany, Wael M. "Field Programmable Gate Array System for IoT Applications." International Journal of Computing and Network Technology 4, no. 3 (2016): 165–73. http://dx.doi.org/10.12785/ijcnt/040307.

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28

El-Medany, Wael M. "Field Programmable Gate Array System for IoT Applications." International Journal of Computing and Network Technology 4, no. 3 (2016): 165–73. http://dx.doi.org/10.12785/ijcts/040307.

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29

Vorwerk, K., M. Raman, A. Kundu, et al. "Power minimisation during field programmable gate array placement." IET Computers & Digital Techniques 4, no. 3 (2010): 170–83. http://dx.doi.org/10.1049/iet-cdt.2009.0008.

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30

Husni, Muhammed Ihsan, Mohammed Kareem Hussein, Mohd Shamian Bin Zainal, Anuar Bin Hamzah, Danial Bin Md Nor, and Hazwaj Bin Mhd Poad. "Soil Moisture Monitoring Using Field Programmable Gate Array." Indonesian Journal of Electrical Engineering and Computer Science 11, no. 1 (2018): 169. http://dx.doi.org/10.11591/ijeecs.v11.i1.pp169-174.

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This paper presents a solution for remote monitoring and sensing of different agricultural parameters that effect the plant growth and productivity. Hardware descriptive language has been used for the implementation of proposed topology on Field Programmable Gate Arrays. The hardware used for this purpose is an Altera board. The simulated results take into consideration the environmental factors such as the humidity, soil moisture content and the temperature. The proposed system continuously monitors the environmental changes for any updates. The system also controls a water motor that is turn

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31

Muhammed, Ihsan Husni, Kareem Hussein Mohammed, Shamian Bin Zainal Mohd, Anuar Bin Hamzah Shipun, Bin Md Nor Danial, and Bin Mhd Poad Hazwaj. "Soil Moisture Monitoring Using Field Programmable Gate Array." Indonesian Journal of Electrical Engineering and Computer Science 11, no. 1 (2018): 169–74. https://doi.org/10.11591/ijeecs.v11.i1.pp169-174.

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This paper presents a solution for remote monitoring and sensing of different agricultural parameters that effect the plant growth and productivity. Hardware descriptive language has been used for the implementation of proposed topology on Field Programmable Gate Arrays. The hardware used for this purpose is an Altera board. The simulated results take into consideration the environmental factors such as the humidity, soil moisture content and the temperature. The proposed system continuously monitors the environmental changes for any updates. The system also controls a water motor that is turn

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32

Xu, Guo Sheng. "Design of Data Acquisition System Based on FPGA." Advanced Materials Research 403-408 (November 2011): 1592–95. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.1592.

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A new kind of data acquisition system is introduced in this paper, in which the multi-channel synchronized real-time data acquisition under the coordinate control of field-programmable gate array(FPGA) is realized. The design uses field programmable gate arrays(FPGA) for the data processing and logic control. For high speed CCD image data processing, the paper adopts regional parallel processing based on FPGA. The FPGA inner block RAM is used to build high speed image data buffer is put into operation to achieve high speed image data integration and real-time processing. The proposed data acqu

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33

Gordon, David, Christian Wouters, Maximilian Wick, et al. "Development and experimental validation of a real-time capable field programmable gate array–based gas exchange model for negative valve overlap." International Journal of Engine Research 21, no. 3 (2018): 421–36. http://dx.doi.org/10.1177/1468087418788491.

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Homogeneous charge compression ignition has the potential to significantly reduce NO x emissions, while maintaining a high fuel efficiency. Homogeneous charge compression ignition is characterized by compression-induced autoignition of a lean homogeneous air–fuel mixture. Combustion timing is highly dependent on the in-cylinder state including pressure, temperature and trapped mass. To control homogeneous charge compression ignition combustion, it is necessary to have an accurate representation of the gas exchange process. Currently, microprocessor-based engine control units require that the g

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34

Patel, Dhruv, Jignesh Bhatt, and Sanjay Trivedi. "Programmable logic controller performance enhancement by field programmable gate array based design." ISA Transactions 54 (January 2015): 156–68. http://dx.doi.org/10.1016/j.isatra.2014.08.019.

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35

Lyu, Congyi, Haoyao Chen, Xin Jiang, Peng Li, and Yunhui Liu. "Real-time object tracking system based on field-programmable gate array and convolution neural network." International Journal of Advanced Robotic Systems 14, no. 1 (2016): 172988141668270. http://dx.doi.org/10.1177/1729881416682705.

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Vision-based object tracking has lots of applications in robotics, like surveillance, navigation, motion capturing, and so on. However, the existing object tracking systems still suffer from the challenging problem of high computation consumption in the image processing algorithms. The problem can prevent current systems from being used in many robotic applications which have limitations of payload and power, for example, micro air vehicles. In these applications, the central processing unit- or graphics processing unit-based computers are not good choices due to the high weight and power cons

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36

Shieh, Cheng Shion. "From Simulation to FPGA Control Circuit Implementation for Wind Power with Battery Charging." Advanced Materials Research 588-589 (November 2012): 777–80. http://dx.doi.org/10.4028/www.scientific.net/amr.588-589.777.

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While application of field-programmable gate array (FPGA) chip has been extensively investigated, the charging control is relatively unexplored. This paper proposes a flow chart of energy storage for wind power system with Lead-Acid battery whose charging control is constructed by Very High Speed Integrated Circuit Hardware Description Language (VHDL) code. This research focuses on the proposed digital control algorithm can be directly downloaded into field-programmable gate array (FPGA) chip after simulation finishing. This saves greatly time on hardware circuit design. A simulation is presen

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37

Govil, Anchal, Anmol Karnwal, Govinda Sindhu, Ayush Singh, and Dr Shubham Shukla. "Design and Implementation of UART Using FPGA Board." International Journal for Research in Applied Science and Engineering Technology 10, no. 4 (2022): 1187–90. http://dx.doi.org/10.22214/ijraset.2022.41478.

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Abstract: This paper introduces the implementation of the Universal Asynchronous Receiver- Transmitter Controller (UART) based on Microprogrammed Controller on Field Programmable Gate Array (FPGA. Our UART design is fully functional and built-in. Coded using the Verilog design from top to bottom and visible in Spartan-3E FPGA using Xilinx ISE Webpack 14.7. Use results show that the design can work Spartan-3E FPGA maximum clock frequency of 218.248 MHz. The maximum frequent use of the UART controller is 192.773 MHz. of bits and hence this is why with a small amount of storage. Keywords: Receive

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38

Ji, Shuai, Chengrui Zhang, Tianliang Hu, and Ke Wang. "A Hardware Independent Real-time Ethernet for Motion Control Systems." International Journal of Computers Communications & Control 11, no. 1 (2015): 39. http://dx.doi.org/10.15837/ijccc.2016.1.617.

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Ethernet for Manufacture Automation Control (EtherMAC) is a new kind of real-time Ethernet used in motion control systems. It adopts a line topology with a standard industrial computer based master node and field-programmable-gate-array based slave nodes. EtherMAC employs one slave node to manage cycle communication and clock synchronization, so the real-time demand for its master node can be greatly reduced and dedicated hardware is no longer mandatory. Its distributed clock compensation mechanism can get synchronization accuracy in nanosecond order. The advantages of industrial computer and

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39

Mallikarjuna, Gowda C. P., and Hajare Raju. "Space-time trellis codes: Field programmable gate array approach." International Journal of Reconfigurable and Embedded Systems 9, no. 3 (2020): 213–23. https://doi.org/10.11591/ijres.v9.i3.pp213-223.

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In this paper, an effective method of implementation of Space-Time Trellis Codes (STTC) for 4-state on Field Programmable Gate Array is presented. To reach the very high data rates provided in STTC, a lot of expensive highspeed Digital Signal Processors (DSPs) should be employed for the real time applications, while it might not be affordable. This fact has motivated in designing dedicated hardware implementations using Field Programmable Gate Array (FPGA) with low cost and power consumption. The hardware device XC3S400, family Xilinx Spartan-3, and package PQ208 are used in this project, in w

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40

Van Noije, W. A. M., and G. J. Declerck. "Advanced CMOS gate array architecture combining `gate isolation' and programmable routing channels." IEEE Journal of Solid-State Circuits 20, no. 2 (1985): 469–80. http://dx.doi.org/10.1109/jssc.1985.1052332.

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41

Shaw Terrill, Richard. "Development of a 50,000-gate programmable logic device for gate array prototyping." Microelectronics Journal 25, no. 6 (1994): xix—xxii. http://dx.doi.org/10.1016/0026-2692(94)90058-2.

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42

Fuengfusin, Ninnart, and Hakaru Tamukoh. "Mixed-precision weights network for field-programmable gate array." PLOS ONE 16, no. 5 (2021): e0251329. http://dx.doi.org/10.1371/journal.pone.0251329.

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In this study, we introduced a mixed-precision weights network (MPWN), which is a quantization neural network that jointly utilizes three different weight spaces: binary {−1,1}, ternary {−1,0,1}, and 32-bit floating-point. We further developed the MPWN from both software and hardware aspects. From the software aspect, we evaluated the MPWN on the Fashion-MNIST and CIFAR10 datasets. We systematized the accuracy sparsity bit score, which is a linear combination of accuracy, sparsity, and number of bits. This score allows Bayesian optimization to be used efficiently to search for MPWN weight spac

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43

Mowafy, Aya Nabeel. "Asynchronous Circuits Design Using a Field Programmable Gate Array." International Journal for Research in Applied Science and Engineering Technology 6, no. 4 (2018): 2423–32. http://dx.doi.org/10.22214/ijraset.2018.4412.

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44

Балбаев, Г. К. "ТЕХНОЛОГИЯ FPGA (FIELD PROGRAMMABLE GATE ARRAY) ДЛЯ КОСМИЧЕСКОЙ СВЯЗИ". Вестник Академии гражданской авиации, № 1 (2022): 34–38. http://dx.doi.org/10.53364/24138614_2022_24_1_34.

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45

Amirany, Abdolah, Kian Jafari, and Mohammad Hossein Moaiyeri. "A Task-Schedulable Nonvolatile Spintronic Field-Programmable Gate Array." IEEE Magnetics Letters 12 (2021): 1–4. http://dx.doi.org/10.1109/lmag.2021.3092995.

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46

YANG, Jung-Lin, Shin-Nung LU, and Pei-Hsuan YU. "Asynchronous Circuit Design on Field Programmable Gate Array Devices." IEICE Transactions on Electronics E95-C, no. 4 (2012): 516–22. http://dx.doi.org/10.1587/transele.e95.c.516.

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47

Kurniawan, Yusuf, and Muhammad Adli Rizqulloh. "Block cipher four implementation on field programmable gate array." Communications in Science and Technology 5, no. 2 (2020): 53–64. http://dx.doi.org/10.21924/cst.5.2.2020.184.

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Block ciphers are used to protect data in information systems from being leaked to unauthorized people. One of many block cipher algorithms developed by Indonesian researchers is the BCF (Block Cipher-Four) - a block cipher with 128-bit input/output that can accept 128-bit, 192-bit, or 256-bit keys. The BCF algorithm can be used in embedded systems that require fast BCF implementation. In this study, the design and implementation of the BCF engine were carried out on the FPGA DE2. It is the first research on BCF implementation in FPGA. The operations of the BCF machine were controlled by Nios

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48

Stanko, S., B. Klein, and J. Kerp. "A field programmable gate array spectrometer for radio astronomy." Astronomy & Astrophysics 436, no. 1 (2005): 391–95. http://dx.doi.org/10.1051/0004-6361:20042227.

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49

Masui, S., T. Ninomiya, M. Oura, W. Yokozeki, K. Mukaida, and S. Kawashima. "A ferroelectric memory-based secure dynamically programmable gate array." IEEE Journal of Solid-State Circuits 38, no. 5 (2003): 715–25. http://dx.doi.org/10.1109/jssc.2003.810034.

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50

Lingyan Sun, Hongwei Song, Z. Keirn, and B. V. K. V. Kumar. "Field programmable gate array (FPGA) for iterative code evaluation." IEEE Transactions on Magnetics 42, no. 2 (2006): 226–31. http://dx.doi.org/10.1109/tmag.2005.861744.

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