Relevant bibliographies by topics / Programmable interconnect

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Programmable interconnect'

Author: Grafiati
Published: 4 June 2021
Last updated: 5 February 2022

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Journal articles on the topic "Programmable interconnect"

1

DeHon, A. "Unifying mesh- and tree-based programmable interconnect." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12, no. 10 (2004): 1051–65. http://dx.doi.org/10.1109/tvlsi.2004.834237.

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Yazdanshenas, Sadegh, and Vaughn Betz. "Interconnect Solutions for Virtualized Field-Programmable Gate Arrays." IEEE Access 6 (2018): 10497–507. http://dx.doi.org/10.1109/access.2018.2806618.

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Ching-Wei Yeh, Lung-Tien Liu, Chung-Kuan Cheng, T. C. Hu, S. Ahmed, and M. Liddell. "Block-oriented programmable design with switching network interconnect." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2, no. 1 (1994): 45–53. http://dx.doi.org/10.1109/92.273149.

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Marrakchi, Zied, Hayder Mrabet, Umer Farooq, and Habib Mehrez. "FPGA Interconnect Topologies Exploration." International Journal of Reconfigurable Computing 2009 (2009): 1–13. http://dx.doi.org/10.1155/2009/259837.

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This paper presents an improved interconnect network for Tree-based FPGA architecture that unifies two unidirectional programmable networks. New tools are developed to place and route the largest benchmark circuits, where different optimization techniques are used to get an optimized architecture. The effect of variation in LUT and cluster size on the area, performance, and power of the Tree-based architecture is analyzed. Experimental results show that an architecture with LUT size 4 and arity size 4 is the most efficient in terms of area and static power dissipation, whereas the architecture
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Snider, Gregory S., and R. Stanley Williams. "Nano/CMOS architectures using a field-programmable nanowire interconnect." Nanotechnology 18, no. 3 (2007): 035204. http://dx.doi.org/10.1088/0957-4484/18/3/035204.

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Zhang, Fan, Chenguang Guo, Shifeng Zhang, et al. "Research on Hex Programmable Interconnect Points Test in Island-Style FPGA." Electronics 9, no. 12 (2020): 2177. http://dx.doi.org/10.3390/electronics9122177.

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With the decreasing size of manufacturing process, the scale of island-style field programmable gate array (FPGA) becomes larger, which leads to the increasing complexity of FPGA routing resources, especially hex programmable interconnect points (PIPs). Hex PIPs which span six tiles of the island-style FPGA have complex interconnect rules. Accordingly, research on complete hex PIPs test is rarely involved in the study of routing resources test. Therefore, this paper analyzes the hex PIPs architecture of the island-style FPGA, summarizes the interconnect rules of the hex PIPs mathematically in
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Li, Jian, Tom E. Seidel, and Jim W. Mayer. "Copper-Based Metallization in ULSI Structures: Part II: Is Cu Ahead of Its Time as an On-Chip Interconnect Material?" MRS Bulletin 19, no. 8 (1994): 15–21. http://dx.doi.org/10.1557/s0883769400047692.

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The demand for manufacturing integrated circuit (IC) devices such as dynamic random access memory (DRAM), static random access memory (SRAM), electrically erasable and programmable read only memory (EEPROM) and logic devices with high circuit speed, high packing density and low power dissipation requires the downward scaling of feature sizes in ultralarge-scale integration (ULSI) structures. When chip size becomes smaller, the propagation delay time in a device is reduced. However, the importance of on-chip interconnect RC (resistance capacitance) delay to chip performance, reliability, and pr
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Zhang, Jie, Na Zhang, Xu Ming Zhu, Yong Guan, and Yong Mei Liu. "A Survey of Diagnosis Method for Interconnect in SRAM-Based FPGAs." Key Engineering Materials 474-476 (April 2011): 1949–54. http://dx.doi.org/10.4028/www.scientific.net/kem.474-476.1949.

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To further improve the fault coverage and accuracy of fault location in SRAM based on FPGAs interconnect, an efficient method of fault detection and location is presented. Eight types of programming based on multiple times programmable FPGA is used, and further improved fault coverage and accuracy of fault location. Analysis showed that the proposed methods could cover all interconnect single faults and locate five single faults to specific switch or locate bridge fault to a pair of segments.
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Lee, Edmund, Guy Lemieux, and Shahriar Mirabbasi. "Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays." Journal of Signal Processing Systems 51, no. 1 (2007): 57–76. http://dx.doi.org/10.1007/s11265-007-0141-y.

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Yen, Mao-Hsu, Sao-Jie Chen, and Sanko H. Lan. "Symmetric and Programmable Multi-Chip Module for Low-Power Prototyping System." VLSI Design 12, no. 2 (2001): 113–24. http://dx.doi.org/10.1155/2001/19261.

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The advantages of a Multi-Chip Module (MCM) product are its low-power and small-size. But the design of an MCM system usually requires weeks of engineering effort, thus we need a generic MCM substrate with programmable interconnections to accelerate system prototyping. In this paper, we propose a Symmetric and Programmable MCM (SPMCM) substrate for this purpose. This SPMCM substrate consists of a symmetrical array of slots for bare-chip attachment and Field Programmable Interconnect Chips (FPICs) for substrate routing. Experimental results demonstrate that our FPIC polygonal routing module use
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Dissertations / Theses on the topic "Programmable interconnect"

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HAWK, CHRISTOPHER J. "DESIGN OF A PROGRAMMABLE ROUTING FRAMEWORK FOR MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1076114416.

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Dixon, Bobby Earl Stroud Charles E. "Built-in self-test of the programmable interconnect in field programmable gate arrays." Auburn, Ala, 2008. http://repo.lib.auburn.edu/EtdRoot/2008/FALL/Electrical_and_Computer_Engineering/Thesis/Dixon_Bobby_16.pdf.

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Royal, Andrew Peter. "Globally asynchronous locally synchronous interconnect for field programmable gate arrays." Thesis, Imperial College London, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.415717.

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Campregher, Nicola. "Interconnect yield analysis and fault tolerance for field programmable gate arrays." Thesis, Imperial College London, 2007. http://hdl.handle.net/10044/1/11966.

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Teehan, Paul Leonard. "Reliable high-throughput FPGA interconnect using source-synchronous surfing and wave pipelining." Thesis, University of British Columbia, 2008. http://hdl.handle.net/2429/2767.

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FPGA clock frequencies are slow enough that only a fraction of the interconnect’s bandwidth is used. By exploiting this bandwidth, the transfer of large amounts of data can be greatly accelerated. Alternatively, it may also be possible to save area on fixed-bandwidth links by using on-chip serial signaling. For datapath-intensive designs which operate on words instead of bits, this can reduce wiring congestion as well. This thesis proposes relatively simple circuit-level modifications to FPGA interconnect to enable high-bandwidth communication. High-level area estimates indicate a potential in
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Rehman, Saif Ur. "Développement des techniques de test et de diagnostic pour les FPGA hiérarchique de type mesh." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT110/document.

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L’évolution tendant à réduire la taille et augmenter la complexité des circuits électroniques modernes, est en train de ralentir du fait des limitations technologiques, qui génèrent beaucoup de d’imperfections et de defaults durant la fabrication ou la durée de vie de la puce. Les FPGAs sont utilisés dans les systèmes numériques complexes, essentiellement parce qu’ils sont reconfigurables et rapide à commercialiser. Pour garder une grande fiabilité de tels systèmes, les FPGAs doivent être testés minutieusement pour les defaults. L’optimisation de l’architecture des FPGAs pour l’économie de sur
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Charlery, Hervé Robert. "Integration d' un micro-réseau à commutation de paquets dans un système multiprocesseur à mémoire partagée intégré sur puce." Paris 6, 2005. http://www.theses.fr/2005PA066486.

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Juang, Shun-Fu, and 莊順富. "A Field Programmable Interconnect Chip." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/68265210482038562213.

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Nguyen, Hung. "Rapid prototyping using field programmable gate array (FPGA) and field programmable interconnect devices (FPID)." 1996. http://hdl.handle.net/1993/19271.

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Wu-Pin, Chan, and 詹戊賓. "VLSI Design of A Polygonal Field Programmable Interconnect Chip." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/14069940778773868662.

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碩士<br>國立臺灣科技大學<br>電子工程系<br>87<br>In this thesis, we explore the routing network of PMCM (Programmable Multiple Chip Module) system. In order to facilitate a cost effective routing network with dynamic programming feature, an FPIC (Field Programmable Interconnect Chip) is designed and implemented with CMOS technology. The major feature of the proposed FPIC are as follow: It adapts a polygonal routing module instead of the conventional square routing module, and uses the concept of virtual wire to effectively provide more virtual I/O pins for solving the pin limitation problem: usual
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Books on the topic "Programmable interconnect"

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Lemieux, Guy. Design of interconnection networks for programmable logic. Kluwer Academic, 2003.

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David, Lewis, ed. Design of interconnection networks for programmable logic. Kluwer Academic Publishers, 2004.

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Lemieux, Guy. Design of interconnection networks for programmable logic. 2004.

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Lewis, David, and Guy Lemieux. Design of Interconnection Networks for Programmable Logic. Springer, 2003.

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Book chapters on the topic "Programmable interconnect"

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Leasure, Bruce, David J. Kuck, Sergei Gorlatch, et al. "Programmable Interconnect Computer." In Encyclopedia of Parallel Computing. Springer US, 2011. http://dx.doi.org/10.1007/978-0-387-09766-4_2291.

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Campregher, Nicola, Peter Y. K. Cheung, and Milan Vasilko. "BIST Based Interconnect Fault Location for FPGAs." In Field Programmable Logic and Application. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30117-2_34.

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Krishnan, Rohini, Jose Pineda de Gyvez, and Harry J. M. Veendrick. "Encoded-Low Swing Technique for Ultra Low Power Interconnect." In Field Programmable Logic and Application. Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-45234-8_24.

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Bansal, Nikhil, Sumit Gupta, Nikil Dutt, Alex Nicolau, and Rajesh Gupta. "Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures." In Field Programmable Logic and Application. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30117-2_95.

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Huang, Renqiu, Manish Handa, and Ranga Vemuri. "Analysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable FPGAs." In Field Programmable Logic and Application. Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30117-2_96.

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Toon, Nigel. "Continuous interconnect provides solution to density/performance trade-off in programmable logic." In Field-Programmable Logic Architectures, Synthesis and Applications. Springer Berlin Heidelberg, 1994. http://dx.doi.org/10.1007/3-540-58419-6_104.

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Ramalingam, Suresh, Henley Liu, Myongseob Kim, et al. "A New Class of High-Capacity, Resource-Rich Field-Programmable Gate Arrays Enabled by Three- Dimensional Integration Chip-Stacked Silicon Interconnect Technology." In 3D Integration in VLSI Circuits. CRC Press, 2018. http://dx.doi.org/10.1201/9781315200699-3.

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Symington, Keith J., John F. Snowdon, and Heiko Schroeder. "High Bandwidth Dynamically Reconfigurable Architectures Using Optical Interconnects." In Field Programmable Logic and Applications. Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/978-3-540-48302-1_46.

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Belkacemi, Dihia, Mehammed Daoui, and Samia Bouzefrane. "Parallel Applications Mapping onto Heterogeneous MPSoCs Interconnected Using Network on Chip." In Mobile, Secure, and Programmable Networking. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-67550-9_9.

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Turner, J., R. Cliff, W. Leong, et al. "Migration of a dual granularity globally interconnected PLD architecture to a 0.5μ TLM process." In Field-Programmable Logic and Applications. Springer Berlin Heidelberg, 1995. http://dx.doi.org/10.1007/3-540-60294-1_94.

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Conference papers on the topic "Programmable interconnect"

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DeHon, André. "Entropy, counting, and programmable interconnect." In the 1996 ACM fourth international symposium. ACM Press, 1996. http://dx.doi.org/10.1145/228370.228381.

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DeHon, A. "Entropy, Counting, and Programmable Interconnect." In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242346.

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DeHon, André. "Design of programmable interconnect for sublithographic programmable logic arrays." In the 2005 ACM/SIGDA 13th international symposium. ACM Press, 2005. http://dx.doi.org/10.1145/1046192.1046210.

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Lombardi, Fabrizio, David Ashen, Xiaotao Chen, and Wei Kang Huang. "Diagnosing programmable interconnect systems for FPGAs." In the 1996 ACM fourth international symposium. ACM Press, 1996. http://dx.doi.org/10.1145/228370.228385.

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Hutton, Michael. "Interconnect prediction for programmable logic devices." In the 2001 international workshop. ACM Press, 2001. http://dx.doi.org/10.1145/368640.368816.

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Lombardi, F., D. Ashen, Xiaotao Chen, and Wei Kang Huang. "Diagnosing Programmable Interconnect Systems for FPGAs." In Fourth International ACM Symposium on Field-Programmable Gate Arrays. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.242436.

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Chenming Hu. "Interconnect devices for field programmable gate array." In Proceedings of IEEE International Electron Devices Meeting. IEEE, 1992. http://dx.doi.org/10.1109/iedm.1992.307430.

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Marrakchi, Zied, Hayder Mrabet, Christian Masson, and Habib Mehrez. "Efficient Mesh of Tree Interconnect for FPGA Architecture." In 2007 International Conference on Field-Programmable Technology. IEEE, 2007. http://dx.doi.org/10.1109/fpt.2007.4439263.

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Rodionov, Alex, David Biancolin, and Jonathan Rose. "Fine-Grained Interconnect Synthesis." In FPGA '15: The 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. ACM, 2015. http://dx.doi.org/10.1145/2684746.2689061.

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Haile Yu, Yuk Hei Chan, and Philip H. W. Leong. "FPGA interconnect design using logical effort." In 2008 International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2008. http://dx.doi.org/10.1109/fpl.2008.4629980.

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