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Dissertations / Theses on the topic 'Programmable Switch'

Author: Grafiati

Published: 4 June 2021

Last updated: 15 February 2022

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1

HAWK, CHRISTOPHER J. "DESIGN OF A PROGRAMMABLE ROUTING FRAMEWORK FOR MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY." University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1076114416.

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2

Gruesen, Michael G. "Towards an Ideal Execution Environment for Programmable Network Switches." University of Akron / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=akron1468834070.

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3

Ji, Shengjie. "DE4NF : HIGH PERFORMANCE NFV FRAMEWORKWITH P4-BASED EVENT SYSTEM." Case Western Reserve University School of Graduate Studies / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=case1588000703683216.

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4

Toresson, Ludwig. "Making a Packet-value Based AQM on a Programmable Switch for Resource-sharing and Low Latency." Thesis, Karlstads universitet, Institutionen för matematik och datavetenskap (from 2013), 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kau:diva-82568.

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There is a rapidly growing number of advanced applications running over the internet that requires ultra-low latency and high throughput. Bufferbloat is one of the most known problems which add delay in the form of packets being enqueued into large buffers before being transmitted. This has been solved with the developments of various Active Queue Management (AQM) schemes to control how large the queue buffers are allowed to grow. Another aspect that is important today is how the available bandwidth can be shared between applications with different priorities. The Per-Packet Value (PPV) concep

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5

Isaacson, Spencer W. "Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip." BYU ScholarsArchive, 2007. https://scholarsarchive.byu.edu/etd/971.

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Current FPGA technology has advanced to the point that useful embedded SoPCs can now be designed. The Real Time Processor (RTP) project at Brigham Young University leverages the advances in FPGA technology with a system architecture that is customizable to specific applications. A simple real-time processor has been designed to provide support for a hardware-assisted real-time operating system providing fast context switches. As part of the hardware RTOS, the following have been implemented in hardware: scheduler, register banks, mutex, semaphore, queue, interrupts, event, and others. A novel

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6

SAMSANI, SIVA PRASAD REDDY. "MODELING OF I/O BLOCK AND SWITCH BLOCK FOR SECOND GENERATION MULTI-TECHNOLOGY FIELD PROGRAMMABLE GATE ARRAY (MT-FPGA)." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1138326310.

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7

Lindström, Henrik. "Migration to P4-Programmable Switches and Implementation of the Rapid Spanning Tree Protocol." Thesis, Linköpings universitet, Programvara och system, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-167509.

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P4 is a high-level language for programming the data plane of a network switch. These P4-programmable switches come with no pre-defined behavior or protocols, so it is entirely up to the loaded P4 program to define these. This allows the user to exclude any unwanted functionality and to create custom protocols. It also removes the dependence on the switch vendor in terms of both trust and addition of new features. This thesis looks at migration from traditional switches to P4-programmable ones. Since no behavior is included out-of-the-box in the P4 switches, a search is made for open-source P4

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8

Gray, Jordan D. "Application of Floating-Gate Transistors in Field Programmable Analog Arrays." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7540.

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Floating-gate transistors similar to those used in FLASH and EEPROM can be used to build reconfigurable analog arrays. The charge on the floating gate can be modified to pass or block a signal in a cross-bar switch matrix, or it can be finely tuned to eliminate a threshold difference across a chip or set a bias. By using such a compact and versatile reconfigurable analog memory element, the number of analog circuit components included on an integrated circuit that is field-programmable is significantly higher. As a result, large-scale FPAAs can be built with the same impact on analog design

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Kapkar, Rohan Viren. "Modeling and Simulation of Altera Logic Array Block using Quantum-Dot Cellular Automata." University of Toledo / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1304616947.

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10

Yalkin, Cengiz. "Digitally controlled programmable active switched capacitor filters." Thesis, Monterey, California. Naval Postgraduate School, 1987. http://hdl.handle.net/10945/22244.

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11

Chang, Simon. "A switched current field programmable analogue array." Thesis, University of Nottingham, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.284425.

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12

Chen, Derrick. "TSFPGA, a time-switched field-programmable gate array." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/41373.

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13

Lacy, Cameron. "Design of a programmable switched-capacitor analog FIR filter." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0007/MQ46200.pdf.

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14

Forgione, Alessandro. "Openflow e software-defined networking: l'evoluzione della rete programmabile." Bachelor's thesis, Alma Mater Studiorum - Università di Bologna, 2014. http://amslaurea.unibo.it/7919/.

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Il paradigma “Software-Defined Networking” (SDN) ha suscitato recentemente interesse grazie allo sviluppo e all'implementazione di uno standard tecnologico come OpenFlow. Con il modello SDN viene proposta una rete programmabile tramite la separazione dell’unità di controllo e l'unità di instradamento, rendendo quindi i nodi di rete (come ad es. router o switch) esclusivamente hardware che inoltra pacchetti di dati secondo le regole dettate dal controller. OpenFlow rappresenta lo standard dominante nella tecnologia SDN in grado di far comunicare l'unità controller e l'hardware di uno o più nodi

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Larsson, Rasmus. "Creating Digital Twin Distributed Networks Using Switches With Programmable Data Plane." Thesis, Linköpings universitet, Programvara och system, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-175359.

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The domain specific language P4 is a novel initiative which extends the Software-Defined Networking (SDN) paradigm by allowing for data plane programmability. Network virtualisation is a class of network technologies which can be used to abstract the addressing in a network, allowing multiple tenants to utilise the network resources while being agnostic to the underlying network and the other tenants. In other words, twins of tenants using the same addresses can co-exist on the same underlying network. If a twin is a distributed network, it may even be spread out across multiple sites which ar

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Tallhage, Jonas. "Construction of a Low-Noise Amplifier Chain With Programmable Gain and Offset." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-106143.

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A low-noise, variable gain amplier chain was constructed for interfa-cing a sensor to an ADC. During the course of the work two dierent methods -switched-capacitor circuits and chopping circuits - for dealing with 1/f noise wereinvestigated during the course of the work. The resulting circuit did not quitemeet the performance required by the specication, some possible improvementsare suggested.

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Wicaksana, Arief. "Infrastructure portable pour un système hétérogène reconfigurable dans un environnement de cloud-FPGA." Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT088/document.

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La haute performance ainsi que la basse consommation d’énergie offertes par lesField-Programmable Gate Arrays (FPGAs) contribuent à leur popularité en tant queaccélérateurs matériels. Cet argument a été soutenu par les intégrations récentes des FPGAs dans des systèmes cloud et centre de données. Toutefois, le potentiel d’une architecture reconfigurable peut être encore optimisé en traitant les FPGAs comme une ressource virtualisée et en les offrant une capacité de multitâche. La solution pour interrompre une tâche sur FPGAs à pour objectif d’effectuer un changement de contexte matériel (hardwa

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18

Hilton, Clint Richard. "A Flexible Circuit-Switched Communication Network for FPGA-Based SOC Design." Diss., CLICK HERE for online access, 2005. http://contentdm.lib.byu.edu/ETD/image/etd799.pdf.

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Bourge, Alban. "Changement de contexte matériel sur FPGA, entre équipements reconfigurables et hétérogènes dans un environnement de calcul distribué." Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAT068/document.

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Architectures reconfigurables dynamiquement offrent théoriquement excellent compromis entre performance et flexibilité. Pratiquement, ces architectures sont basées sur un ou plusieurs processeurs et plusieurs cellules reconfigurables. Une cellule reconfigurable peut charger, exécuter et décharger des accélérateurs matériels. Cette propriété permet la virtualisation des tâches matérielles. Dans ce contexte, une application peut prendre avantage de la flexibilité du logiciel et la performance du matériel. Dans les architectures reconfigurables actuels, les tâches matérielles sont limitées à une

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Měřínský, Jiří. "CAE systém EPLAN Electric P8 - tvorba výkresové dokumentace pro dálkové ovládání motorgenerátoru." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2010. http://www.nusl.cz/ntk/nusl-218804.

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This Graduation Theses dissertate about a creation of a drawing documentation at the professional CAE EPLAN Electric P8 system. One original solution of a remote control and of motor-generator monitoring with a mobile phone, short SMS-aided in this case, was used as an example of the drawing documentation. As has allready been noted in previous Bachelor Thesis, this application can be use not only for a remote control of a motor-generator, but this solution is suitable for other electric devices too, which are out of reach of an attendance for example. In our case a generator with 6kVA power i

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Bezerra, Thiago Brito. "DESENVOLVIMENTO DE UM CONVERSOR A/D INTEGRADOR COM FAIXA DE ENTRADA E RESOLUÇÃO PROGRAMÁVEL A CAPACITOR CHAVEADO." Universidade Federal do Maranhão, 2012. http://tedebc.ufma.br:8080/jspui/handle/tede/486.

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Made available in DSpace on 2016-08-17T14:53:20Z (GMT). No. of bitstreams: 1 Tiago Brito Bezerra.pdf: 3848907 bytes, checksum: 09c5f40ad1ac5ce43a253e0335d491da (MD5) Previous issue date: 2012-04-13<br>Coordenação de Aperfeiçoamento de Pessoal de Nível Superior<br>Programmable integrated circuits enable its adjustment after fabrication to fit more than one application within a certain set of applications. A programmable measurement system can be applied to the measurement of different quantities involving a set of sensors with different signal characteristics and employing a single analog-t

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Li, Nan. "Digital control strategies for DC/DC SEPIC converters towards integration." Phd thesis, INSA de Lyon, 2012. http://tel.archives-ouvertes.fr/tel-00760064.

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The use of SMPS (Switched mode power supply) in embedded systems is continuously increasing. The technological requirements of these systems include simultaneously a very good voltage regulation and a strong compactness of components. SEPIC ( Single-Ended Primary Inductor Converter) is a DC/DC switching converter which possesses several advantages with regard to the other classical converters. Due to the difficulty in control of its 4th-order and non linear property, it is still not well-exploited. The objective of this work is the development of successful strategies of control for a SEPIC co

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Zhang, Man. "Modeling of Multiphysics Electromagnetic & Mechanical Coupling and Vibration Controls Applied to Switched Reluctance Machine." Thesis, Université Paris-Saclay (ComUE), 2018. http://www.theses.fr/2018SACLS287/document.

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En raison de ses avantages inhérents, tels que son faible coût, sa fiabilité élevée, sa capacité de fonctionnement à grande vitesse et en environnements difficiles, la machine à réluctance variable (MRV) est une solution attrayante pour l'industrie automobile. Cependant, la traction automobile est une application pour laquelle le comportement acoustique du groupe motopropulseur doit être particulièrement considéré, dans l'optique de ne pas dégrader le confort des passagers. Afin de rendre la MRV compétitive pour cette application automobile, le travail présenté se concentre sur plusieurs métho

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Nunes, Rafael Oliveira. "CONVERSOR ANALÓGICO-DIGITAL INTEGRADOR A CAPACITOR CHAVEADO COM FAIXA DE ENTRADA PROGRAMÁVEL." Universidade Federal do Maranhão, 2010. http://tedebc.ufma.br:8080/jspui/handle/tede/456.

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Made available in DSpace on 2016-08-17T14:53:14Z (GMT). No. of bitstreams: 1 Rafael Oliveira Nunes.pdf: 2514852 bytes, checksum: 72d45d30f5d3d54f97f6401ca5005607 (MD5) Previous issue date: 2010-12-23<br>Coordenação de Aperfeiçoamento de Pessoal de Nível Superior<br>Programmable integrated circuits for specified applications enable its adjustment after fabrication, to fit more than one application within a certain set of applications. These circuits are flexible, but could lose in performance when compared to other circuit constructed to serve only a specific application. A programmable sys

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Belfort, Diomadson Rodrigues. "Circuito de Condicionamento de Sinais Analógicos Programável para Sistemas Integrados." Universidade Federal do Maranhão, 2007. http://tedebc.ufma.br:8080/jspui/handle/tede/429.

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Made available in DSpace on 2016-08-17T14:53:07Z (GMT). No. of bitstreams: 1 Diomadson Belfort.pdf: 1540332 bytes, checksum: 3100ff3681a43294daea6ee8313b879e (MD5) Previous issue date: 2007-09-05<br>In digital measurement systems, signal conditioning circuits have the main functionality of adjusting analog signals for digital conversion. For maximizing the application of a measurement circuit or system, yet considering its integration in a single chip, these circuits must be programmable, in order to serve to different kinds of sensors with diverse output signal characteristics. The main

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Rain, Xavier. "Contributions à la commande et à la conception des machines à réluctance variable à double saillance." Thesis, Paris 11, 2013. http://www.theses.fr/2013PA112170.

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Dans le domaine du véhicule électrique, la chaîne de traction allant de la batterie de stockage aux roues en passant par le moteur constitue le cœur du système. Elle bénéficie régulièrement d’innovations technologiques rendant ce véhicule de plus en plus attractif. Actuellement, les motorisations proposées par les constructeurs sont classiques, de type synchrone à rotor bobiné, à aimant permanent ou asynchrone. De conception éprouvée et dotées de lois de commande complexes et parfaitement maîtrisées, elles offrent de bonnes performances.Cependant, les industriels explorent de nouvelles motoris

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Chang, Chih-Wei, and 張智偉. "A Study On The Internet-based Programmable Optomechanical Optical Switch." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/35122248675559419279.

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碩士<br>國立臺灣科技大學<br>高分子工程系<br>91<br>In this study, a cost effective and low insertion loss optomechanical optical switch is developed by integrating a step motor actuated active passive switching mechanism and use a high precision passive alignment mechanism that could aligns collimators . Currently, the most commercially available optomechanical optical switches couple input and output optical signals by means of aligning optical fiber collimators with a step motor . In order to achieve the acceptable positioning accuracy and acceptance angle, more complicated auxiliary mechanism would be neede

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Liang, Ming-Jer, and 梁明哲. "Optimization of Farmpacker by Programmable Controller and Micro Switch Combination." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/29274353674537746162.

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碩士<br>國立屏東技術學院<br>機械工程技術研究所<br>84<br>This study proposes a simple apparatus of induction and pack and of farmpacker to be engaged in automatically packed eggs . This apparatus is used to displace complex , expensive , farmpacker imported . The major components of this inducting and packing apparatus are micro switch and programmable controller . Micro switch is engaged in induction . Programmable controller control the motion of egg-packing . In the first mode of experiment , we control

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"Logic perturbation based circuit partitioning and optimum FPGA switch-box designs." 2001. http://library.cuhk.edu.hk/record=b5890817.

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Cheung Chak Chung.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2001.<br>Includes bibliographical references (leaves 101-114).<br>Abstracts in English and Chinese.<br>Abstract --- p.i<br>Acknowledgments --- p.iii<br>Vita --- p.v<br>Table of Contents --- p.vi<br>List of Figures --- p.x<br>List of Tables --- p.xiv<br>Chapter 1 --- Introduction --- p.1<br>Chapter 1.1 --- Motivation --- p.1<br>Chapter 1.2 --- Aims and Contribution --- p.4<br>Chapter 1.3 --- Thesis Overview --- p.5<br>Chapter 2 --- VLSI Design Cycle --- p.6<br>Chapter 2.1 --- Logic Synthesis --- p.7<br>Chapter

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Hsieh, Chang-Hsien, and 謝章顯. "Automatic Transfer Switch Using Programmable Logic Controller with Dual Backup Source." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/r62t6n.

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碩士<br>國立臺北科技大學<br>電機工程系所<br>93<br>Think about the stability and reliability of the electric power supply, the very important place such as hospital or a pumping station, ATS used for main power source and backup generator interchangeable selection. General, ATS system provided one generator for backup power source controlled by a printed circuit board, when main power is failure, ATS switch to the position of generator and starting the generator on the same time and the electric power can be supply to load continuously. The research use two generators for backup source that should be exchangea

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"Connection-switch box design and optimal MST-based graph algorithm on FPGA segmentation design." 2004. http://library.cuhk.edu.hk/record=b5891958.

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Zhou Lin.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2004.<br>Includes bibliographical references (leaves 50-53).<br>Abstracts in English and Chinese.<br>Chapter 1 --- Introduction --- p.1<br>Chapter 1.1 --- Motivation --- p.1<br>Chapter 1.2 --- Aims and Contribution --- p.3<br>Chapter 1.3 --- Thesis Overview --- p.4<br>Chapter 2 --- Field-Programmable Gate Array and Routing Algorithm in VPR --- p.6<br>Chapter 2.1 --- Commercially Available FPGAs --- p.6<br>Chapter 2.2 --- FPGA Logic Block Architecture --- p.7<br>Chapter 2.2.1 --- Logic Block Functionality vs. FPGA Area-Eff

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32

Hung, Yi-Huang, and 洪郼艎. "Congestion-aware Programmable Logic Device Routing Framework for Area-efficient Switch Architectures." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/55894536594495131145.

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碩士<br>元智大學<br>資訊工程學系<br>98<br>Dangling-wires in area-efficient switches incur excessive routing congestiton as well as wire capacitance. In this thesis, we propose a routing framework to reduce the number of dangling-wires in crossbar switch block. Our routing framework consists of pattern routing, anchor pair insertion, bounding box expansion, and advanced bounding box expansion. The experimental results demonstrate that our proposed router reduces dangling-wires and channel width by 19% and 38%, respectively, as compared to VPR-C. Besides, the wire length is reduced by 11%. By using our new

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"Programmable Metallization Cell Devices for Flexible Electronics." Doctoral diss., 2011. http://hdl.handle.net/2286/R.I.9513.

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abstract: Programmable metallization cell (PMC) technology is based on an electrochemical phenomenon in which a metallic electrodeposit can be grown or dissolved between two electrodes depending on the voltage applied between them. Devices based on this phenomenon exhibit a unique, self-healing property, as a broken metallic structure can be healed by applying an appropriate voltage between the two broken ends. This work explores methods of fabricating interconnects and switches based on PMC technology on flexible substrates. The objective was the evaluation of the feasibility of using this te

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Tarulli, Massimo. "New Generation of Programmable Neuroprostheses - Switched Mode Power Supply Functional Electrical Stimulator." Thesis, 2009. http://hdl.handle.net/1807/30133.

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Functional electrical stimulation (FES) devices have direct applications in the realm of rehabilitation engineering, physiotherapy, occupational therapy and medicine for research, diagnostic and therapeutic purposes. This thesis presents a novel electrical stimulator for use in a FES system. The stimulator produces regulated current pulses using two switched mode power supplies (SMPS) in series. The first power stage - a flyback converter - steps up the supply voltage using primary side digital control. The second power stage is a buck converter with output current hysteretic control. An

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"Fractal Properties and Applications of Dendritic Filaments in Programmable Metallization Cells." Doctoral diss., 2015. http://hdl.handle.net/2286/R.I.36438.

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abstract: Programmable metallization cell (PMC) technology employs the mechanisms of metal ion transport in solid electrolytes (SE) and electrochemical redox reactions in order to form metallic electrodeposits. When a positive bias is applied to an anode opposite to a cathode, atoms at the anode are oxidized to ions and dissolve into the SE. Under the influence of the electric field, the ions move to the cathode and become reduced to form the electrodeposits. These electrodeposits are filamentary in nature and persistent, and since they are metallic can alter the physical characteristics of th

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Van, der Merwe Jacobus Stefanus. "The design of an electro-optic control interface for photonic packet switching applications with contention resolution capabilities." Diss., 2007. http://hdl.handle.net/2263/29241.

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The objective of the research is to design an electro-optic control for the Active Vertical Coupler-based Optical Cross-point Switch (OXS). The electronic control should be implemented on Printed Circuit Board (PCB) and therefore the design will include the PCB design as well. The aim of the electronic control board is to process the headers of the packets prior to entering the OXS to be switched and from the information in the headers, determine the state that the OXS should be configured in. It should then configure the optical cross-point accordingly. The electronic control board should sho

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Chang, Wen-Shu, and 張文旭. "Programmable switched-current filter." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/18148479120679273563.

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碩士<br>南台科技大學<br>電子工程系<br>90<br>This thesis presents a programmable switched-current filter design. In order to improve the filter performance and reduce its supply voltage as well as power consumption, three circuit techniques including S2I, ground gate amplifier(GGA) and class-AB, are adopted to implement the switched-current integrator which is the basic block of the filter. In addition, MOSFET only current dividers(MOCD) via R-2R structure are employed to develop a programmable 5th order Chebyshev low pass filter. The filter has been designed and implemented using 0.35μm 1P4M standard CMOS

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ZHOU, GI-BAI, and 周啟白. "Programmable switched-capacitor sinusoidal generator." Thesis, 1987. http://ndltd.ncl.edu.tw/handle/76721719637701306914.

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Marques, Rui Miguel Carvalho. "Named data networking with programmable switches." Master's thesis, 2017. http://hdl.handle.net/10451/31861.

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Tese de mestrado em Engenharia Informática (Arquitectura, Sistemas e Redes de Computadores) Universidade de Lisboa, Faculdade de Ciências, 2017<br>As redes IP, que são universais atualmente, apresentam um conjunto de problemas que encontra a sua génese nos seus propósitos originais. Na génese do IP, o objetivo era a partilha de recursos. Hoje em dia, as redes de computadores já não se baseiam num computador mainframe a disponibilizar recursos de hardware. São usadas como meio de disseminação alargada de uma panóplia de média, como ficheiros de hipertexto, imagens e vídeos. Grande parte das dif

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Pinto, Diogo Figueiredo. "Network coding data planes with programmable switches." Master's thesis, 2017. http://hdl.handle.net/10451/30687.

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Tese de mestrado, Engenharia Informática (Arquitectura, Sistemas e Redes de Computadores), Universidade de Lisboa, Faculdade de Ciências, 2017<br>Atualmente, as redes de computadores seguem um paradigma tradicional de store-andforward, ou seja, os dispositivos de rede fazem armazenamento, encaminhamento e/ou replicação de pacotes recebidos, sem os modificar. No virar do milénio, surgiu um artigo seminal [24], no qual foi demonstrado teoricamente que a combinação da informação proveniente de diversos pacotes, permite aumentar a capacidade de uma rede relativamente à capacidade máxima, alcançada

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Fu, kuo-Yao, and 傅國堯. "Design of the Programmable Scheduling Engine for ATM Switches." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/57804686185413984300.

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碩士<br>國立東華大學<br>資訊工程學系<br>89<br>Today, communication required by various applications over the network is not only data traffic. New applications such as voice, video, multimedia, and interactive video conferencing need the Internet to provide integrated services. In many areas, we would like to provide different services for applications. Hence, quality of service (QoS) for diverse traffic characteristics is essential for modern network communications. In this thesis, we design a hardware scheduling engine which can provide QoS. A typical design for the general scheduling engine of

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"Lateral Programmable Metallization Cell Devices And Applications." Doctoral diss., 2011. http://hdl.handle.net/2286/R.I.9204.

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abstract: Programmable Metallization Cell (PMC) is a technology platform which utilizes mass transport in solid or liquid electrolyte coupled with electrochemical (redox) reactions to form or remove nanoscale metallic electrodeposits on or in the electrolyte. The ability to redistribute metal mass and form metallic nanostructure in or on a structure in situ, via the application of a bias on laterally placed electrodes, creates a large number of promising applications. A novel PMC-based lateral microwave switch was fabricated and characterized for use in microwave systems. It has demonstrated l

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Amanor-Boadu, Judy M. "A User Programmable Battery Charging System." Thesis, 2013. http://hdl.handle.net/1969.1/149560.

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Rechargeable batteries are found in almost every battery powered application. Be it portable, stationary or motive applications, these batteries go hand in hand with battery charging systems. With energy harvesting being targeted in this day and age, high energy density and longer lasting batteries with efficient charging systems are being developed by companies and original equipment manufacturers. Whatever the application may be, rechargeable batteries, which deliver power to a load or system, have to be replenished or recharged once their energy is depleted. Battery charging systems must pe

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Lin, Checung, and 林哲玄. "Implementation of Switched Reluctance Motor Drive Based on Fuzzy Vector Control and Programmable System on Chip." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/36170597923987565359.

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碩士<br>明志科技大學<br>電機工程研究所<br>100<br>A switched reluctance motor (SRM) is a doubly salient machine; which has neither rotor windings nor permanent magnets. In addition, its main advantages include structural simplicity, low overhead, and high efficiency. However, the motor’s magnetic characteristic is non-linear, resulting in significant torque ripples and acoustic noise, so that limit the scope of its industrial applications. This thesis proposes a vector control method that can improve SRM’s torque ripples and acoustic noise. Additionally, to improve system performance, this thesis also applies

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Huang, ChihYang, and 黃智揚. "The Fully CMOS Compatible Multiple-Time-Programmable Memory Circuits and Switched-Capacitor DC-DC Converter Design." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/28103987955499888564.

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碩士<br>國立中興大學<br>電機工程學系所<br>100<br>In recent years, embedded non-volatile memories are used in various systems. However, due to compatibility of processes, memory chips and the other functional chips are fabricated separately. If the memories can be integrated in the same chip with analog and digital circuits, the single chip is usually referred as SOC (system-on-a-chip). In the mean time, the cost and fabrication time can be reduced. The thesis presents the design of the peripheral circuits for the CMOS-based non-volatile memory cells. The circuits perform program, erase, read and verify for t

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Wu, Chia-You, and 吳嘉祐. "Chip Design for the Peripheral Circuits of Embedded Differential Multi-Time-Programmable Memories Including Switched-Capacitor Step-Down Converters." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/pya46f.

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碩士<br>國立中興大學<br>電機工程學系所<br>101<br>In the development of systems-on-chip technologies, the CMOS embedded non-volatile memories usually need extra process steps. However, those without extra processes are also possible. The former is suitable for median memory capacities with the higher cost. The latter is appropriate for small memory capacities. If the systems do not require large memory capacities, the technique without the extra processes can be applied for cost and fabrication time reduction. In this thesis, the peripheral circuits are designed for differential Multi-Time-Programmable (MTP)

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