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1
LI, PING, ZHONG LI, WOLFGANG A. HALANG, and GUANRONG CHEN. "ANALYSIS OF A MULTIPLE-OUTPUT PSEUDO-RANDOM-BIT GENERATOR BASED ON A SPATIOTEMPORAL CHAOTIC SYSTEM." International Journal of Bifurcation and Chaos 16, no. 10 (2006): 2949–63. http://dx.doi.org/10.1142/s0218127406016574.
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A novel multiple-output pseudo-random-bit generator (PRBG) based on a coupled map lattice (CML) consisting of skew tent maps, which generates spatiotemporal chaos, is presented. In order to guarantee PRBG highly effective, avoiding synchronization among the sites in the CML is discussed. The cryptographic properties, such as probability distribution, auto-correlation and cross-correlation, of the PRBG with various parameters, are investigated numerically. The randomness of the PRBG is verified via FIPS 140-2. In addition, as compared with the PRBG based on the CML consisting of the logistic maps, which are often used in chaos-based PRBGs by many other researchers, the ranges of the parameters within which this multiple-output PRBG have good cryptographic properties are much bigger in terms of their cryptographic properties. It lays a foundation for designing a faster and more secure encryption.
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Chiang, Yi Te, He Sheng Wang, and Yung Nien Wang. "A Chaotic-Based Pseudo-Random Bit Generator for Navigation Applications." Applied Mechanics and Materials 311 (February 2013): 99–104. http://dx.doi.org/10.4028/www.scientific.net/amm.311.99.
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In this paper, we propose a novel method to generate pseudo-random-noise (PRN) bits for navigation applications. In the present method, the code sequence generator is constructed based on two chaotic logistic maps running parallel and starting from independent initial conditions. The logistic map is a simple mathematical model that shows bewildering complex behavior. By appro-priately setting the initial conditions, the PRN sequence is then generated by comparing the outputs of both logistic maps. Several simulations are set up to verify the correlation properties of the pseudo-random bit generator (PRBG). The result shows that the code sequences generated by the proposed PRBG have great auto- and cross-correlation properties, which are very similar to the PRN sequences used by GPS navigation system. The RPBG sequences are therefore suitable for signal ranging that is used comprehensively in the navigation system. On the other hand, the chaotic nature of the proposed PRBG codes can provide more secure communication than the traditional PRN sequences. The proposed PRN sequences are well suitable to be incorporated with the so-called chaotic shift keying (CSK) modulation.
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García-Martínez, M., and E. Campos-Cantón. "Pseudo-random bit generator based on lag time series." International Journal of Modern Physics C 25, no. 04 (2014): 1350105. http://dx.doi.org/10.1142/s0129183113501052.
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In this paper, we present a pseudo-random bit generator (PRBG) based on two lag time series of the logistic map using positive and negative values in the bifurcation parameter. In order to hidden the map used to build the pseudo-random series we have used a delay in the generation of time series. These new series when they are mapped xn against xn+1 present a cloud of points unrelated to the logistic map. Finally, the pseudo-random sequences have been tested with the suite of NIST giving satisfactory results for use in stream ciphers.
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Fadhil, Sahib Hasan, and Amer Saffo Maryam. "FPGA Hardware Co-Simulation of Image Encryption using Hybrid Chaotic Maps Based Stream Cipher." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 4 (2020): 215–25. https://doi.org/10.35940/ijeat.D6713.049420.
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In This paper, new model of image encryption is designed. This model using stream cipher based on finite precision chaotic maps. The model designed in efficient way by using Xilinx System Generator (XSG). Pseudo Random Bit Generator (PRBG) depends on chaotic maps is proposed to design Fixed Point Hybrid Chaotic Map-PRBG (FPHYBCM-PRBG). National Institute of Standards and Technology (NIST) randomness measures tested the randomness of the proposed FPHYBCM-PRBG system. The security analysis, such as histogram, correlation coefficient, information entropy, differential attack (NPCR and UACI) are used to analyze the proposed system. Also, FPGA Hardware Co-Simulation over Xilinx SP605 XC6SLX45T provided to test the reality of image encryption system. The results show that FPHYBCM-PRBG is suitable for image encryption based on stream cipher and outperform some encryption algorithms in sufficient way to enhance the security and robust against brute force attack with low maximum frequency and throughput.
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Qiu, Jin, and Ping Wang. "Color Image Encryption Scheme Based on Chaotic Map." Applied Mechanics and Materials 182-183 (June 2012): 1800–1804. http://dx.doi.org/10.4028/www.scientific.net/amm.182-183.1800.
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In this paper, a chaos-based image encryption scheme with stream cipher structure is proposed. The key component of the encryption system is a pseudo-random bit generator (PRBG) based on a chaotic map and a linear feedback shift register. The proposed PRBG is not only passes the statistical tests, but also improve the security. The overall design of the image encryption scheme is to be explained while detail cryptanalysis is given.
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WANG, XINGYUAN, WEI LIU, NINI GU, and HUAGUANG ZHANG. "DIGITAL STREAM CIPHER BASED ON SCS-PRBG." International Journal of Modern Physics B 23, no. 25 (2009): 5085–92. http://dx.doi.org/10.1142/s0217979209053539.
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Limitations caused by degeneration of dynamics characteristics may exist in the traditional single chaotic system. The authors propose a method i.e., switch controller chaos and pseudo random bit generator (it is called SCS-PRBG for short), which is based on multiple chaotic systems and switch control. By the theoretic analysis of random key stream and performance of SCS-PRBG, we can see that its digital stream cipher has better randomicity and security. And if using hardware parallel computation, the speed of encryption can be improved sharply. The results of the experiments also present better security of this arithmetic.
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H, Soumya Babu, and Gopakumar K. "ELECTRONIC CIRCUIT REALISATION OF A CHAOTIC PSEUDO RANDOM BIT GENERATOR." ICTACT Journal on Microelectronics 7, no. 2 (2021): 1121–26. https://doi.org/10.21917/ijme.2021.0195.
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Most of the properties of chaotic systems like sensitivity to initial conditions, deterministic dynamics, mixing property, structural complexity can be considered as analogous to diffusion and confusion with small changes in plain text or the secret key, deterministic pseudo randomness and complex properties of cryptographic systems. The interesting relationship between cryptography and chaos leads to new, highly secure cryptographic techniques. The development of chaotic stream ciphers in cryptography requires the need for the generation of pseudo random bits and hence the need for pseudo random bit generators (PRBG). In this paper, circuit realisation of a pseudo random bit generator is presented, which is based on two chaotic maps, namely the logistic maps, running in parallel and starting from two random independent initial conditions. The circuit is being implemented and simulated for different initial conditions using Multisim software. The results obtained from simulation are further tested for randomness using the NIST suite tests and the detailed results of the statistical testing are also presented in this paper.
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Ahmed, Kamil Hasan Al-Ali, and Mohammed Daif Alkhasraji Jafaar. "Colour image encryption based on hybrid bit-level scrambling, ciphering, and public key cryptography." Bulletin of Electrical Engineering and Informatics 12, no. 3 (2023): 1607~1619. https://doi.org/10.11591/eei.v12i3.4728.
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This paper proposes an image encryption technique using three stages algorithms based on hyper-chaotic maps. In the first scenario, bit-level scrambling (BLS) using a 2D coupled chaotic map (2D-CCM) is used to encrypt the bits of the basic colour image. In the second strategy, the scrambled bit level is XORed with pseudo random bit generator (PRBG). The PRBG is designed using a combination of chaotic maps, including, logistic map (LM), sine map (SM), 5D chaotic map (5D-CM), enhanced quadratic map (EQM), and 2D henon SM (2D-HSM). The pubic key based on the Chebyshev polynomial chaotic map is used as the final phase of the encryption algorithms. The performance analysis of the proposed image encryption technique is validated through various criteria such as fundamental space analysis, correlation coefficient, entropy, the number of pixels changes rate (NPCR), and unified average-changing intensity (UACI). Also, the obtained results are compared with other recent studies. The simulation results demonstrated that the proposed technique has robust security and it provides the image with high protection against various attacks.
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Abdulla, M. Abuayyash, and Ajlouni Naim. "Using Permutations to Enhance the Gain of RUQB Technique." International Journal of Information Technology and Web Engineering, April-Jun (April 1, 2018): 30–45. https://doi.org/10.5281/zenodo.1210768.
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<em>Quantum key distribution (QKD) techniques usually suffer from a gain problem when comparing the final key to the generated pulses of quantum states. This research permutes the sets that RUQB (Abu-ayyash & Ajlouni, 2008) uses in order to increase the gain. The effect of both randomness and permutations are studied; While RUQB technique improves the gain of BB84 QKD by 5.5% it was also shown that the higher the randomness of the initial key the higher the gain that can be achieved, this work concluded that the use of around 7 permutations results in 30% gain recovery in an ideal situations. </em>
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Al-Ali, Ahmed Kamil Hasan, and Jafaar Mohammed Daif Alkhasraji. "Colour image encryption based on hybrid bit-level scrambling, ciphering, and public key cryptography." Bulletin of Electrical Engineering and Informatics 12, no. 3 (2023): 1607–19. http://dx.doi.org/10.11591/eei.v12i3.4728.
Full textAbstract:
This paper proposes an image encryption technique using three stages algorithms based on hyper-chaotic maps. In the first scenario, bit-level scrambling (BLS) using a 2D coupled chaotic map (2D-CCM) is used to encrypt the bits of the basic colour image. In the second strategy, the scrambled bit level is XORed with pseudo random bit generator (PRBG). The PRBG is designed using a combination of chaotic maps, including, logistic map (LM), sine map (SM), 5D chaotic map (5D-CM), enhanced quadratic map (EQM), and 2D henon SM (2D-HSM). The pubic key based on the Chebyshev polynomial chaotic map is used as the final phase of the encryption algorithms. The performance analysis of the proposed image encryption technique is validated through various criteria such as fundamental space analysis, correlation coefficient, entropy, the number of pixels changes rate (NPCR), and unified average-changing intensity (UACI). Also, the obtained results are compared with other recent studies. The simulation results demonstrated that the proposed technique has robust security and it provides the image with high protection against various attacks.
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Akif, Omar Z., Sura Ali, Rasha Subhi Ali, and Alaa Kadhim Farhan. "A new pseudorandom bits generator based on a 2D-chaotic system and diffusion property." Bulletin of Electrical Engineering and Informatics 10, no. 3 (2021): 1580–88. http://dx.doi.org/10.11591/eei.v10i3.2610.
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A remarkable correlation between chaotic systems and cryptography has been established with sensitivity to initial states, unpredictability, and complex behaviors. In one development, stages of a chaotic stream cipher are applied to a discrete chaotic dynamic system for the generation of pseudorandom bits. Some of these generators are based on 1D chaotic map and others on 2D ones. In the current study, a pseudorandom bit generator (PRBG) based on a new 2D chaotic logistic map is proposed that runs side-by-side and commences from random independent initial states. The structure of the proposed model consists of the three components of a mouse input device, the proposed 2D chaotic system, and an initial permutation (IP) table. Statistical tests of the generated sequence of bits are investigated by applying five evaluations as well as the ACF and NIST. The results of five standard tests of randomness have been illustrated and overcome a value of 0.160 in frequency test. While the run test presents the pass value t0=4.769 and t1=2.929. Likewise, poker test and serial test the outcomes was passed with 3.520 for poker test, and 4.720 for serial test. Finally, autocorrelation test passed in all shift numbers from 1 to 10.
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Omar, Z. Akif, Mazin Ali Sura, Subhi Ali Rasha, and Kadhim Farhan Alaa. "A new pseudorandom bits generator based on a 2D-chaotic system and diffusion property." Bulletin of Electrical Engineering and Informatics 10, no. 3 (2021): pp. 1580~1588. https://doi.org/10.11591/eei.v10i3.2610.
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A remarkable correlation between chaotic systems and cryptography has been established with sensitivity to initial states, unpredictability, and complex behaviors. In one development, stages of a chaotic stream cipher are applied to a discrete chaotic dynamic system for the generation of pseudorandom bits. Some of these generators are based on 1D chaotic map and others on 2D ones. In the current study, a pseudorandom bit generator (PRBG) based on a new 2D chaotic logistic map is proposed that runs side-by-side and commences from random independent initial states. The structure of the proposed model consists of the three components of a mouse input device, the proposed 2D chaotic system, and an initial permutation (IP) table. Statistical tests of the generated sequence of bits are investigated by applying five evaluations as well as the ACF and NIST. The results of five standard tests of randomness have been illustrated and overcome a value of 0.160 in frequency test. While the run test presents the pass value t0=4.769 and t1=2.929. Likewise, poker test and serial test the outcomes was passed with 3.520 for poker test, and 4.720 for serial test. Finally, autocorrelation test passed in all shift numbers from 1 to 10.
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TANG, K. W., WALLACE K. S. TANG, and K. F. MAN. "A CHAOS-BASED PSEUDO-RANDOM NUMBER GENERATOR AND ITS APPLICATION IN VOICE COMMUNICATIONS." International Journal of Bifurcation and Chaos 17, no. 03 (2007): 923–33. http://dx.doi.org/10.1142/s021812740701763x.
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In this paper, a fast chaos-based pseudo-random number generator (PRNG) is proposed for secured communications. In order to achieve fast throughput and facilitate hardware realization, 32-bit fixed point representation and arithmetic are used. Even under such configuration with quantization errors which will make the normal chaos-based PRNG impractical, our scheme can pass all the statistical tests in the up-to-date National Institute of Standards and Technology (NIST) test suite with the output bit rate up to 134 Mbps in a 2.6 GHz Pentium-4 machine. With such a fast PRNG, a stream cipher is hence designed for the application of online secure voice communication system with User Datagram Protocol (UDP).
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N, Bharatesh, and Rohith S. "FPGA Implementation of Park-Miller Algorithm to Generate Sequence of 32-Bit Pseudo Random Key for Encryption and Decryption of Plain Text." International Journal of Reconfigurable and Embedded Systems (IJRES) 2, no. 3 (2013): 99. http://dx.doi.org/10.11591/ijres.v2.i3.pp99-105.
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There are many problems arises in randomized algorithms whose solutions are fundamentally based on assumptions that pure random numbers exist, so pseudo-random number generators can imitate randomness sufficiently well for most applications. The proposed scheme is a FPGA implementation of Park-Miller Algorithm for generating sequence of Pseudo-Random keys. The properties like High speed, low power and flexibility of designed PRNG(Pseudo Random Number Generator) makes any digital circuit faster and smaller. The algorithm uses a PRNG Module, it contains 32-bit Booth Multiplier, 32-bit Floating point divider and a FSM module. After generating a sequence of 32-bit Pseudo-Random numbers we have used these numbers as a key to Encrypt 128-bit plain text to become a cipher text and by using the same key to decrypt the encrypted data to get original Plain text. The Programming is done in Verilog-HDL, successfully synthesized and implemented in XILINX Spartan 3E FPGA kit.
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Pasqualini, Luca, and Maurizio Parton. "Pseudo Random Number Generation through Reinforcement Learning and Recurrent Neural Networks." Algorithms 13, no. 11 (2020): 307. http://dx.doi.org/10.3390/a13110307.
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A Pseudo-Random Number Generator (PRNG) is any algorithm generating a sequence of numbers approximating properties of random numbers. These numbers are widely employed in mid-level cryptography and in software applications. Test suites are used to evaluate the quality of PRNGs by checking statistical properties of the generated sequences. These sequences are commonly represented bit by bit. This paper proposes a Reinforcement Learning (RL) approach to the task of generating PRNGs from scratch by learning a policy to solve a partially observable Markov Decision Process (MDP), where the full state is the period of the generated sequence, and the observation at each time-step is the last sequence of bits appended to such states. We use Long-Short Term Memory (LSTM) architecture to model the temporal relationship between observations at different time-steps by tasking the LSTM memory with the extraction of significant features of the hidden portion of the MDP’s states. We show that modeling a PRNG with a partially observable MDP and an LSTM architecture largely improves the results of the fully observable feedforward RL approach introduced in previous work.
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Yu, Fei, Zinan Zhang, Hui Shen, Yuanyuan Huang, Shuo Cai, and Sichun Du. "FPGA implementation and image encryption application of a new PRNG based on a memristive Hopfield neural network with a special activation gradient." Chinese Physics B 31, no. 2 (2022): 020505. http://dx.doi.org/10.1088/1674-1056/ac3cb2.
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A memristive Hopfield neural network (MHNN) with a special activation gradient is proposed by adding a suitable memristor to the Hopfield neural network (HNN) with a special activation gradient. The MHNN is simulated and dynamically analyzed, and implemented on FPGA. Then, a new pseudo-random number generator (PRNG) based on MHNN is proposed. The post-processing unit of the PRNG is composed of nonlinear post-processor and XOR calculator, which effectively ensures the randomness of PRNG. The experiments in this paper comply with the IEEE 754-1985 high precision 32-bit floating point standard and are done on the Vivado design tool using a Xilinx XC7Z020CLG400-2 FPGA chip and the Verilog-HDL hardware programming language. The random sequence generated by the PRNG proposed in this paper has passed the NIST SP800-22 test suite and security analysis, proving its randomness and high performance. Finally, an image encryption system based on PRNG is proposed and implemented on FPGA, which proves the value of the image encryption system in the field of data encryption connected to the Internet of Things (IoT).
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Aruna, Mrs S., Ch Soumya Pranathi, A. Siva Madhuri, and K. Neha. "Implementation of Programmable n-bit Pseudo Random Sequence Generator using 45 nm Technology." International Journal for Research in Applied Science and Engineering Technology 12, no. 6 (2024): 958–66. http://dx.doi.org/10.22214/ijraset.2024.63240.
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Abstract: In recent times with the advent of computers, programmers recognized the necessity for a means of introducing randomness into a computer program. Pseudo-random numbers generates necessary values for processes that require randomness, such as creating test signals or for synchronizing transmitting and receiving devices in a spread spectrum transmission. It is not possible to generate truly random numbers from deterministic thing like computers so PRSG is a technique developed to generate random numbers using a computer. Our proposed system is used to implement multiple polynomials of degree 2 to 16 in Incisive and Genus Cadence Tool. This system can be implemented in statistical analysis, and modern-day computer simulations, digital cryptography and generation of OTP.
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Fahrizal, Muhammad, and Achmad Solichin. "Pengamanan M-Commerce Menggunakan One Time Password Metode Pseudo Random Number Generator (PRNG)." Rabit : Jurnal Teknologi dan Sistem Informasi Univrab 5, no. 2 (2020): 108–16. http://dx.doi.org/10.36341/rabit.v5i2.1363.
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Mobile commerce atau m-commerce merupakan sistem perdagangan elektronik (e-commerce) yang menggunakan peralatan bergerak seperti telepon genggam, telepon pintar, PDA, dan notebook. Dengan pertumbuhan pengguna telepon pintar (smartphone) di seluruh dunia, banyak pemilik bisnis perdagangan elektronik yang juga menyediakan aplikasi m-commerce untuk mempermudah para pelanggannya dalam bertransaksi. Selain memberikan kenyamanan bagi pengguna, penyedia aplikasi m-commerce harus dapat memastikan bahwa pelanggan dapat bertransaksi dengan aman. Resiko keamanan merupakan salah satu kendala besar dalam perkembangan sistem perdagangan elektronik. Oleh karena itu, pada penelitian ini diterapkan metode pengamanan aplikasi m-commerce menggunakan one time password (OTP) yang dibangkitkan dengan metode Pseudo Random Number Generator (PRNG). Penelitian ini juga melakukan modifikasi terhadap algoritme PRNG dengan melakukan tiga kali proses bit shifting dan menambahkan algoritme enkripsi. Hasil pengujian menunjukkan bahwa sistem dapat membangkitkan OTP yang selalu unik untuk setiap transaksi. Hasil penelitian ini bermanfaat bagi pengembang aplikasi m-commerce untuk mengamankan aplikasinya.
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Kurniasih, Firda, Rini Marwati, and Ririn Sispiyati. "Penggabungan Affine Cipher dan Least Significant Bit-2 untuk Penyisipan Pesan Rahasia pada Gambar." Jurnal EurekaMatika 11, no. 2 (2023): 79–88. http://dx.doi.org/10.17509/jem.v11i2.62115.
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As technology develops, improving message security is very important. One approach that can be taken to improve message security is to combine cryptography and steganography. In this study, the authors combined Affine Cipher cryptographic and Least Significant Bit-2 (LSB-2) steganography. In this merge method, the Affine Cipher cryptography is applied first, then, the encrypted message is inserted into an image using LSB-2. Specifically, LSB-2 is a modification of the Least Significant Bit (LSB) method which works by exchanging the sixth bits of each pixel color element in the image with the bits of the secret message. The LSB-2 used is a random LSB-2. In this case, the random numbers are generated by the Pseudo Random Number Generator (PRNG). The results of this research are a computer application with the Python language version 3.11 which can disguise messages and insert them in an image. Based on the implementation, the combination Affine Cipher and LSB-2 can complicate cryptanalysis because it has to hack two algorithms and the message is hidden randomly in an image.Keywords: Affine Cipher, Cryptography, LSB-2, Message Security, Steganography. AbstrakSeiring berkembangnya teknologi, peningkatan keamanan pesan menjadi sangat penting. Salah satu pendekatan yang dapat dilakukan untuk meningkatkan keamanan pesan adalah dengan menggabungkan kriptografi dan steganografi. Pada penelitian ini, penulis melakukan penggabungan antara teknik kriptografi Affine Cipher dan steganografi Least Significant Bit-2 (LSB-2). Dalam metode penggabungan ini, keamanan pesan dilakukan dengan menerapkan kriptografi Affine Cipher terlebih dahulu. Kemudian, pesan yang telah dienkripsi disisipkan ke dalam citra menggunakan LSB-2. Lebih spesifiknya, LSB-2 merupakan modifikasi dari metode Least Significant Bit (LSB) dengan menukarkan bit ke enam dari setiap elemen warna pixel pada gambar dengan bit-bit dari pesan rahasia yang ingin disembunyikan. LSB-2 yang digunakan merupakan LSB-2 secara acak. Bilangan acak yang diperlukan dalam proses ini dihasilkan melalui Pseudo Random Number Generator (PRNG). Hasil penelitian ini berupa aplikasi komputer dengan bahasa pemrograman Python versi 3.11 yang dapat menyamarkan pesan dan menyisipkannya dalam gambar. Berdasarkan implementasi, diperoleh hasil bahwa penggabungan Affine Cipher dan LSB-2 dapat mempersulit kriptanalisis karena harus meretas dua algoritma dan pesan disembunyikan secara acak keberadaannya di dalam gambar.
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Arianty, Rini, and Diana Tri Susetianingtias. "KOMBINASI LOGISTIC MAP DAN PSEUDO-RANDOM NUMBER GENERATOR PADA PEMBANGKITAN KUNCI UNTUK ENKRIPSI CITRA DIGITAL." Jurnal Ilmiah Teknologi dan Rekayasa 25, no. 3 (2020): 187–98. http://dx.doi.org/10.35760/tr.2020.v25i3.3120.
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Informasi berbentuk gambar yang bersifat sensitif atau rahasia, seperti data pribadi, dokumen penting yang dikirimkan melalui internet belum tentu aman dari serangan pihak luar. Kerugian yang cukup besar dapat ditimbulkan apabila data tersebut diakses dan dimanipulasi oleh orang yang tidak bertanggung jawab. Salah satu metode dalam mengamankan suatu informasi adalah kriptografi. Logistic map adalah salah satu algoritma chaos yang sering digunakan dalam kriptografi citra karena algoritma ini mampu menghasilkan deretan bilangan acak yang kompleks dengan persamaan polinomial rekursif yang sederhana. Pada penelitian ini, akan diimplementasikan algoritma chaos logistic map dan pseudo-random number generator (PRNG) dalam pengenkripsian citra. Citra input akan diubah bentuknya kedalam array lalu proses difusi dilakukan secara selektif dengan mensubstitusi 4 bit MSB setiap nilai warna citra dengan kunci logistic map. Hasil difusi tersebut akan dikonfusi dengan cara mensubstitusikan indeks arraynya dengan kunci prng sehingga didapat sebuah array baru yang teracak indeksnya. Array tersebut diubah kembali menjadi sebuah citra sehingga didapat citra terenkripsi yang aman.
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Bhandari, Jugal Kishore, Yogesh Kumar Verma, and S. K. Hima Bindhu. "Enhancing FPGA Testing Efficiency: A PRBS-Based Approach for DSP Slices and Multipliers." International Journal of Electrical and Electronics Research 12, no. 1 (2024): 139–45. http://dx.doi.org/10.37391/ijeer.120120.
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The multiplication operations are pivotal in (Application-Specific Integrated Circuits) ASICs and Digital Signal Processors (DSPs). The integration of Field-Programmable Gate Arrays (FPGAs) into modern embedded systems, efficient Built-in Self-Tests (BISTs), particularly for complex components like DSP slices, is essential. This paper evaluates Pseudo Random Binary Sequence (PRBS) generators and checkers as BIST tools for high-speed data transfers in FPGAs. The design achieves minimal errors and remarkable efficiency with less than 4% logic utilization within available Look-Up Tables (LUTs). The testing of embedded multipliers in modern FPGAs is analyzed, shedding light on their performance. The analysis includes Built-in Self-Test (BIST), PRBS generator, PRBS checker, and Bit Error Rate (BER), providing insights into FPGA-based testing. This analysis assesses PRBS tools for high-speed FPGA data transfers. A hybrid multiplier design, featuring BIST and PRBS capabilities, notably reduces DSP slice utilization from 16% to 5%. This liberated FPGA resource enhances operational capabilities. The runtime PRBS data control at the block level design exemplifies adaptability in FPGA testing. The findings underscore PRBS-based BIST potential in FPGA testing. The hybrid multiplier not only optimizes FPGA resources but also aligns with dynamic digital system requirements. This research aids FPGA designers and engineers in advanced testing strategies for evolving embedded systems.
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Hashmi, Muhammad Asim, and Noshina Tariq. "An Efficient Substitution Box design with a chaotic logistic map and Linear Congruential Generator for secure communication in Smart cities." EAI Endorsed Transactions on Smart Cities 7, no. 1 (2023): e5. http://dx.doi.org/10.4108/eetsc.v7i1.2845.
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The study provides a unique method for creating an efficient substitution box (S-box) for advanced encryption standards using a Chaotic Logistic Map (CLM) and a Linear Congruential Generator (LCG) (AES) for secure communications in a smart city. The Pseudo-Random Number Generator (PRNG), which is further examined, is constructed using an extensive search of reasonable possibilities for the initial seed and set parameters. Using statistical testing, the performance analysis of the new S-box is assessed. Additionally, the resilience of differential, as well as linear cryptanalysis, is shown. It is derived using other features, including nonlinearity, the Bit Independence Criterion (BIC), and the Strict Avalanche Criterion (SAC). The suggested S-box has good potential and is usable for symmetric key cryptography, according to the features of the new S-cryptographic box.
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Amit, Kore, Damania Kartik, Deshmukh Vaidehi, Jadhav Sneha, and Boruah Preeyonuj. "SECURITY ENHANCEMENT USING NEURAL NETWORKS FOR DATA TRANSMISSION." JournalNX - A Multidisciplinary Peer Reviewed Journal QIPCEI2K18 (April 29, 2018): 112–15. https://doi.org/10.5281/zenodo.1411792.
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Cryptography is a process of protecting information and data from unauthorized access. The goal of any cryptographic system is the access of information among the intended user without any leakage of information. As technology advances the methods of traditional cryptography becomes more and more complex. Neural Networks provide an alternate way for crafting a security system whose complexity is far less than that of the current cryptographic systems and has been proven to be productive. Both the communicating neural networks receive an identical input vector, generate an output bit and are based on the output bit. Our approach is based on the application of natural noise sources that we can use to teach our system to approximate with the aim of generating an output non-linear function. This approach provides the potential for generating an unlimited number of unique Pseudo Random Number Generator (PRNG) that can be used on a one to one basis. We can use the PRNG generated to encrypt the input data and create a cipher text that has a high cryptographic strength. https://journalnx.com/journal-article/20150582
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Sastry, Prof Executive Dean P. N. V. M., and Prof Dean Dr S. Vathsal. "Ultra High multi channel clock frequency(THz, PHz, EHz, ZHz,YHz,XHz,WHz) baud rate speed PRBS Transceiver HDL RTL ASIC Design for Ultra High long Distance Wireless Communication Engineering Smart Computing Products/ Applications." IOSR Journal of VLSI and Signal processing 14, no. 4 (2024): 18–26. http://dx.doi.org/10.9790/4200-14041826.
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The Key Objective is HDL RTL Design Architecture of Ultra high multi Clock Frequency Speed Rate ( MHz, GHz, THz, PHz, EHz, ZHz, etc) Bits Per Second Baud Rate ) P.R.B.S(Pseudo Random Binary Sequence) Transceiver Soft A.S.I.C IP Core product for identification of the property of Different Pseudo Random Binary Sequence Patterns (Seed Words) of 2e 7 -1, 2e10 -1, 2e 15 -1, 2e 23 -1, 2e 31 -1 tapped elements as per C.C.I.T.T-I.T.U Standards and IEEE-754 Single and Double Data Rate Data Precision Standards (32 bit & 64 Bit Data Width ) suited for Very Advanced Futuristic Hi-tech Smart High Speed Long Distance Wireless Digital Communication A.S.I.C Products / Applications like Space/Satellite, Aerospace and Large Data Processing and computing like High Speed Internet and Cloud Computing based Hi-Fi Industrial Data Automation Standard Ultra High Speed Wireless Communication A.S.I.C products and Applications-3G,4G,5G etc. The Multi channel PRBS Transceiver consists Transmitter and receiver of different PRBS patterns- 2e7 -1, 2e10 -1, 2e15 -1, 2e23 -1, 2e31 -1 NRZ. The data input transmitted and received serially in the form bit by bit. These different pattern sequences are Designated as per CCITT ITU 0.151/O.152/O.153 & AT&T Standards. The Aim and purpose of invention of Ultra high multichannel Clock frequency PRBS Transceiver is for transmit and receive data serially by using Tx_in and Tx_out, rxin, rxout signals and The Transceiver is processed the low frequency signal input with different high speed carrier wave frequencies in the form of different PRBS pseudo random binary sequence seed word bit/byte patterns -2e7 -1, 2e10 -1, 2e15 -1, 2e23 -1, 2e31 -1 NRZ and also on receiver side processed with the above patterns. Materials and Methods: Transmission and reception of Data serially based on the Deterministic random seed word pattern methods of different PRBS 2e7 -1, 2e10 -1, 2e15 -1, 2e23 -1, 2e31 -1 tapped sequence Elements and All these PRBS are purely synchronized with Ultra high clock frequency(MHz, GHz, THz, PHz, EHz, ZHz, YHz, XHz, WHz). The Soft IP Core Designed by System Verilog HDL/ Verilog HDL. RTL Design Simulation done by Synopsys VCS 2020.1 software and Altera Model-Sim Software and Logic Design Flow & Synthesis done by Xilinx ISE and Altera Quartus EDA Tools. Results: Generation of Simulation Display and waveform for Ultra High Clock frequency(MHz, GHz, THz, PHz, EHz, ZHz, YHz, XHz, WHz) Synchronized Pseudo Random Binary Sequence (PRBS) Register Transfer Level (RTL) Generators, Transceiver for efficient and effective High Quality Data transmission and Reception of Various tapped sequence patterns for Identification of property of different PRBS patterns2e7 -1, 2e10-1, 2e15-1, 2e23 -1, 2 31 -1 NRZ of Ultra high speed Long distance wireless engineering Applications/ products.
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Zhu, Shenli, Xiaoheng Deng, Wendong Zhang, and Congxu Zhu. "Construction of a New 2D Hyperchaotic Map with Application in Efficient Pseudo-Random Number Generator Design and Color Image Encryption." Mathematics 11, no. 14 (2023): 3171. http://dx.doi.org/10.3390/math11143171.
Full textAbstract:
This paper proposes a new two-dimensional discrete hyperchaotic system and utilizes it to design a pseudo-random number generator (PRNG) and an efficient color image encryption algorithm. This hyperchaotic system has very complex dynamic properties and can generate highly random chaotic sequences. The complex hyperchaotic characteristics of the system are confirmed via bifurcation diagram, chaotic attractor, Lyapunov exponents, correlation analysis, approximate entropy and permutation entropy. Compared with some traditional discrete chaotic systems, the new chaotic system has a larger range of chaotic parameters and more complex hyperchaotic characteristics, making it more suitable for application in information encryption. The proposed PRNG can generate highly random bit sequences that can fully pass all NIST testing items. The proposed color image encryption algorithm achieves cross-channel permutation and diffusion of pixels in parallel. These strategies not only greatly improve the encryption speed of color images, but also enhance the security level of cipher images. The simulation experiments and security analysis results show that the algorithm has strong robustness against differential attacks, statistical attacks and interference attacks, and has good application potential in real-time secure communication applications of color images.
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Klein, Netanel, Eyal Harel, and Itamar Levi. "The Cost of a True Random Bit—On the Electronic Cost Gain of ASIC Time-Domain-Based TRNGs." Cryptography 5, no. 3 (2021): 25. http://dx.doi.org/10.3390/cryptography5030025.
Full textAbstract:
Random number generators are of paramount importance in numerous fields. Under certain well-defined adversarial settings, True Random Number Generators (TRNGs) are more secure than their computational (pseudo) random number generator counterparts. TRNGs are also known to be more efficiently implemented on hardware platforms where, for various applications, efficiency in terms of electronic cost factors is critical. In this manuscript, we first provide an evaluation of robustness and reliability of efficient time-domain-based TRNG implementation over FPGA platform. In particular, we demonstrate sensitivities which imply a TRNG construction which is not agnostic to electronic-design-automation tools and to the level of designers’ know-how. This entails a large amount of effort and validation to make the designs robust, as well as requires a high degree of complexity from non-trivial FPGAs flows. This motivates the second part of the manuscript, where we propose an ASIC-based implementation of the TRNG, along with the optimization steps to enhance its characteristics. The optimized design improves the randomness-throughput by 42× for the same entropy level described in previous works, and it can provide maximal entropy level of 0.985 with 7× improvement in randomness throughput over the raw samples (no pre-processing). The proposed design simultaneously provides a reduced energy of 0.1 (mW/bit) for the same entropy level as previous works, and 1.06 (mW/bit) for the higher entropy flavor, and a lower area utilization of 0.000252 (mm2) on a 65 nm technology evaluation, situating it in the top-class of the discuss ratings. This leads to the quantitative question of the gain in electronic cost factors over ASIC TRNGs, and the minimum Cost Per Bit/Source possible to date. Finally, we exemplify a TRNG versus PRNG cost-extrapolation for security architects and designers, targeting an ASIC scenario feeding a lightweight encryption core.
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Mamun, Md Selim Al, and Fatema Akhter. "Pseudo Random Binary Sequence Based on Cyclic Difference Set." Symmetry 12, no. 8 (2020): 1202. http://dx.doi.org/10.3390/sym12081202.
Full textAbstract:
With the increasing reliance on technology, it has become crucial to secure every aspect of online information where pseudo random binary sequences (PRBS) can play an important role in today’s world of Internet. PRBS work in the fundamental mathematics behind the security of different protocols and cryptographic applications. This paper proposes a new PRBS namely MK (Mamun, Kumu) sequence for security applications. Proposed sequence is generated by primitive polynomial, cyclic difference set in elements of the field and binarized by quadratic residue (QR) and quadratic nonresidue (QNR). Introduction of cyclic difference set makes a special contribution to randomness of proposed sequence while QR/QNR-based binarization ensures uniformity of zeros and ones in sequence. Besides, proposed sequence has maximum cycle length and high linear complexity which are required properties for sequences to be used in security applications. Several experiments are conducted to verify randomness and results are presented in support of robustness of the proposed MK sequence. The randomness of proposed sequence is evaluated by popular statistical test suite, i.e., NIST STS 800-22 package. The test results confirmed that the proposed sequence is not affected by approximations of any kind and successfully passed all statistical tests defined in NIST STS 800-22 suite. Finally, the efficiency of proposed MK sequence is verified by comparing with some popular sequences in terms of uniformity in bit pattern distribution and linear complexity for sequences of different length. The experimental results validate that the proposed sequence has superior cryptographic properties than existing ones.
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Rivaldo, Rian, Handrizal Handrizal, and Herriyance Herriyance. "Pengamanan Pesan Menggunakan Metode MLSB PRNG dan Kompresi File dengan Algoritma RLE pada File Audio." JURNAL SISTEM INFORMASI BISNIS 11, no. 1 (2020): 1–8. http://dx.doi.org/10.21456/vol11iss1pp1-8.
Full textAbstract:
The development of sending messages from one place to another can be done regardless of distance and time. However, the delivery of these messages is hampered by problems of confidentiality and message security. Especially if the data contains important and confidential information that not just anyone is allowed to read and find out about it. In overcoming this problem, steganography techniques can be used with the Modified Least Significant Bit algorithm, where the determination of the embedding index is based on random numbers generated by the Pseudo-Random Number Generator with the Multiply with Carry algorithm. In addition to security, data size is also an important factor in data transmission. The larger the size the more time it will take to transmit the data. Therefore, the Run Length Encoding algorithm is needed to compress the data size, which will shorten the time to transmit the data. In the message extraction process, a stego key is needed to generate random numbers. Based on the testing of the extraction process with an arbitrary key, it is obtained that the message tested is not the original message that has been embedded previously. In the results of the embedding and extraction process, it is obtained that the average value of PSNR is 63.61498 dB, which means the quality of the stego object produced is quite good. Whereas the measurement of file compression performance results with an average value of Compression Ratio at 1.00113, Space Savings at 0.1133%, and Bitrate at 584025.33 bits/sample. These results indicate that RLE algorithm compression is not efficient to compress file sizes.
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Simbolon, Buha Johannes. "Steganografi Penyisipan Pesan Pada File Citra Dengan Menggunakan Metode LSB (Least Significant Bit)." Jurnal Nasional Komputasi dan Teknologi Informasi (JNKTI) 4, no. 1 (2021): 1–6. http://dx.doi.org/10.32672/jnkti.v4i1.2656.
Full textAbstract:
The rapid development of technology not only has a positive impact, but can also have a negative impact on the users of this technology. One of them is the development of cyber crime which causes messages to be unsafe to protect. Message security can be protected by using steganography to convert messages into secret passwords. To make the secret password more secure, steganography techniques are used. Steganography is a technique for hiding messages by inserting messages into other containers. In this study, a combination of two algorithms is used, namely the RC4 and Base Cryptography algorithm, which is better known as the Super Encryption algorithm and the steganography technique using the Least Significant Bit (LSB) method with random pixel insertion using a pseudorandom number generator (PRNG). Algorithm use. the scope of the problem is the information insertion media used, the process of making data into information and sending to message recipients, the method used in writing the thesis using LSB (Least Significant Bit) and the programming language used in building this system is PHP (Hypertext Preprocessor) with MySQL database (My Structured Query Language) on PhpMyAdmin.
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Maache, Ahmed, and Abdesattar Kalache. "Design and Implementation of a flexible Multi-purpose Cryptographic System on low cost FPGA." International journal of electrical and computer engineering systems 14, no. 1 (2023): 45–58. http://dx.doi.org/10.32985/ijeces.14.1.6.
Full textAbstract:
The design of cryptographic hardware that supports multiple cryptographic primitives is common in literature. In this work, a new design is presented consisting of a multi-purpose cryptographic system featuring both 128-bit pipelined AES-CORE (Advanced Encryption Standard) for high-speed symmetric encryption and a Keccak hash core on a low-cost FPGA. The KECCAK-CORE’s security and performance parameters are tunable in the sense that capacity, bitrate, and the number of rounds can be user-defined. Such flexibility enables the core to suit a large range of security requirements. The structure of Keccak’s sponge construction is exploited to enable different modes of operation. An example application outlined in this work is Pseudo Random Number Generation (PRNG). With few adjustments, the KECCAK-CORE was also operated as a post-processing unit for True Random Number Generation (TRNG) that uses the analog Lorenz chaotic circuit as a physical entropy source. The multi-purpose design was implemented in VHDL targeting an IntelFPGA Cyclone-V FPGA. For AES symmetric encryption, a maximum throughput of 31.1Gbps was achieved and a logic usage of 25146LEs (23% of the FPGA) in the case of the pipelined variant of AES-CORE. For the KECCAK-CORE, maximum throughput figures of 5.81, 8.4, and 11Gbps were achieved for the three SHA-3 variants 512, 384, and 256-bit respectively, with an area usage of 8947LEs (8%). The system as a whole occupies an area of 26909LEs (26%). The random sequences generated by the system operating in PRNG and TRNG post- processing modes successfully passed the National Institute of Standards and Technology (NIST) statistical test suite (NIST SP 800-22). The information entropy analysis performed on the post-processed TRNG sequences indicates an average of 0.935.
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Lurina, Manda, Sugondo Hadiyoso, and Rina Pudji Astuti. "Scrambling and De-Scrambling Implementation Using Linear Feedback Shift Register Method on FPGA." IJAIT (International Journal of Applied Information Technology) 1, no. 02 (2017): 59–67. http://dx.doi.org/10.25124/ijait.v1i02.876.
Full textAbstract:
communication system, a long sequence of bits ‘0’ or ‘1’ will inherits the loss of bit synchronization, and hence it can cause the false detection on the receiver. To avoid this, long sequence of bits will be randomized first so that long sequence of bits ‘0’ or ‘1’ can be removed. This randomization process is called scrambling and the circuit that works for the process is a scrambler. In the receiver there is a descrambler that serves to return the bits to their original information. This paper presents a design of scrambler and descrambler using a combination of Linear Feedback Shift Register (LFSR) with 15 registers, XOR logic gates, and Pseudo Random Binary Sequence (PRBS) generator structure with polynomial 1 + x14 + x15. One of the two main parts of LFSR is the shift register while the other is the feedback. In LFSR, the bits contained within the selected position in the shift register will be combined in a function and the result will be put back into this register's input bit. Feedback also makes the system more stable and no error occurrence. Then special tap is taken from a certain point in XOR and returned as a feedback register. The system is implemented on FPGA board Altera De0-Nano EP4CE22F17C6 Cyclone IV E. Resource memory required <1% of available memory. Bit rate that can be achieved with clock speed 50MHz is 335570.47 bps.
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Nishitani, Yoshi, Chie Hosokawa, Yuko Mizuno-Matsumoto, Tomomitsu Miyoshi, Hajime Sawai, and Shinichi Tamura. "Detection of M-Sequences from Spike Sequence in Neuronal Networks." Computational Intelligence and Neuroscience 2012 (2012): 1–9. http://dx.doi.org/10.1155/2012/862579.
Full textAbstract:
In circuit theory, it is well known that a linear feedback shift register (LFSR) circuit generates pseudorandom bit sequences (PRBS), including an M-sequence with the maximum period of length. In this study, we tried to detect M-sequences known as a pseudorandom sequence generated by the LFSR circuit from time series patterns of stimulated action potentials. Stimulated action potentials were recorded from dissociated cultures of hippocampal neurons grown on a multielectrode array. We could find several M-sequences from a 3-stage LFSR circuit (M3). These results show the possibility of assembling LFSR circuits or its equivalent ones in a neuronal network. However, since the M3 pattern was composed of only four spike intervals, the possibility of an accidental detection was not zero. Then, we detected M-sequences from random spike sequences which were not generated from an LFSR circuit and compare the result with the number of M-sequences from the originally observed raster data. As a result, a significant difference was confirmed: a greater number of “0–1” reversed the 3-stage M-sequences occurred than would have accidentally be detected. This result suggests that some LFSR equivalent circuits are assembled in neuronal networks.
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Cheng, Shuli, Liejun Wang, Naixiang Ao, and Qingqing Han. "A Selective Video Encryption Scheme Based on Coding Characteristics." Symmetry 12, no. 3 (2020): 332. http://dx.doi.org/10.3390/sym12030332.
Full textAbstract:
The protection of video data has become a hot topic of research. Researchers have proposed a series of coding algorithms to ensure the safe and efficient transmission of video information. We propose an encryption scheme that can protect video information with higher security by combining the video coding algorithm with encryption algorithm. The H.264/AVC encoding algorithm encodes the video into multiple slices, and the slices are independent of each other. With this feature, we encrypt each slice while using the cipher feedback (CFB) mode of the advanced encryption standard (AES) with the dynamic key. The key is generated by the pseudo-random number generator (PRNG) and updated in real time. The encryption scheme goes through three phases: constructing plaintext, encrypting plaintext, and replacing the original bitstream. In our scheme, we encrypt the code stream after encoding, so it does not affect the coding efficiency. The purpose of the CFB mode while using the AES encryption algorithm is to maintain the exact same bit rate and produce a format compatible bitstream. This paper proposes a new four-dimensional (4-D) hyperchaotic algorithm to protect data privacy in order to further improve the security of video encryption. Symmetric encryption requires that the same key is used for encryption and decoding. In this paper, the symmetry method is used to protect the privacy of video data due to the large amount of video encrypted data. In the experiment, we evaluated the proposed algorithm while using different reference video sequences containing motion, texture, and objects.
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Hsiu-Chi Tseng, Hsiu-Chi Tseng, and King-Chu Hung Hsiu-Chi Tseng. "Robust Zero-Watermarking by Circular Features and 1-D NRDPWT Transformation." 電腦學刊 35, no. 1 (2024): 109–29. http://dx.doi.org/10.53106/199115992024023501008.
Full textAbstract:
<p>This paper introduces a secure and robust zero-watermarking framework that leverages the advantages of zero-watermarking, ensuring non-destructive modification of original images and unlimited capacity. The proposed method enables robust watermark embedding while preserving the original image. It employs a novel feature extraction approach using circular areas based on image radius, enhancing feature resilience. Additionally, applying one-dimensional non-recursive discrete periodized wavelet transform (1-D NRDPWT) converts feature values into phi, contributing to enhanced stability and robustness. Enhanced security is achieved through the use of Shuffle and Pseudo-Random Number Generator (PRNG). Experimental results, evaluated using metrics such as Bit Error Rate (BER) and Normalized Correlation (NC), validate the exceptional performance of this watermarking technique. These findings underscore the framework&rsquo;s robustness, security, reliability, and integrity against both general and geometric noise attacks, making it a secure and robust solution for modern digital image copyright protection. In summary, our method offers an effective defense against various noise attacks while ensuring the highest watermark quality without compromising the original image. It is a significant advancement in copyright protection applications.</p> <p>&nbsp;</p>
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Misra, Shashank, Christopher R. Allemang, J. Darby Smith, Suma G. Cardwell, James B. Aimone, and Andrew D. Kent. "(Invited) There’s More to a Probabilistic Neuromorphic Computing System Than Noisy Devices." ECS Meeting Abstracts MA2024-01, no. 57 (2024): 3019. http://dx.doi.org/10.1149/ma2024-01573019mtgabs.
Full textAbstract:
A range of computing problems require understanding uncertainty, such as climate modeling, or use statistics to model problems that are otherwise difficult to solve, such as high energy particle collisions. Currently, these computations are handled by hardware where significant energy is spent to suppress stochasticity in materials and devices, and then significant computational resources are expended to re-introduce stochasticisty in algorithms. Instead, we take inspiration from the brain, which features 1015 stochastic synapses. This talk focuses on understanding how to leverage fluctuations in devices to do efficient sampling, which is a fundamental operation in many statistical approaches to computation [1]. In the first part of this talk, we use bitstreams generated by magnetic tunnel junction and tunnel diode devices to generate samples from different distributions, an elementary operation in statistical approaches to modeling. We show how to use elementary operations on multiple bits to improve both the accuracy and complexity of sampling. While intuition motivates the asking which of the two devices is more efficient at generating a random bitstream, in the second part of this talk, we show that this consideration is a small contribution to the overall circuit required to do a complete calculation. To significantly accelerate applications requires devices that minimize the energy and area cost of the CMOS parts of the design, as the true challenge lies in holistic codesign [2]. At the heart of statistical approaches to computation is sampling. Typically, a uniform random sample is generated using a pseudo-random number generator (PRNG), followed by a mathematical operation to sample an application-relevant distribution. This sample is then plugged into a sequence of deterministic calculations that comprise a model. We use magnetic tunnel junctions and tunnel diodes to generate a fair coinflip, having equal probability of each of two outscomes, from which we create a uniform random sample. We show how to relate the quality of the device bitstreams to the quality of random samples [3]. While these devices consume significantly less energy than the PRNG, the energy consumed by the PRNG is a fraction of the energy consumed by a complete calculation. We next focus on moving the entire process of sampling non-uniform distributions into hardware. We show that weighted coinflips can be used to sample any distribution with a well-defined probability distribution function using a tree. Simple logic operations can be used to combine many inaccurate fair physical coinflips to produce a single high-accuracy weighted logical coinflip, and high quality samples from non-uniform distributions. Overall, a simple implementation uses a few hundred physical coinflips, some simple logic operations (shift register, comparison, XOR extractor), and memory access to produce a sample. This success points to the potential for moving more of the model into increasingly sophisticated sampling schemes. Having established how the basic element of the computation are connected, we are now ready to examine its efficiency compared to a PRNG, whose cost is roughly nJ/operation. Thus far, we have ignored the analog signal transduction attached to the coinflip devices and the logic operations that tie them together. Coinflip devices which cannot be directly integrated with logic will suffer from a von Neumann bottleneck. Thus, the coinflip devices need to be intimately integrated with logic, requiring paying a per-device transduction penalty. We find the energy cost for even the simplest signal transduction – a stimulating pulse and a latching output – is in the 100 fJ – 1 pJ per device range, which is larger than the energy consumed by either magnetic tunnel junctions or tunnel diodes. Meanwhile, the most expensive component of the logic operations stem from the fine-grained integration of memory. While only 32 weighted coinflips are needed to draw a 32-bit non-uniform sample, there are ~232 possible weights needed. We discuss schemes to prune the values needed to avoid the situation where the weights occupy all of a 1 cm2 die. In sum, the energy and area cost of the coinflip device are less important than the energy cost of signal transduction, and the area taken by memory for storing weights of a sampling tree. We emphasize that none of our estimates represents a tight optimization of any part of an imagined probabilistic computer. Still, in a full-system implementation, the efficient management of signal transduction and memory clearly outweight the energy or space consumed by the coinflip devices themselves. These factors comprise the key variables for stochastic devices that need to be accounted for in holistic codesign for probabilistic computing. SNL is managed and operated by NTESS under DOE NNSA contract DE-NA0003525.
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Pieprzyk, Josef, Marcin Pawłowski, Paweł Morawiecki, Arash Mahboubi, Jarek Duda, and Seyit Camtepe. "Pseudorandom bit generation with asymmetric numeral systems." International Journal of Information Security 24, no. 2 (2025). https://doi.org/10.1007/s10207-025-00995-4.
Full textAbstract:
Abstract The generation of pseudorandom binary sequences is of great importance in numerous applications, ranging from simulation and gambling to cryptography. Pseudorandom bit generators (PRBGs) can be divided into two categories based on their claimed security. The first category includes PRBGs that are provably secure, such as the Blum–Blum–Shub generator. The security of the second category relies on heuristic arguments. Unfortunately, PRBGs from the first category are inherently inefficient, and some are vulnerable to quantum attacks. In contrast, those in the second category are highly efficient, though their security depends on their resistance to known cryptographic attacks. This work presents a construction of a PRBG based on the asymmetric numeral system (ANS) compression algorithm. We define a family of PRBGs for $$2^R$$ 2 R ANS states and prove that it is indistinguishable from a truly random generator for sufficiently large R. To enhance efficiency, we explore PRBGs with smaller values of $$R = 7, 8, 9$$ R = 7 , 8 , 9 and demonstrate methods for removing local correlations in the output stream. We permute output bits using rotation and Keccak transformations, showing that the permuted bits pass all NIST tests. Our PRBG design is provably secure for large values of R and heuristically secure for smaller values. Additionally, we claim that our PRBG is secure against quantum adversaries.
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Ndaw, Babacar Alasane, Ousmane Ndiaye, Mamadou Sanghar´e, and Cheikh Thi´ecoumba Gueye. "A New Statistical Test for PRNG Based on the Attendance’s Law." Journal of Advances in Mathematics and Computer Science, March 10, 2021, 37–46. http://dx.doi.org/10.9734/jamcs/2021/v36i130328.
Full textAbstract:
One family of the cryptographic primitives is random Number Generators (RNG) which have several applications in cryptography such that password generation, nonce generation, Initialisation vector for Stream Cipher, keystream. Recently they are also used to randomise encryption and signature schemes.
 A pseudo-random number generator (PRNG) or a pseudo-random bit generator (PRBG) is a deterministic algorithm that produces numbers whose distribution is on the one hand indistinguishable from uniform ie. that the probabilities of appearance of the different symbols are equal and that these appearances are all independent. On the other hand, the next output of a PRNG must be unpredictable from all its previous outputs. Indeed, A set of statistical tests for randomness has been proposed in the literature and by NIST to evaluate the security of random(pseudo) bit or block. Unfortunately there are non-random binary streams that pass these standardized tests.
 In this pap er, as outcome, we intro duce on the one hand a new statistical test in a static contextcalled attendance’s law and on the other hand a distinguisher based on this new attendance’s law.
 
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"FPGA Hardware Co-Simulation of Image Encryption using Hybrid Chaotic Maps Based Stream Cipher." International Journal of Engineering and Advanced Technology 9, no. 4 (2020): 215–25. http://dx.doi.org/10.35940/ijeat.d6713.049420.
Full textAbstract:
In This paper, new model of image encryption is designed. This model using stream cipher based on finite precision chaotic maps. The model designed in efficient way by using Xilinx System Generator (XSG). Pseudo Random Bit Generator (PRBG) depends on chaotic maps is proposed to design Fixed Point Hybrid Chaotic Map-PRBG (FPHYBCM-PRBG). National Institute of Standards and Technology (NIST) randomness measures tested the randomness of the proposed FPHYBCM-PRBG system. The security analysis, such as histogram, correlation coefficient, information entropy, differential attack (NPCR and UACI) are used to analyze the proposed system. Also, FPGA Hardware Co-Simulation over Xilinx SP605 XC6SLX45T provided to test the reality of image encryption system. The results show that FPHYBCM-PRBG is suitable for image encryption based on stream cipher and outperform some encryption algorithms in sufficient way to enhance the security and robust against brute force attack with low maximum frequency and throughput.
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Nazish, Mir, Munika Javid, and M. Tariq Banday. "Enhanced logistic map with infinite chaos and its applicability in lightweight and high-speed pseudo-random bit generation." Cybersecurity 8, no. 1 (2025). https://doi.org/10.1186/s42400-024-00319-4.
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Abstract Chaotic maps are employed in cryptography and secure communications due to their unpredictable and complex dynamics. However, existing chaotic maps, specifically the one-dimensional chaotic maps, often have limited chaotic control parameter ranges, which restricts their effectiveness and applicability in practical low-end applications. This paper proposes an enhanced Logistic map with an infinite chaotic control parameter range to address these limitations. The performance of the proposed map has been comprehensively evaluated using various chaos dynamical tests, including the bifurcation diagram, Lyapunov exponent, cobweb plots, 2D and 3D phase plots, approximate entropy, and sample entropy, time sensitivity analysis, and the 0–1 test. The results demonstrate that the improved Logistic map significantly outperforms its seed map across all evaluation metrics. Additionally, the enhanced Logistic map-based pseudorandom bit generator (PRBG) has been designed and evaluated for resource efficiency and security. The findings validate that the PRBG achieves significant implementation efficiency while also successfully qualifying the fifteen NIST tests, validating its statistical randomness. Thus, the proposed map and the PRBG position themselves as lightweight, highly secure solutions for safeguarding resource-limited smart IoT applications.
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"FPGA Design of Encryption Speech system using Synchronized Fixed-Point Chaotic Maps Based Stream Ciphers." International Journal of Engineering and Advanced Technology 8, no. 6 (2019): 1534–41. http://dx.doi.org/10.35940/ijeat.f8156.088619.
Full textAbstract:
In this work, speech encryption using synchronized fixed-point chaotic map-based stream ciphers (SFPCM-SC) is suggested. Five chaotic maps named quadratic, henon, logistic, lozi and duffing are synchronized by using master-slave synchronization technique and then used to generate the pseudo random bit generator (PRBG) using fixed-point converter. The PRBG is then Xor-ed with digitized speech signal where the encrypted signal is created. In the other side, the same map is synchronized with the master one and used to recover the original speech signal. First this work is simulated by using MATLAB and then built the design using Xilinx system generator (XSG). Finally, the hardware co-simulation is applied for the proposed system by using FPGA SP605 XC6SLX45T device. The results show that the error between master and slave become zero after a small period and the original speech signal is recovered with real time environment in successful.
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Usha, S., and M. Kanthimathi. "Design and Comparison of 24-bit Three Operand Adders using Parallel Prefix method for Efficient Computations." ICST Transactions on Scalable Information Systems, February 1, 2024. http://dx.doi.org/10.4108/eetsis.5004.
Full textAbstract:
Binary Three-operand adder serves as a foundation block used within security and Pseudo Random-Bit Generator (PRBG) systems. Binary Three-operand adder was designed using Carry Save Adder but this consumes more delay. Therefore, a Parallel Prefix Adder (PPA) method can be utilized for faster operation. The canonical types of PPA result in a lesser path delay of approximately O (log2 n). These adders can be designed for 8, 16, 24 or n bits. But this work is focused on developing a 24-bit three-operand adder that takes three 24-bit binary numbers as input and generates a 24-bit sum output and a carry using five different PPA methods The proposed summing circuits are operationalized with Hardware-Description-Language (HDL) using Verilog, and then subjected to synthesis using Field -Programmable Gate- Array (FPGA) Vertex 5. On comparing the proposed adders, it shows that the delay and the size occupied are significantly less in the Sklansky PPA. These faster three-operand adders can be utilized for three-operand multiplication in image processing applications and Internet of Things (IoT) security systems.
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"High – Speed and Low Area-Efficient VLSI Architecture of Three-Operand Binary Adder." Journal on Electronic and Automation Engineering 3, no. 2 (2024): 13–17. http://dx.doi.org/10.46632/jeae/3/2/02.
Full textAbstract:
Three-operand binary adder is the basic functional unit to perform the modular arithmetic in various cryptography and Pseudo Random Bit Generator (PRBG) algorithms and also used in many applications. Carry Save Adder (CS3A) is the widely used technique to perform the three- operand addition. In carry save adder at final stage uses ripple carry adder which will cause large critical path delay. Moreover, a parallel prefix two-operand adder such as Han-Carlson Adder (HCA) can also be used for three-operand addition that significantly reduces the critical path delay with more area complexity. Hence, a new high-speed and area-efficient adder architecture is proposed using pre-compute bitwise addition followed by carry prefix computation logic to perform the three-operand binary addition that consumes substantially less area and less delay. The effectiveness of the proposed method is designed using Xilinx ISE 14.7
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"Minimizing Area and Maximizing Speed in Three-Operand Binary Adder Design." Journal on Electronic and Automation Engineering 4, no. 2 June 2025 (2025): 189–94. https://doi.org/10.46632/jeae/4/2/26.
Full textAbstract:
Three-operand binary adder is the basic functional unit to perform the modular arithmetic in various cryptography and Pseudo Random Bit Generator (PRBG) algorithms and also used in many applications. Carry Save Adder (CS3A) is the widely used technique to perform the three- operand addition. In carry save adder at final stage uses ripple carry adder which will cause large critical path delay. Moreover, a parallel prefix two-operand adder such as Han-Carlson Adder (HCA) can also be used for three- operand addition that significantly reduces the critical path delay with more area complexity. Hence, a new high-speed and area- efficient adder architecture is proposed using pre-compute bitwise addition followed by carry prefix computation logic to perform the three-operand binary addition that consumes substantially less area and less delay. The effectiveness of the proposed method is designed using Xilinx ISE14.7.
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Ryan, Conor, Meghana Kshirsagar, Gauri Vaidya, Andrew Cunningham, and R. Sivaraman. "Design of a cryptographically secure pseudo random number generator with grammatical evolution." Scientific Reports 12, no. 1 (2022). http://dx.doi.org/10.1038/s41598-022-11613-x.
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AbstractThis work investigates the potential for using Grammatical Evolution (GE) to generate an initial seed for the construction of a pseudo-random number generator (PRNG) and cryptographically secure (CS) PRNG. We demonstrate the suitability of GE as an entropy source and show that the initial seeds exhibit an average entropy value of 7.940560934 for 8-bit entropy, which is close to the ideal value of 8. We then construct two random number generators, GE-PRNG and GE-CSPRNG, both of which employ these initial seeds. We use Monte Carlo simulations to establish the efficacy of the GE-PRNG using an experimental setup designed to estimate the value for pi, in which 100,000,000 random numbers were generated by our system. This returned the value of pi of 3.146564000, which is precise up to six decimal digits for the actual value of pi. We propose a new approach called control_flow_incrementor to generate cryptographically secure random numbers. The random numbers generated with CSPRNG meet the prescribed National Institute of Standards and Technology SP800-22 and the Diehard statistical test requirements. We also present a computational performance analysis of GE-CSPRNG demonstrating its potential to be used in industrial applications.
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Moussa, Karim H., Shawki Shaaban, and Ahmed H. El-Sakka. "Secured polar code derived from random hopped frozen-bits." Wireless Networks, September 27, 2022. http://dx.doi.org/10.1007/s11276-022-03127-1.
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AbstractThe polar code is a unique coding approach that can achieve Shannon's capacity in modern communication systems' discrete memory-less channels with superior reliability, but it is not secure enough under modern attacks for such systems. This study aims to offer a comprehensive secured polar coding scheme that uses a combination of polar coding and the Mersenne-Twister pseudo-random number generator (MT-PRNG) to achieve a super secured encoding. The pre-shared crypto-system cyphering key initiates the starting state of the MT-PRNG as a seed. The randomly generated sequences govern the values of the frozen bits in polarized bit channels and their associated indices. A half-bit-error-rate probability system performance is calculated when the encoding ciphering keys at the receiver differ by a single bit from those utilized at the transmitter. Using calculated numerical analysis, the system is shown to be secure against brute force attacks, Rao-Nam attacks, and polar code reconstruction attacks.
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Eid, Mahmoud M. A., Ahmed Nabih Zaki Rashed, Eman Mohsen El-gammal, Tahesin Samira Delwar, and Jee Youl Ryu. "The influence of electrical filters with sequence generators on optical ISL performance evolution with suitable data rates." Journal of Optical Communications, December 17, 2020. http://dx.doi.org/10.1515/joc-2020-0257.
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AbstractThe work offered the analysis comparison study of optical wireless intersatellite link (ISL) for both different bit sequence generators and filters. The study clarifies the impact of varying sorts of both bit sequence generator (data source) in the transmitter and electrical filters in receiver on system performance. The two bit sequence generators used are pseudo random bit sequence generator (PRBSG) and user-defined bit sequence generator (UDBSG). The used filters in this study are low pass (LP) Bessel filter, LP Gaussian filter, LPCROF (cosine roll-off filter), and LPSCROF (squared CROF). Performance of the filter depends on the order of filter and filter bandwidth. The performance parameters in our study are quality factor, Bit Error Rate (BER), and optical received power. In this study, variation of optical received power depends on the type of sequence generator because it is measured after the channel directly.
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Sukumaran, Ajitha. "Pseudo Random Bits Generation Using Chaotic Functions." Journal of Student Research, December 31, 2017. http://dx.doi.org/10.47611/jsr.vi.540.
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The telecommunication development technologies especially mobile and internet networks had extended the demand of information transmission. This results as a challenge to protect the information from the attackers. These require advanced encryption systems to protect the information during transmission. Cryptography is a basic information security measure that encodes messages to make them non-readable. During last two and a half decades, several studies of chaos based on cryptosystems had been developed. An application of discrete chaotic dynamical systems in pseudo random bit generation (PRBG) has been widely studied recently. In each study, proposed a separate pseudo random generation for a particular map running side-by-side in one of them or proposing a hybrid chaotic system used two different maps. The PRBG is generated by combining then comparing the output of both chaotic maps. This report will show the previous studies done in the different ways to generate pseudo random bit. Methods will be discussed in details for the algorithmic formula done for each system and what logical operations done for combination and comparing the output for each.The generated chaotic sequence is implemented for encrypting and decrypting the image and text message
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Gupta, Mangal Deep, and R. K. Chauhan. "Hardware Efficient Pseudo-Random Number Generator using Chen Chaotic System on FPGA." Journal of Circuits, Systems and Computers, September 2, 2021, 2250043. http://dx.doi.org/10.1142/s0218126622500438.
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This paper introduces an FPGA implementation of a pseudo-random number generator (PRNG) using Chen’s chaotic system. This paper mainly focuses on the development of an efficient VLSI architecture of PRNG in terms of bit rate, area resources, latency, maximum length sequence, and randomness. First, we analyze the dynamic behavior of the chaotic trajectories of Chen’s system and set the parameter’s value to maintain low hardware design complexity. A circuit realization of the proposed PRNG is presented using hardwired shifting, additions, subtractions, and multiplexing schemes. The benefit of this architecture, all the binary multiplications (except [Formula: see text] and [Formula: see text] operations are performed using hardwired shifting. Moreover, the generated sequences pass all the 15 statistical tests of NIST, while it generates pseudo-random numbers at a uniform clock rate with minimum hardware complexity. The proposed architecture of PRNG is realized using Verilog HDL, prototyped on the Virtex-5 FPGA (XC5VLX50T) device, and its analysis has been done using the Matlab tool. Performance analysis confirms that the proposed Chen chaotic attractor-based PRNG scheme is simple, secure, and hardware efficient, with high potential to be adopted in cryptography applications.
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Yu, Fei, Zinan Zhang, Hui Shen, et al. "Design and FPGA Implementation of a Pseudo-random Number Generator Based on a Hopfield Neural Network Under Electromagnetic Radiation." Frontiers in Physics 9 (June 4, 2021). http://dx.doi.org/10.3389/fphy.2021.690651.
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When implementing a pseudo-random number generator (PRNG) for neural network chaos-based systems on FPGAs, chaotic degradation caused by numerical accuracy constraints can have a dramatic impact on the performance of the PRNG. To suppress this degradation, a PRNG with a feedback controller based on a Hopfield neural network chaotic oscillator is proposed, in which a neuron is exposed to electromagnetic radiation. We choose the magnetic flux across the cell membrane of the neuron as a feedback condition of the feedback controller to disturb other neurons, thus avoiding periodicity. The proposed PRNG is modeled and simulated on Vivado 2018.3 software and implemented and synthesized by the FPGA device ZYNQ-XC7Z020 on Xilinx using Verilog HDL code. As the basic entropy source, the Hopfield neural network with one neuron exposed to electromagnetic radiation has been implemented on the FPGA using the high precision 32-bit Runge Kutta fourth-order method (RK4) algorithm from the IEEE 754-1985 floating point standard. The post-processing module consists of 32 registers and 15 XOR comparators. The binary data generated by the scheme was tested and analyzed using the NIST 800.22 statistical test suite. The results show that it has high security and randomness. Finally, an image encryption and decryption system based on PRNG is designed and implemented on FPGA. The feasibility of the system is proved by simulation and security analysis.
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Johansson, Thomas, Willi Meier, and Vu Nguyen. "Attacks on the Firekite Cipher." IACR Transactions on Symmetric Cryptology, September 9, 2022, 191–216. http://dx.doi.org/10.46586/tosc.v2022.i3.191-216.
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Firekite is a synchronous stream cipher using a pseudo-random number generator (PRNG) whose security is conjectured to rely on the hardness of the Learning Parity with Noise (LPN) problem. It is one of a few LPN-based symmetric encryption schemes, and it can be very efficiently implemented on a low-end SoC FPGA. The designers, Bogos, Korolija, Locher and Vaudenay, demonstrated appealing properties of Firekite, such as requiring only one source of cryptographically strong bits, small key size, high attainable throughput, and an estimate for the bit level security depending on the selected practical parameters.We propose distinguishing and key-recovery attacks on Firekite by exploiting the structural properties of its PRNG. We adopt several birthday-paradox techniques to show that a particular sum of Firekite’s output has a low Hamming weight with higher probability than the random case. We achieve the best distinguishing attacks with complexities 266.75 and 2106.75 for Firekite’s parameters corresponding to 80-bit and 128-bit security, respectively. By applying the distinguishing attacks and an additional algorithm we describe, one can also recover the secret matrix used in the Firekite PRNG, which is built from the secret key bits. This key recovery attack works on most large instances of Firekite parameters and has slightly larger complexity, for instance, 269.87 on the 80-bit security parameters n = 16,384, m = 216, k = 216.