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Journal articles on the topic 'Pseudo-differential amplifier'

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Published: 3 June 2025

Last updated: 13 July 2025

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Shainda, J. Tahseen*1 Sandeep Singh 2. "REVIEW PAPER ON PSEUDO-DIFFERENTIAL AND BULK-DRIVEN MOS TRANSISTOR TECHNIQUE FOR OTA." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 6, no. 7 (2017): 596–601. https://doi.org/10.5281/zenodo.829785.

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This paper presents review on Pseudo-Differential amplifier technique and Bulk-Driven MOS transistor technique for ultra-low voltage and power. By using this technique, a different design of operational transconductance amplifier (OTA) is briefly explained along with their outputs and their application. By using a pseudo-differential technique a voltage drop across the tail current is avoid as the tail-current is removed in Pseudo-differential amplifier where as by using the Bulk-Driven MOS transistor a minimum supply voltage is achieved because of the possibility in reduction of threshold voltage<strong>.</strong>

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Atkin, E. V., and V. V. Shumikhin. "Charge Sensitive Amplifier with Pseudo-differential Output." Russian Microelectronics 50, no. 3 (2021): 206–10. http://dx.doi.org/10.1134/s1063739721020037.

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NGUYEN, Huy-Hieu, Jeong-Seon LEE, and Sang-Gug LEE. "Low Voltage Current-Reused Pseudo-Differential Programmable Gain Amplifier." IEICE Transactions on Electronics E93-C, no. 1 (2010): 148–50. http://dx.doi.org/10.1587/transele.e93.c.148.

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Giustolisi, Gianluca, Alfio Dario Grasso, and Salvatore Pennisi. "High-Drive and Linear CMOS Class-AB Pseudo-Differential Amplifier." IEEE Transactions on Circuits and Systems II: Express Briefs 54, no. 2 (2007): 112–16. http://dx.doi.org/10.1109/tcsii.2006.886239.

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Manfredini, Giuseppe, Alessandro Catania, Lorenzo Benvenuti, Mattia Cicalini, Massimo Piotto, and Paolo Bruschi. "Ultra-Low-Voltage Inverter-Based Amplifier with Novel Common-Mode Stabilization Loop." Electronics 9, no. 6 (2020): 1019. http://dx.doi.org/10.3390/electronics9061019.

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This work presents a single-stage, inverter-based, pseudo-differential amplifier that can work with ultra-low supply voltages. A novel common-mode stabilization loop allows proper differential operations, without impacting over the output differential performance. Electrical simulations show the effectiveness of this amplifier for supply voltages in the range of 0.3–0.5 V. In particular, a dc voltage gain of 25.16 dB, a gain-bandwidth product of 131.9 kHz with a capacitive load of 10 pF, and a static current consumption of only 557 nA are estimated at VDD = 0.5 V. Moreover, the circuit behavior with respect to process and temperature variations was verified. Finally, the proposed amplifier is employed in a switched-capacitor integrator and in a sample-and-hold circuit to prove its functionality in case-study applications.

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Babaeinik, Majid, Massoud Dousti та Mohammad Bagher Tavakoli. "A High Bandwidth (DC-40 GHz) Pseudo Differential Distributed Amplifier in 0.18-μm RF CMOS". Journal of Circuits, Systems and Computers 26, № 12 (2017): 1750191. http://dx.doi.org/10.1142/s0218126617501912.

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This study presents a CMOS distributed amplifier (DA) with pseudo differential amplifying that achieves DC-40[Formula: see text]GHz bandwidth (BW) in 0.18-[Formula: see text]m RF CMOS process. The DA with three-stage amplifying cells was proposed to improve the DA performance. The inter-stage was composed of pseudo differential amplifying for bandwidth extension. By incorporating the pseudo differential amplifier configuration and capacitor-less circuit in the stages, the DA provides average gain and high bandwidth. The simulation results showed that the DA has a S[Formula: see text] of 6.4[Formula: see text]dB, 3-dB BW from DC up to 40[Formula: see text]GHz. It also has a minimum noise figure (NF) of 4.27[Formula: see text]dB, one dB compression point (P[Formula: see text] of [Formula: see text]3.5[Formula: see text]dBm, a high reverse isolation S[Formula: see text] of less than [Formula: see text]15[Formula: see text]dB, an input return loss S[Formula: see text] and output return loss S[Formula: see text] of less than [Formula: see text]16 and [Formula: see text]12[Formula: see text]dB, respectively. It consumes 115[Formula: see text]mW and occupies a total active area of 0.27[Formula: see text]mm2.

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Kasipogula, Bhaskara Rao, and Gurumurthy Komanapalli. "A chopper amplifier with adaptive biasing OTA for biomedical applications, featuring high gain and CMRR." PLOS ONE 19, no. 11 (2024): e0313423. http://dx.doi.org/10.1371/journal.pone.0313423.

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This paper presents a design of fully differential chopper amplifier employing the flipped voltage follower (FVF) adaptive biasing technique, focusing on its potential use in biopotential recording applications. The suggested architectural OTA incorporates self-cascoded current mirrors (SCCMs) as the active load to achieve a substantial output swing. The FVFs based adaptive biasing approach for the differential input stage boosts extra current and enhances gain and dynamic characteristics. The chopper amplifier attains a common mode rejection ratio (CMRR) of more than 100 dB through the strategic utilization of chopper modulators and pseudo-resistors. Additionally, this device exhibits characteristics such as accurate and stable gain, high input impedance, and a compact physical footprint. The present study also includes a comparison between the suggested structure and the bio-potential amplifiers discussed in the existing literature. This comparison is based on key metrics such as gain, input referred noise (IRN), CMRR, and input impedance (Zin). The proposed structure yielded a gain of 63.72 dB, an IRN of 0.07nVrms, a CMRR of 127.97 dB and a Zin of 1.54 GΩ. The bio-potential chopper amplifier under consideration was constructed and simulations were performed by utilizing the Cadence Virtuoso Spectre simulator tool at 180 nm CMOS technology node.

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Ballo, Andrea, Alfio Dario Grasso, and Salvatore Pennisi. "0.4-V, 81.3-nA Bulk-Driven Single-Stage CMOS OTA with Enhanced Transconductance." Electronics 11, no. 17 (2022): 2704. http://dx.doi.org/10.3390/electronics11172704.

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The paper describes a single-stage operational transconductance amplifier suitable for very-low-voltage operation in power-constrained applications. The proposed circuit avoids the tail current generator in the differential pair while preventing pseudo-differential operation. Moreover, the adoption of positive feedback allows increasing the stage transconductance while minimizing the current consumption. Experimental measurements on prototypes implemented in a standard CMOS 180-nm technology, show superior performance as compared to the state of the art.

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Karami Horestani, Fatemeh, Zahra Karami Horastani, and Niclas Björsell. "A Band-Pass Instrumentation Amplifier Based on a Differential Voltage Current Conveyor for Biomedical Signal Recording Applications." Electronics 11, no. 7 (2022): 1087. http://dx.doi.org/10.3390/electronics11071087.

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Recently, due to their abundant benefits, current-mode instrumentation amplifiers have received considerable attention in medical instrumentation and read-out circuit for biosensors. This paper is focused on the design of current-mode instrumentation amplifiers for portable, implantable, and wearable electrocardiography and electroencephalography applications. To this end, a CMOS differential voltage second-generation current conveyor (DVCCII) based on a linear transconductor is presented. A new band-pass instrumentation amplifier, based on the designed DVCCII, is also implemented in this paper. The concept of the proposed differential voltage current conveyor and instrumentation amplifier is validated numerically and their predicted performance is presented. The simulation results of the presented circuits were tested for 0.18 μm TSMC CMOS technology in a post layout simulation level using the Cadence Virtuoso tool with a ±0.9 V power supply, and demonstrated that the designed DVCCII has a wide dynamic range of ±400 mV and ±0.85 mA and a power consumption of 148 μW. The layout of the DVCCII circuit occupies a total area of 0.378 μm2. It is shown that the designed DVCCII benefits from good linearity over a wide range of input signals and provides a low input impedance at terminal X. Two versions of the proposed band-pass instrumentation amplifier using pseudo resistances were designed with different specifications for two different applications, namely for EEG and ECG signals. Numerical analyses of both designs show proper outputs and frequency responses by eliminating the undesired artifact and DC component of the EEG and ECG input signals.

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Wang, Zhiqiang, Xiaosong Wang, and Yu Liu. "A Wideband Power Amplifier in 65 nm CMOS Covering 25.8 GHz–36.9 GHz by Staggering Tuned MCRs." Electronics 12, no. 17 (2023): 3566. http://dx.doi.org/10.3390/electronics12173566.

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Broadband millimeter-wave power amplifiers have attracted much attention and have wide applications for 5G communication, satellite communication, radar, sensing, etc. Yet, it is challenging to design a power amplifier with broadband small-signal gain and power performance simultaneously. In this study, a transformer-based symmetrical magnetically coupled resonator (MCR) matching network for broadband output matching and stagger-tuned MCRs are used to achieve both broadband small- and large-signal performance. Also, to enhance the gain for the power amplifier, a three-stage common-source pseudo-differential structure is adopted to mitigate the low-gain issue due to stagger tuning, and the shunt resistors aimed to decrease the Q factor of the MCRs. We used the in-phase two-way current combined with microstrip transmission lines to increase the output power. Designed in 65 nm bulky CMOS technology, the power amplifier presents a 3 dB small-signal gain bandwidth from 25.8 GHz to 36.9 GHz, indicating a peak gain of 25.87 dB at 30.5 GHz. The power amplifier demonstrates a 17.84 dBm saturated output power (Psat) at 31 GHz and a 24.37% peak power added efficiency (PAEmax) at 28 GHz. The power amplifier achieves a flat Psat of 17.44 ± 0.4 dBm, a PAEmax of 22.59 ± 1.78%, and an OP1dB of 13.78 ± 0.31 dBm from 26 GHz to 36 GHz.

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Zhou, Zhijun, Longbin Zhu, Rui Yang, et al. "A High CMRR Instrumentation Amplifier Employing Pseudo-Differential Inverter for Neural Signal Sensing." IEEE Sensors Journal 22, no. 1 (2022): 419–27. http://dx.doi.org/10.1109/jsen.2021.3130003.

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., D. S. Shylu. "DESIGN AND ANALYSIS OF LOW POWER PSEUDO DIFFERENTIAL CLASS-AB TELESCOPIC OPERATIONAL AMPLIFIER." International Journal of Research in Engineering and Technology 03, no. 19 (2014): 243–48. http://dx.doi.org/10.15623/ijret.2014.0319044.

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Kasipogula, Bhaskara Rao, and Gurumurthty Komanapalli. "A High Gain, High CMRR, Low Noise Bio-Potential amplifier based on Switched Capacitor Feedback Amplifier." Journal of Integrated Circuits and Systems 19, no. 2 (2024): 1–9. http://dx.doi.org/10.29292/jics.v19i2.813.

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This paper describes a biopotential amplifier based on an operational transconductance amplifier (OTA) de-signed specifically for bio-potential recordings to achieve high gain and low noise. The amplifier uses a differential architec-ture with chopper modulators and pseudo-resistors to achieve a Common Mode Rejection Ratio (CMRR) of over 100 dB. The design has several key features, including precise and high steady gain, large output swing, good load-driving capabilities, high input impedance (Zin), and a small footprint. The paper compares the proposed circuit with other bio-potential ampli-fiers in the literature, focusing on key parameters such as gain, input referred noise (IRN), CMRR, and Zin. The outcomes show that the suggested amplifier has a gain of 57.7 dB, an IRN of 0.839 µVrms, a CMRR of 108.13 dB, and consumes 8.854 µW at 0.8 V. The proposed bio-potential amplifier was implemented using a 180 nm CMOS technology node and was verified through simulations using the Cadence Virtuoso Spec-tre Simulator. The findings indicate that the proposed design is highly effective for recording bio-potentials in various appli-cations.

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Malz, Stefan, Bernd Heinemann, Rudolf Lachner та Ullrich R. Pfeiffer. "J-band amplifier design using gain-enhanced cascodes in 0.13 μm SiGe". International Journal of Microwave and Wireless Technologies 7, № 3-4 (2015): 339–47. http://dx.doi.org/10.1017/s175907871500080x.

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This paper presents two J-band amplifiers in different 0.13 μm SiGe technologies: a small signal amplifier (SSA) in a technology in which never before gain has been shown over 200 GHz; and a low noise amplifier (LNA) design for 230 GHz applications in an advanced SiGe HBT technology with higher fT/fmax, demonstrating the combination of high gain, low noise, and low power in a single amplifier. Both circuits consist of a four-stage pseudo-differential cascode topology. By employing series–series feedback at the single-stage level the small-signal gain is increased, enabling circuit operation at high-frequencies and with improved efficiency, while maintaining unconditional stability. The SSA was fabricated in a SiGe BiCMOS technology by Infineon with fT/fmax values of 250/360 GHz. It has measured 19.5 dB gain at 212 GHz with a 3 dB bandwidth of 21 GHz. It draws 65 mA from a 3.3 V supply. On the other hand, a LNA was designed in a SiGe BiCMOS technology by IHP with fT/fmaxof 300/450 GHz. The LNA has measured 22.5 dB gain at 233 GHz with a 3 dB bandwidth of 10 GHz and a simulated noise figure of 12.5 dB. The LNA draws only 17 mA from a 4 V supply. The design methodology, which led to these record results, is described in detail with the LNA as an example.

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PAIK, Daehwa, Masaya MIYAHARA, and Akira MATSUZAWA. "An Analysis on a Dynamic Amplifier and Calibration Methods for a Pseudo-Differential Dynamic Comparator." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E95-A, no. 2 (2012): 456–70. http://dx.doi.org/10.1587/transfun.e95.a.456.

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Nagari, A., and G. Nicollini. "A 3 V 10 MHz pseudo-differential SC bandpass filter using gain enhancement replica amplifier." IEEE Journal of Solid-State Circuits 33, no. 4 (1998): 626–30. http://dx.doi.org/10.1109/4.663568.

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Grace, Carl, Maurice Garcia-Sciveres, Timon Heim, and Amanda Krieger. "Low-Jitter Clock Receivers for Fast Timing Applications." Sensors 25, no. 7 (2025): 2284. https://doi.org/10.3390/s25072284.

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Precision timing is a key requirement for emerging 4D particle tracking, Positron Emission Tomography (PET), beam and fusion plasma diagnostics, and other systems. Time-to-Digital Converters (TDCs) are commonly used to provide digital estimates of the relative timing between events, but the jitter performance of a TDC can be no better than the performance of the circuits that acquire the pulses and deliver them to the TDC. Several clock receiver and distribution circuits were evaluated, and a differential amplifier with resistive loads driving a pseudo-differential clock distribution network, developed using design guidelines for radiation tolerance and cryogenic compatibility, was fabricated as part of three prototypes: an analog front-end testbed chip for high-precision timing pixel readout, a dedicated TDC evaluation chip, and a Low-Gain Avalanche Detector (LGAD) readout circuit. Based on TDC measurements of the prototypes, we infer that the jitter added by the clock receiver and distribution circuits is less than 2.25 ps-rms. This performance meets the requirements of many future precision timing systems. The clock receiver and on-chip pseudo-differential driver were fabricated in commercial 28-nm CMOS technology and occupy 2288 µm2.

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Kong, Dameng, and Quanzhen Duan. "A Pseudo-Differential Capacitive MEMS Accelerometer Analog Front-End Design." Journal of Physics: Conference Series 2477, no. 1 (2023): 012033. http://dx.doi.org/10.1088/1742-6596/2477/1/012033.

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Abstract Based on the current design and application of the chip and the research status at home and abroad, we proposed a silicon micro-accelerometer analog front-end integrated circuit with high resolution and wide capacitance application range by using SMIC 0.18μm CMOS technology. The circuit is composed of a capacitive readout circuit, a demodulator, and a low-pass filter. To detect the weak capacitive signal, the capacitor readout circuit of this paper adopts the continuous-time voltage mode charge amplifier structure and combines with the signal modulation technology and the optimization of the MOS transistor size to achieve low noise and high resolution. With the application of the signal modulation technology, the low-frequency capacitance sensor signal is shifted from 2-12 kHz to high-frequency 800 kHz. The signal modulation technology modulates the low-frequency capacitive sensor signal of 2~12 kHz at the high frequency of 800 kHz, and the signal is converted into voltage through the capacitive readout circuit. The simulation results show that the designed analog front-end circuit can convert the accelerometer capacitance signal with the frequency of 2~12 kHz, the dynamic capacitance peak is 0.108 pF, and the static capacitance is 10 pF into the expected voltage signal. In addition, the output noise can be as low as 556 nV/√Hz in the capacitive frequency range of the accelerometer, which meets the requirement of 2.5 aF capacitive resolution. Therefore, the silicon micro-accelerometer analog front-end circuit designed in this paper has the characteristics of a wide capacitor application range, low noise, and high resolution, and can be widely used.

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Meng-Hung Shen, Po-Hsiang Lan, and Po-Chiun Huang. "A 1-V CMOS Pseudo-Differential Amplifier With Multiple Common-Mode Stabilization and Frequency Compensation Loops." IEEE Transactions on Circuits and Systems II: Express Briefs 55, no. 5 (2008): 409–13. http://dx.doi.org/10.1109/tcsii.2007.914445.

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Suadet, Apirak, and Varakorn Kasemsuwan. "A CMOS inverter-based class-AB pseudo-differential amplifier with current-mode common-mode feedback (CMFB)." Analog Integrated Circuits and Signal Processing 74, no. 2 (2012): 387–98. http://dx.doi.org/10.1007/s10470-012-9970-0.

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Im, Saemin, and Sang-Gyu Park. "Analysis and Design of a Microphone Preamplifier for Mobile Applications." Electronics 10, no. 14 (2021): 1624. http://dx.doi.org/10.3390/electronics10141624.

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A design of an on-chip ac-coupling preamplifier for mobile applications is presented. A microphone preamplifier should have a large input impedance to mitigate the effective-gain reduction caused by the microphone’s non-zero output impedance. From a review of previously reported microphone preamplifier structures in terms of input impedance, feasibility of on-chip ac-coupling, and noise performance, we chose an inverting amplifier structure with capacitive feedback. In addition, to provide dc bias path, we used off-state MOSFET switches as pseudo-resistors of very large resistance in the giga-ohm range. The large resistance enables on-chip ac-coupling with sufficient noise performance. A fast start-up is achieved by turning-on the switch for a short period during the preamplifier start-up. The gain of the preamplifier can be programmed from 0 dB to 21 dB with 3 dB steps. A 2-stage pseudo-class-AB amplifier was adopted to reduce power consumption. The proposed preamplifier was implemented using a 28 nm CMOS process and achieves 107 dB dynamic range in a 20 kHz bandwidth under 0 dB gain setting and balanced differential input signal. The preamplifier dissipates a power of 270 μW with a 1.8 V supply.

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Girardi, Alessandro, Lucas Compassi-Severo, and Paulo César Comassetto de Aguirre. "Design Techniques for Ultra-Low Voltage Analog Circuits Using CMOS Characteristic Curves: a practical tutorial." Journal of Integrated Circuits and Systems 17, no. 1 (2022): 1–11. http://dx.doi.org/10.29292/jics.v17i1.573.

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The use of ultra-low-voltage (ULV) analog circuits for IoT applications, in which reduced power consumption is a mandatory specification, is becoming more and morean important design approach. Also, in many IoT applications, power is supplied with energy harvested from environmental sources. It is more efficient for the circuit to operate at a voltage level close to the provided by the energy harvester (between 0.3 and 0.6 V). To deal with this when using low-cost technology process nodes - 180-nm, for example, with |VT| ≈0.5V - it is necessary to apply specific design techniques that take advantage of reverse short channel effect, forward bulk bias-ing (FBB) or bulk-driven circuits. The use of low-VT transistors is also a good alternative when they are available inthe target process node. This paper presents a comprehensive scenery about modern CMOS ULV design techniques from the designer’s point of view, including design trade-offs and comments about design decisions. Four step-by-step design examples of ULV circuits are presented: a cross-coupled negative transconductor, a CMOS inverter as an analog amplifier, a pseudo-differential inverter-based amplifier, and a bulk-driven differential amplifier with active load. All designs require the biasing of transistors in moderate and weak inversion regions.The goal is to demonstrate that it is possible to design ULV analog circuits using standard-VT transistors with a supply voltage much lower than the nominal VDD.

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KRISHNAMURTHY, KARTHIKEYAN, JIAN XU, XIAOQIANG SHOU, et al. "40 Gb/s TDM SYSTEM TRANSCEIVER PROTOTYPE IN InP HBT TECHNOLOGY." International Journal of High Speed Electronics and Systems 15, no. 03 (2005): 643–65. http://dx.doi.org/10.1142/s0129156405003375.

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A time-division-multiplexing (TDM) system transceiver with 4–channel 10 Gb/s interfaces to achieve 40 Gb/s non-return to zero (NRZ) transmission is presented. The front-end components are implemented in an indium phosphide double hetero-junction bipolar transistor (InP DHBT) technology. They include a 4:1 multiplexer with a voltage controlled oscillator and clock multiplication unit, modulator drivers for electro-absorption and differential lithium-niobate modulators, trans-impedance amplifier, limiting amplifier and 1:4 demultiplexer with clock and data recovery circuit. The transceiver was used to teat optical transmission over a 2.26 km link with a 40 Gb/s, 231-1 pseudo-random bit sequence (PRBS) data. The transmitter achieves better than 12.9 dB extinction ratio, 1 ps added root mean square (RMS) jitter and 4 dBm output power. Without any optical amplification the receiver achieves -9.1 dBm back to back sensitivity at a bit error rate (BER) of 10-12 and a high dynamic range of 12.5 dBm.

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Eghtesadi, Minoo, Mohammad Reza Mosavi, and Egidio Ragonese. "A Pseudo-Differential LNA with Noise Improvement Techniques for Concurrent Multi-Band GNSS Applications." Electronics 13, no. 14 (2024): 2805. http://dx.doi.org/10.3390/electronics13142805.

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A low-noise amplifier (LNA) design with the operation of concurrent dual-band for Global Navigation Satellite System (GNSS) receivers with single channel is presented in this work. This LNA structure has an inductively degenerated cascode architecture and is pseudo-differential, operating at two frequencies simultaneously (1.2 GHz and 1.57 GHz). Two noise reduction/cancellation techniques, using load capacitor and feedforward path, respectively, are proposed resulting in an excellent improvement in the noise figure (NF). The input matching circuit uses both series and parallel resonant components to enable concurrency. The adopted pseudo-differential structure results in input balun elimination. Inductively degenerated cascode topology provides both input impedance and optimum noise impedance matching. The soundness of the proposed approach has been demonstrated in a 0.18-µm CMOS technology by TSMC. Simulation results show that at 1.2 GHz and 1.57 GHz the LNA achieves −13 dB and −11 dB of input matching, 24.6 dB and 24.7 dB of gain, 1.47 dB and 1.43 dB of NF, respectively. The input-referred 1-dB compression point (IP1dB) is around −16 dBm, while the input-referred third-order intercept point (IIP3) achieves −2.2 dBm at 1.2 GHz and −0.6 dBm at 1.57 GHz. The LNA draws about 13 mA from a 1.8-V supply voltage.

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Yin, Yue, Xinbing Zhang, Ziting Feng, et al. "An Ultra-Low-Voltage Transconductance Stable and Enhanced OTA for ECG Signal Processing." Micromachines 15, no. 9 (2024): 1108. http://dx.doi.org/10.3390/mi15091108.

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In this paper, a rail-to-rail transconductance stable and enhanced ultra-low-voltage operational transconductance amplifier (OTA) is proposed for electrocardiogram (ECG) signal processing. The variation regularity of the bulk transconductance of pMOS and nMOS transistors and the cancellation mechanism of two types of transconductance variations are revealed. On this basis, a transconductance stabilization and enhancement technique is proposed. By using the “current-reused and transconductance-boosted complementary bulk-driven pseudo-differential pairs” structure, the bulk-driven pseudo-differential pair during the input common-mode range (ICMR) is stabilized and enhanced. The proposed OTA based on this technology is simulated using the TSMC 0.18 μm process in a Cadence environment. The proposed OTA consumes a power below 30 nW at a 0.4 V voltage supply with a DC gain of 54.9 dB and a gain-bandwidth product (GBW) of 14.4 kHz under a 15 pF capacitance load. The OTA has a high small signal figure-of-merit (FoM) of 7410 and excellent common-mode voltage (VCM) stability, with a transconductance variation of about 1.35%. Based on a current-scaling version of the proposed OTA, an OTA-C low-pass filter (LPF) for ECG signal processing with VCM stability is built and simulated. With a −3 dB bandwidth of 250 Hz and a power consumption of 20.23 nW, the filter achieves a FoM of 3.41 × 10−13, demonstrating good performance.

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Eghtesadi, Minoo, Gianluca Giustolisi, Andrea Ballo, Salvatore Pennisi, and Egidio Ragonese. "A 5 mW 28 nm CMOS Low-Noise Amplifier with Transformer-Based Electrostatic Discharge Protection for 60 GHz Applications." Electronics 13, no. 21 (2024): 4285. http://dx.doi.org/10.3390/electronics13214285.

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This paper presents a low-power 60 GHz low-noise amplifier (LNA) designed for Gbit/s applications using 28 nm CMOS technology. The LNA exploits a single-stage pseudo-differential architecture with integrated input transformer for both electrostatic discharge (ESD) protection and simultaneous noise/impedance matching. An effective power-constrained design strategy is adopted to pursue the lowest current consumption at the minimum noise figure (NF), with the best tradeoff between gain and frequency bandwidth. The LNA, which has been designed to drive an on–off keying (OOK) demodulator, is operated at a supply voltage as low as 0.9 V and achieves a voltage gain of about 21 dB with a 3 dB bandwidth of 2 GHz around 60 GHz. Thanks to the proper impedance transformation at the 60 GHz input, the amplifier exhibits an NF of 6.3 dB, also including the input transformer loss with a very low power consumption of about 5 mW. The adoption of a single-stage topology also allows an excellent input 1 dB compression point (IP1dB) of −4.7 dBm. The input transformer guarantees up to 2 kV human body model (HBM) ESD protection.

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Li, Zhiyu, Xueqian Shang, Haigang Feng, and Xinpeng Xing. "A Power-Efficient 50 MHz-BW 76.8 dB Signal-to-Noise-and-Distortion Ratio Continuous-Time 2-2 MASH Delta-Sigma Analog-to-Digital Converter with Digital Calibration." Journal of Low Power Electronics and Applications 15, no. 2 (2025): 20. https://doi.org/10.3390/jlpea15020020.

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Continuous-time Sigma-Delta (CTSD) Analog-to-Digital Converter (ADC) is widely used in wireless receivers due to its built-in anti-aliasing and resistive input. In order to achieve a wide bandwidth while ensuring low power consumption, this paper proposes a CT 2-2 Multi-stAge Noise-sHaping (MASH) ADC for wireless communication. In order to reduce power consumption, the loop filter adopts a feedforward structure, and the operational amplifier uses complementary differential input pairs and feedforward compensation. The pseudo-random sequence injection and Least Mean Squares (LMS) algorithm are adopted to calibrate the digital noise cancelation filter to match the analog transfer function. The simulation results obtained in 40 nm CMOS show that the presented 2-2 CT MASH ADC achieves a 76.8 dB signal-to-noise-and-distortion ratio (SNDR) at a 50MHz bandwidth (BW) with a 1.6 GHz sampling rate and consumes 29.7 mW power under 1.2/0.9 V supply, corresponding to an excellent figure of merit (FoM) of 169.1 dB.

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Llimos Muntal, Pere, and Ivan Harald Holger Jorgensen. "34.3 fJ/conv.-step 8-MHz Bandwidth Fourth-Order Pseudo-Differential Ring-Amplifier-Based Continuous-Time Delta–Sigma ADC in 65 nm." IEEE Solid-State Circuits Letters 1, no. 10 (2018): 198–201. http://dx.doi.org/10.1109/lssc.2019.2910468.

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Corbacho, Israel, Juan M. Carrillo, José L. Ausín, Miguel Á. Domínguez, Raquel Pérez-Aloe, and Juan Francisco Duque-Carrillo. "Compact CMOS Wideband Instrumentation Amplifiers for Multi-Frequency Bioimpedance Measurement: A Design Procedure." Electronics 11, no. 11 (2022): 1668. http://dx.doi.org/10.3390/electronics11111668.

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The design of an instrumentation amplifier (IA), based on indirect current feedback and suited to electrical bioimpedance spectroscopy, is presented. The IA consists of two transconductors and a summing stage, featuring a single-stage configuration process that allows the maximum achievable bandwidth to be extended. The transconductors are linearized by means of resistive source degeneration, whereas the use of super source followers allows a reduction in the values of the source degeneration resistors. This fact leads to a decrease in the overall noise and the silicon area, thus resulting in a compact implementation. A thorough analysis of the proposed solution, accompanied by a design procedure and verified by means of electrical simulations, is also provided. Two versions of the IA, i.e., a single-ended (SE) and a pseudo-differential (PD) structure, were designed and fabricated using 180 nm CMOS technology to operate with a 1.8 V supply. The experimental results, including a BW of 5.2 MHz/8.0 MHz, a CMRR higher than 72 dB/80 dB, a DC current consumption of 139.0 μA/219.3 μA and a silicon area equal to 0.0173 mm2/0.0291 mm2 for the SE/PD implementation, validate the suitability of the approach.

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Choi, Bo-Hun. "A Time-Differential BOCDA Sensor Measurement System Applied to a 1 km Long SMF Using a Semiconductor Optical Amplifier as a Pump Chopper." Sensors 24, no. 8 (2024): 2417. http://dx.doi.org/10.3390/s24082417.

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A time-differential (TD) Brillouin optical correlation domain analysis (BOCDA) sensor system was applied to measure the Brillouin gain spectrum of a 1 km long sensing optical fiber. The optical delay line used in all BOCDA measurement systems was eliminated in the TD-BOCDA system by using a bit-delayed modulation relationship between the probe and pump lightwaves. These lightwaves were phase modulated using 216-1 pseudo-random binary sequence codes at 5 Gbps. A 2 cm dispersion-shifted fiber placed at the end of the 1 km optical fiber was distinctly identified by the Brillouin frequency extracted from the Brillouin gain spectrum measurement. To investigate the measurement stability of the TD-BOCDA system, experiments were conducted under two different pumping conditions. A semiconductor optical amplifier (SOA) and an intensity modulator (MOD) were compared for the pump chopper used in the TD-BOCDA system to detect the extinction ratio of the pump and the resulting noise in the Brillouin gain measurement. The stability of the Brillouin frequency measurement from the Brillouin gain spectrum in the TD-BOCDA system was investigated by increasing the average value of the measurement using either the SOA or MOD. The repeated-measurement deviation of the system with the SOA was only half of the deviation observed in the system with the MOD. The performance of TD-BOCDA is equivalent to or better than that of conventional BOCDAs in terms of measurement reliability. Moreover, TD-BOCDA is free from the drawbacks of traditional BOCDA, which uses time-delayed fibers and varies the bit rates.

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Rekha, S., and T. Laxminidhi. "Common Mode Feedback Circuits for Low Voltage Fully-Differential Amplifiers." Journal of Circuits, Systems and Computers 25, no. 10 (2016): 1650124. http://dx.doi.org/10.1142/s0218126616501243.

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Continuous time common mode feedback (CMFB) circuits for low voltage, low power applications are proposed. Four circuits are proposed for gate/bulk-driven pseudo-differential transconductors operating on sub-1-V power supply. The circuits are validated for a bulk-driven pseudo-differential transconductor operating on 0.5[Formula: see text]V in 0.18[Formula: see text][Formula: see text]m standard CMOS technology. Simulation results reveal that the proposed CMFB circuits offer power efficient solution for setting the output common mode of the transconductors. They also load the transconductor capacitively offering capacitance of about 1[Formula: see text]fF to tens of femto farads.

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Liao, Xiaofei, Dixian Zhao, and Xiaohu You. "An E-band CMOS frequency quadrupler with 1.7-dBm output power and 45-dB fundamental suppression." Journal of Semiconductors 43, no. 9 (2022): 092401. http://dx.doi.org/10.1088/1674-4926/43/9/092401.

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Abstract This paper presents an E-band frequency quadrupler in 40-nm CMOS technology. The circuit employs two push–push frequency doublers and two single-stage neutralized amplifiers. The pseudo-differential class-B biased cascode topology is adopted for the frequency doubler, which improves the reverse isolation and the conversion gain. Neutralization technique is applied to increase the stability and the power gain of the amplifiers simultaneously. The stacked transformers are used for single-ended-to-differential transformation as well as output bandpass filtering. The output bandpass filter enhances the 4th-harmonic output power, while rejecting the undesired harmonics, especially the 2nd harmonic. The core chip is 0.23 mm2 in size and consumes 34 mW. The measured 4th harmonic achieves a maximum output power of 1.7 dBm with a peak conversion gain of 3.4 dB at 76 GHz. The fundamental and 2nd-harmonic suppressions of over 45 and 20 dB are achieved for the spectrum from 74 to 82 GHz, respectively.

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Centurelli, Francesco, Riccardo Della Sala, and Giuseppe Scotti. "A Standard-Cell-Based CMFB for Fully Synthesizable OTAs." Journal of Low Power Electronics and Applications 12, no. 2 (2022): 27. http://dx.doi.org/10.3390/jlpea12020027.

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In this paper, we propose a fully standard-cell-based common-mode feedback (CMFB) loop with an explicit voltage reference to improve the CMRR of pseudo-differential standard-cell-based amplifiers and to stabilize the dc output voltage. This latter feature allows robust biasing of operational transconductance amplifiers (OTAs) based on a cascade of such stages. A detailed analysis of the CMFB is reported to both provide insight into circuit behavior and to derive useful design guidelines. The proposed CMFB is then exploited to build a fully standard-cell OTA suitable for automatic place and route. Simulation results referring to the standard-cell library of a commercial 130 nm CMOS process illustrated a differential gain of 28.3 dB with a gain-bandwidth product of 15.4 MHz when driving a 1.5 pF load capacitance. The OTA exhibits good robustness under PVT and mismatch variations and achieves state-of-the-art FOMs also thanks to the limited area footprint.

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Cao, Zhiheng, Tongyu Song, and Shouli Yan. "A 14 mW 2.5 MS/s 14 bit $\Sigma\Delta$ Modulator Using Split-Path Pseudo-Differential Amplifiers." IEEE Journal of Solid-State Circuits 42, no. 10 (2007): 2169–79. http://dx.doi.org/10.1109/jssc.2007.905241.

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Tang, Hui, Jian Gao, Xin Chen, Lan Yu Zhang, and Zhao He Zeng. "Design and Analysis of a Planar Piezo-Actuated Nanopositioner with Millimeter Scale Stroke." Key Engineering Materials 679 (February 2016): 143–48. http://dx.doi.org/10.4028/www.scientific.net/kem.679.143.

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In recent years, Fast Tool Servo (FTS) mechanism in precision manufacturing equipment emerges as a promising application for the piezo-actuated flexible nanopositioner. A flexible nanopositioner with large stroke, high bandwidth, high precision and multi-Degrees-of-Freedom (multi-DOFs) is really desired for this application. In order to meet this requirement, a novel 2-DOF flexible nanopositioner consists of two pairs of differential lever displacement amplifiers (DLDA) is proposed in this paper first, also, kinetostatics modeling is conducted by using the Pseudo-Rigid Body (PRB) method. After a series of mechanism optimal designs, the performance of the designed nanopositioner is verified by using the Finite Element Analysis (FEA) method. A piezoelectric (PZT) actuator with 90 µm is selected in this simulation, the experimental results indicate that the mechanism workspace can achieve around 2.1×2.1 mm2, the bandwidth can reach up to around 136 Hz, while the cross-coupling is also kept with 1%. All the results consistently prove the proposed device possesses satisfactory performance for fulfilling the practical precision manufacturing tasks.

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STEPANENKO, Dmitry A., and Ksenija A. BUNCHUK. "MATHEMATICAL MODELLING OF VIBRATIONS OF NON-UNIFORM RING-SHAPED ULTRASONIC WAVEGUIDES." Mechanics of Machines, Mechanisms and Materials 3, no. 56 (2021): 90–96. http://dx.doi.org/10.46864/1995-0470-2021-3-56-90-96.

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The article describes technique for modelling of ultrasonic vibrations amplifiers, which are implemented in the form of non-uniform ring-shaped waveguides, based on application of harmonic balance method. Bending vibrations of the waveguide are described by means of non-uniform integral and differential equations equivalent to Euler–Bernoulli equations in order to simplify calculation of amplitude-frequency characteristics of vibrations, particularly, to exclude the need of working with singular matrices. Using harmonic balance method, equations of vibrations are reduced to overdetermined non-uniform linear system of algebraic equations, which least-squares solution is determined by means of pseudo-inverse matrix. On the basis of analysis of numerical example possibility of existence of variable-sign and constant-sign vibration modes of the waveguide is shown and it is determined that for realization of amplifying function it is necessary to use waveguide at constant-sign vibration mode. The constant-sign vibration modes are combinations of bending defor-mation and extensional deformation of central line of the waveguide and they are detected due to accounting extensibility of the central line in equations of vibrations. Validity of the obtained results is confirmed by comparing them to the results of modelling by means of finite element method.

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Frech, Michael, and John Hubbert. "Monitoring the differential reflectivity and receiver calibration of the German polarimetric weather radar network." Atmospheric Measurement Techniques 13, no. 3 (2020): 1051–69. http://dx.doi.org/10.5194/amt-13-1051-2020.

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Abstract. It is a challenge to calibrate differential reflectivity ZDR to within 0.1–0.2 dB uncertainty for dual-polarization weather radars that operate 24∕7 throughout the year. During operations, a temperature sensitivity of ZDR larger than 0.2 dB over a temperature range of 10 ∘C has been noted. In order to understand the source of the observed ZDR temperature sensitivity, over 2000 dedicated solar box scans, two-dimensional scans of 5∘ azimuth by 8∘ elevation that encompass the solar disk, were made in 2018 from which horizontal (H) and vertical (V) pseudo antenna patterns are calculated. This assessment is carried out using data from the Hohenpeißenberg research radar which is identical to the 17 operational radar systems of the German Meteorological Service (Deutscher Wetterdienst, DWD). ZDR antenna patterns are calculated from the H and V patterns which reveal that the ZDR bias is temperature dependent, changing about 0.2 dB over a 12 ∘C temperature range. One-point-calibration results, where a test signal is injected into the antenna cross-guide coupler outside the receiver box or into the low-noise amplifiers (LNAs), reveal only a very weak differential temperature sensitivity (<0.02 dB) of the receiver electronics. Thus, the observed temperature sensitivity is attributed to the antenna assembly. This is in agreement with the NCAR (National Center for Atmospheric Research) S-Pol (S-band polarimetric radar) system, where the primary ZDR temperature sensitivity is also related to the antenna assembly (Hubbert, 2017). Solar power measurements from a Canadian calibration observatory are used to compute the antenna gain and to validate the results with the operational DWD monitoring results. The derived gain values agree very well with the gain estimate of the antenna manufacturer. The antenna gain shows a quasi-linear dependence on temperature with different slopes for the H and V channels. There is a 0.6 dB decrease in gain for a 10 ∘C temperature increase, which directly relates to a bias in the radar reflectivity factor Z which has not been not accounted for previously. The operational methods used to monitor and calibrate ZDR for the polarimetric DWD C-band weather radar network are discussed. The prime sources for calibrating and monitoring ZDR are birdbath scans, which are executed every 5 min, and the analysis of solar spikes that occur during operational scanning. Using an automated ZDR calibration procedure on a diurnal timescale, we are able to keep ZDR bias within the target uncertainty of ±0.1 dB. This is demonstrated for data from the DWD radar network comprising over 87 years of cumulative dual-polarization radar operations.

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Rickett, Laura, and Pratim Datta. "Beauty-Contests in the Age of Financialization: Information Activism and Retail Investor Behavior." Journal of Information Technology 33, no. 1 (2018): 31–49. http://dx.doi.org/10.1057/s41265-016-0026-2.

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Keynes (The General Theory of Employment, Interest and Money, Harcourt Brace and Co., New York, 1936) had rightfully argued that picking stocks is akin to a beauty contest. The chances of winning are amplified if one's choice matches the likelihood of the panel's choice. In this era of financialization, where profit-making has shifted to speculative sways rather than fundamental trade and commodity production measures (Krippner, Socio-Econ Rev 3(2): 173-208, 2005), similar beauty contests have become even more acute. Online, real-time media channels along with pervasive investments applications have ushered in unprecedented online financial information and retail investor interest, ranging from dealing in penny stocks to sentiment-based trading. More than information sources, similar investment sites compete to recommend investment directions and strategies, not driven by strict fundamentals used by “arbitrageurs” or rational speculators but on pseudo-signals proffered by various information investment channels with varying degrees of credibility. This behavior, referred to herein as information activism, concomitantly adds a sociopsychological dimension to the concept of financialization (Lagoarde-Segot, Int Rev Financial Anal 2016) – wherein technology-driven information reach and range contribute to financial dominance of financial actors and practices. Using information activism as a lens, this research empirically evidences the extent to which information activism affects retail investor behavior under various market conditions. This study examines the differential effects of two primary, albeit reputable, sources of information activism: an investment news channel (CNBC – Mad Money) and an online financial blog (SeekingAlpha), and the effect on investor behavior during the 2008 financial crisis. In identifying the specific downstream effects of information activism on capital markets and investor behavior, factors related to investor behavior, such as trading volume and price reaction, are analyzed surrounding information activism events. Results indicate that retail investors appear to rely on online information activists during uncertain economic conditions. Findings denote that abnormal returns are associated with information activism during uncertain economic conditions and for buy recommendations when information asymmetry is high. Abnormal trading volume is also associated with information activism during economic uncertainty and with buy recommendations when information asymmetry is high particularly for stocks exchanges where unsophisticated investors tend to trade more heavily.

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Gil-Torralvo, Ana, Marta Benavent, Maria A. Dominguez-Cejudo, et al. "Abstract P2-07-08: Identification of UGT2B15 as a potential biomarker in response to neoadjuvant therapy in HER2+ breast cancer." Cancer Research 82, no. 4_Supplement (2022): P2–07–08—P2–07–08. http://dx.doi.org/10.1158/1538-7445.sabcs21-p2-07-08.

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Abstract INTRODUCTION. In response to neoadjuvant therapy, pathological complete response (pCR; lack of residual disease in breast and lymph nodes), has been proposed as a prognostic marker for long-term clinical outcomes, such as disease-free (DFS) and overall survival (OS), in human epidermal growth factor receptor 2 (HER2)-positive and triple-negative breast cancer. In clinical practice, recognizing those patients likely to achieve such responses proves challenging to the oncologist, making the identification of new useful biomarkers vital. Here, we searched for potential biomarkers that anticipate pCR to neoadjuvant therapy in HER2-positive, hormone receptor-negative breast cancer tissue samples. METHODS. Patients with early and locally advanced breast cancer, diagnose as HER2-positive, hormone receptor-negative by immunohistochemistry (IHC) at the time of neoadjuvant treatment were included. All samples were collected from biobank at Hospital Universitario Virgen del Rocio. We defined two groups: responder (R) and non-responder (nR) and analyzed 18 samples in the discovery cohort (10 R vs 8 nR) and 12 samples in the validation cohort (6 R vs 6 nR).The RNA for the study was extracted from tissue fixed in formaldehyde and paraffin embedded. The extraction of the RNA was carried out using the commercial kit RecoverAll Total Nucleic Acid Isolation Kit from Ambion (Applied Biosystems). RNA was quantified by Qubit RNA HS Assay Kit (Molecular Probes). Before hybridization, RNA for the discovery cohort was amplified using GeneChip WT Pico Kit (Applied Biosystems).We analyzed transcript expression using ClariomD array. Differential expression between the two groups was analyzed using in-house R scripts (version 3.5.1). Data were corrected and normalized using Robust Multi-array Average method. Expression was summarized at gene level using the corresponding annotation for ClariomD BrainArray. Gene validation was performed by qPCR using TaqMan Gene Expression Assay (Applied Biosystem). RESULTS. Considering a fold change ≥ 2 and an adjusted p-value &lt;0.05 as statistically significant, we found 53 differentially expressed transcripts: 51 downregulated transcripts (lower expression in R) and 2 upregulated transcripts (higher expression in R). The RNA was annotated as non-coding RNAs in over 25% of the cases. The distribution of such molecules was as followed: 8 long non-coding RNAs (56%); 3 non-coding RNAs (22%) and 3 pseudo-genes (22%). Regarding protein coding transcripts, gene ontology analysis revealed an enrichment of terms associated to metabolic processes and response to toxic substance.As expected, ERBB2, which encodes for HER2, appeared at the top of the list with a patent upregulation of expression in the responder group when compared with non-responder patients. To validate the data, we used qPCR and ERBB2 expression as a positive control of the results (p-value=0.0380). Our data showed a significant downregulation of UDP-glucuronosyltransferase 2B15 (UGT2B15; p-value= 0.0173), which encodes a glycosyltransferase, involved in the metabolism and elimination of toxic compounds. CONCLUSIONS. The ability to predict which patients will benefit from neoadjuvant therapy and achieve a pCR would allow for improved patient stratification and more personalized medicine. Here, we identified a set of transcript differentially expressed (FC&gt;2; adjusted p-value&lt;0.05) in patients that achieve pCR (R) when compared with tissue samples with residual disease (nR). We usedERBB2 expression as a positive control to validate the data and show that UGT2B15 is consistently upregulated in non-responder patients. Further work is needed to elucidate UGT2B15 role, but it is worth mentioning that an increased rate of glucuronidation has been associated with a loss of potency for the target drugs. Citation Format: Ana Gil-Torralvo, Marta Benavent, Maria A Dominguez-Cejudo, Alejandro Falcon, Begoña Vieites, Sonia Molina-Pinela, Manuel Ruiz, Álvaro Montaño, Rosario Gónzalez, Julia Martínez, Juan de la Haba, Antonio Rodríguez, Maria I Queipo, Begoña Jímenez, Javier Salvador-Bofill. Identification of UGT2B15 as a potential biomarker in response to neoadjuvant therapy in HER2+ breast cancer [abstract]. In: Proceedings of the 2021 San Antonio Breast Cancer Symposium; 2021 Dec 7-10; San Antonio, TX. Philadelphia (PA): AACR; Cancer Res 2022;82(4 Suppl):Abstract nr P2-07-08.

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Babaeinik, Majid, Massoud Dousti, and Mohammad Bagher Tavakoli. "Analysis and Design of High Gain-Bandwidth CMOS Distributed Amplifier Utilizing a Cascaded Pseudo Differential Distributed Amplifier." Journal of Circuits, Systems and Computers, July 21, 2020, 2150005. http://dx.doi.org/10.1142/s0218126621500055.

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Distributed amplifiers (DAs) are one of the most important and common wideband amplifiers that can use various arrangements in their gain cell structure. One of the gain cells that can be effective in increasing the bandwidth of a distributed amplifier is the pseudo-differential amplifier (PDA). Although pseudo-differential distributed amplifiers (PDDAs) have a wide bandwidth and amplify DC, they have a small voltage gain. In this paper, various circuits with the same power and chip area are proposed to improve the performance of PDDAs. For evaluating and comparing the performance of the proposed circuits, they are implemented in 0.18[Formula: see text][Formula: see text]m RF-CMOS technology. The simulation results reveal that two cascaded PDDAs with three stages have a better performance than three cascaded PDDAs with two stages; in two cascaded PDDAs with three stages, a gain of 9[Formula: see text]dB can be achieved for a bandwidth of 50[Formula: see text]GHz in 0.18[Formula: see text][Formula: see text]m RF-CMOS technology. In this amplifier, parameters S[Formula: see text], S[Formula: see text] and S[Formula: see text] are [Formula: see text]12, [Formula: see text]10 and [Formula: see text]18 dB, respectively; noise figure is 4.3–5.8[Formula: see text]dB, and [Formula: see text] is +4[Formula: see text]dBm. This amplifier consumes 220[Formula: see text]mW power and has a chip area of 0.58[Formula: see text]mm2.

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Zhou, Zhijun, Keping Wang, Longbin Zhu, et al. "A Differential Difference Amplifier Employing Pseudo-Differential CMFB for Neural Signal Recording Applications." IEEE Transactions on Circuits and Systems II: Express Briefs, 2022, 1. http://dx.doi.org/10.1109/tcsii.2022.3223874.

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Manfredini, Giuseppe, Alessandro Catania, Lorenzo Benvenuti, Mattia Cicalini, Massimo Piotto, and Paolo Bruschi. "Ultra-Low-Voltage Inverter-Based Amplifier with Novel Common-Mode Stabilization Loop." June 19, 2020. https://doi.org/10.3390/electronics9061019.

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Lee, Calvin Yoji, Praveen Kumar Venkatachala, Ahmed ElShater, and Un-Ku Moon. "A Pseudo-Pseudo-Differential ADC Achieving 105dB SNDR in 10kHz Bandwidth Using Ring Amplifier Based Integrators." IEEE Transactions on Circuits and Systems II: Express Briefs, 2021, 1. http://dx.doi.org/10.1109/tcsii.2021.3060011.

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Manouras, Vasileios, and Ioannis Papananos. "A Wideband High-Gain Power Amplifier Operating in the D Band." November 8, 2022. https://doi.org/10.1109/VLSI-SoC54400.2022.9939613.

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In this paper the design, analysis and implementation of a 3-stage, broadband power amplifier (BPA), is presented. The device is suitable for medium-distance wireless and wireline gigabit communication in the D-band (110 – 170 GHz). A pseudo-differential cascode topology is adopted for each stage leading to optimized broadband performance. The PA is integrated in a 0.13 μm SiGe BiCMOS technology with f T /f max = 250/370 GHz, achieving a saturation output power P sat > 9 dBm and a maximum large-signal power gain G P > 29.5 dB, over the entire D-band. The chip size is 1.150 × 0.467 mm <sup>2</sup> including all pads.

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Kuai, Yang, Liwei Yan, Mingjie Liu, and Fei Yang. "A 31–36 GHz low noise‐variable gain amplifier with less than 0.37° RMS phase error and 0.4 dB gain step in 65‐nm CMOS." Microwave and Optical Technology Letters 66, no. 7 (2024). http://dx.doi.org/10.1002/mop.34229.

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AbstractThis article realizes a low noise‐variable gain amplifier (LN‐VGA) operating at the frequency range of 31–36 GHz. The LN‐VGA consists of two amplifier stages and a gain control stage. To achieve low noise and high gain, the two amplifier stages were implemented using a single‐ended inductive source‐degeneration cascaded with pseudo‐differential neutralization capacitors. Moreover, a symmetrical splitting cascode unit topology is proposed in the gain control stage to improve the precision of phase variation and gain step within the 3‐dB bandwidth. The LN‐VGA was fabricated using a 65‐nm CMOS process, demonstrating a gain control range of 15.2–21.2 dB with less than 2° phase variation and a minimum noise figure of 5.6 dB. The measured results show less than 0.37° rms phase error and a 0.4 dB gain step at 31–36 GHz. The chip occupies an area of 0.81 × 0.51 mm2 excluding pads and consumes 27 mW of power.

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Rusanen, Jere, Alok Sethi, Nuutti Tervo, et al. "Ka-band stacked and pseudo-differential orthogonal load-modulated balanced power amplifier in 22 nm CMOS FDSOI." International Journal of Microwave and Wireless Technologies, October 11, 2023, 1–8. http://dx.doi.org/10.1017/s1759078723001137.

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Abstract This paper presents an integrated power amplifier (PA) following the orthogonal load-modulated balanced amplifier (OLMBA) topology. The fixed-phase prototype in this paper is implemented with 22 nm complementary metal oxide semiconductor (CMOS) fully depleted silicon-on-insulator (FDSOI) process. The proposed PA operates at 26 GHz frequency range, where it achieves 19.5 dBm output power, 16.6 dB gain, 15.7% power added efficiency, and 18.3 dBm output 1-dB compression point ( $P_{\rm 1\,dB}$ ). The PA is also tested with high dynamic range modulated signals, and it achieves, respectively, 11.4 dBm and 4.9 dBm average output power (Pavg) with 100 MHz and 400 MHz 64-QAM third-generation partnership project/new radio frequency range 2 signals, and 14 dBm Pavg with 0.6 Gb/s (120 MHz) single carrier 64-QAM signal, measured at 26 GHz and using −28 dBc adjacent channel leakage ratio and −21.9 dB (8%) error vector magnitude as threshold values. The proposed OLMBA is also compared to a stand-alone quadrature-balanced PA. Modulated measurements show that the stand-alone quadrature-balanced PA has better linearity in deep back-off, but the OLMBA has better efficiency.

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Shabanzadeh, Negar, Rehman Akbar, Aarno Pärssinen, and Timo Rahkonen. "Origins and minimization of intermodulation distortion in a pseudo-differential CMOS beamforming receiver." Analog Integrated Circuits and Signal Processing, July 25, 2021. http://dx.doi.org/10.1007/s10470-021-01916-w.

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AbstractThis paper studies how nonlinear distortion is generated in the combination of an inverter-based low-noise amplifier and a passive mixer. The dominant nonlinearity appears to be the quadratic $$V_{gs}V_{ds}$$ V gs V ds mixing term in the passive mixer that first causes low-frequency IM2 and then upconverts it to IM3. Adding a common-mode feedback (CMFB) cancels the IM2 in a pseudo-differential structure, and hence also reduces the IM3 caused by the cascaded second order nonlinearities significantly. The effect of CMFB gain, bandwidth and linearity were analyzed, and it is concluded that from the linearity point of view, the feedback circuit does not have to be very wideband since the dominant distortion products originate from baseband. Finally, the paper takes a look at the spurious tones rising in the mixing, and how to extend the analysis to include the actual frequency translation effect.

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