Academic literature on the topic 'Pulse modulation'

The phase angle control of the Two-Level Sinusoidal Pulse Width Modulation (SPWM) strategy has been studied in Part I of this thesis, and applied to a new voltage-source type PWM High Voltage Direct Current (HVDC) transmission system. The PWM-HVDC station exercises direct control over the voltage phase angle, the amplitude and the frequency at the ac terminals using the phase angle lock loop (PLL) control of the SPWM. The parallel connection of multi-terminal PWM-HVDC stations can be achieved through simple local feedback control. The feasibility studies for the system, based on laboratory experiments and numerical analysis, are reported in the thesis.<br>In Part II of the thesis, the Three-Level SPWM technique has been studied and applied to the controls of a 3-chase, 6-valve, current-source PWM rectifier. A new Dynamic Three-Level SPWM strategy together with its Decoupler Pre-Processor has been proposed. The strategy enables each of three phase currents of the converter to be controlled independently and linearly, so that the dynamic feedback can be channelled. The Pole Placement control method has been implemented successfully, using a real-time digital control scheme. The scheme also succeeds in active filtering. The experimental results are obtained from a 1-KVA size laboratory model with a real-time controller using three TMS320C25 DSPs. The three DSPs operating in parallel are necessary to compute the feedback algorithms with minimum delays so as to ensure sufficient frequency bandwidth.

With the requirement to store and transmit information efficiently, an ever increasing number of uses of data compression techniques have been generated in diverse fields such as television, surveillance, remote sensing, medical processing, office automation, and robotics. Rapid increases in processing capabilities and the speed of complex integrated circuits make data compression techniques a prime candidate for application in the areas mentioned above. This report addresses, from a theoretical viewpoint, three major data compression techniques, Pixel Coding, Predictive Coding, and Transform Coding. It begins with a project description and continues with data compression techniques, focusing on Differential Pulse Code Modulation.

This work presents the performance analysis of the offset pulse position modulation (PPM) scheme using graded-index plastic optical fibre with a Gaussian impulse response. The aim of this analysis is to predict how sensitivity, error, number of required photons, threshold voltage, and the effect of inter-symbol interference will change with the change in the number of data bits encoded at a rate of 1 Gbit/s. An information theory analysis is presented in detail and also the band-utilization efficiency is determined. Results are compared to equivalent digital PPM and multiple PPM schemes and it is also shown that offset PPM gives an advantage over on-off keying (OOK). Bit error rate (BER) analysis has been presented numerically. The errors due to different coding techniques are compared. It has also been shown that offset pulse position modulation is more power efficient than multiple pulse position modulation. The spectral analysis of offset pulse position modulation coding scheme has been carried out. For an offset PPM sequence the spectral characteristics is presented both theoretically and numerically. The results show strong frequency components at the frame rate and, if return-to-zero pulses are used, the slot rate. Slot synchronisation has been taken into consideration for the first time as offset PPM spectrum exhibits discrete slot rate component. The effect of pulse shaping and modulating index on the spectrum has been shown. The dependency of slot component on the pulse shape is examined. The results show that the frame synchronisation is possible for offset PPM as this coding exhibits a strong frame rate component. A comparison of spectral characteristics has been presented considering digital, multiple and shortened PPM. For ease of implementation an offset PPM coder has been designed. In this work an efficient clock recovery topology is presented for offset PPM data sequence at the receiver end. For clock recovery, a phase locked loop is designed. Data recovery has also been presented. It is shown that a frame clock can be extracted from the data sequence that yields the possibility of frame synchronization. A detailed noise analysis has been performed for random offset PPM input. It has been shown that the proposed clock recovery system is also effective for extracting other data sequence. To elucidate, a multiple Pulse Position Modulation (MPPM) data sequence is considered. The MPPM data sequence has also been synchronised with the recovered clock. A noise analysis is carried out for multiple PPM.

Optical fibre systems have played a key role in making possible the extraordinary growth in world-wide communications that has occurred in the last 25 years, and are vital in enabling the proliferating use of the Internet. Its high bandwidth capabilities, low attenuation characteristics, low cost, and immunity from the many disturbances that can afflict electrical wires and wireless communication links make it ideal for gigabit transmission and a major building block in the telecommunication infrastructure. The main concern of this thesis is a full and detailed investigation and implementation of the Offset Pulse Position Modulation (Offset PPM) communication system. Novel work is carried out for applying Offset PPM over an optical communication channel theoretically and experimentally to examine the system performance. An Offset PPM encoder and decoder were implemented to code Pulse Code Modulation (PCM) format into Offset PPM format and to decode back the Offset PPM to PCM. The first paradigm of implementation was implemented using electronic components. A further investigation took place on the Offset PPM associated output. Computer programming and simulation using the VHSIC Hardware Description Language (VHDL) of this PPM code was considered and comparison with previous theoretical results presented. The received Offset PPM signal returned back to its original input PCM form without errors. Successful VHDL and Field Programmable Gate Array (FPGA) implementation using Altera Quartus II of Offset PPM encoder and decoder as a single system has been presented in the study. An FPGA embedded Bit Error Rate (BER) test device has also been implemented for sensitivity measurements purposes and all the designs have been tested successfully with back-to-back testing. Results show that Offset PPM is an advantageous PPM code for optic communication. Furthermore, the system has achieved a very high data rate of 50 Mb/s without an optical communication set. An optical communication system (transmitter/receiver) over POF was developed and the Offset PPM scheme was investigated through this optical channel. Results show that the Offset PPM sequence transferred through the optic system without being altered. In addition, this implementation is optimised PPM coding; the system is working perfectly with up to 10 Mb/s with 10-12 BER based on the limitations of the optical communication set. All the results and analyses indicate that Offset PPM is an ideal alternative to be considered for highly dispersive optical channels, and performance evaluation for higher bandwidths also favourably compares to existing coding schemes.

<p>With an increasing number of transistors integrated on a single die, the need for global on-chip interconnectivity is growing. Long interconnects, in turn, have very large capacitances which consume a large share of a chip’s total power budget.</p><p>Power consumption can be lowered in several ways, mainly by reduction of switching activity, reduction of total capacitance and by using low voltage swing. In this project, the issue is addressed by proposing a new encoding based on Pulse Width Modulation (PWM). The implementation of this encoding will both lower the switching activity and decrease the capacitance between nearby wires. Hence, the total effective capacitance will be reduced considerably. Schematic level implementation of a robust transmitter and receiver circuit was carried out in CMOS090, designed for speeds up to 100 MHz. On a 10 mm wire, this implementation would give a 40% decrease in power dissipation compared to a parallel bus having the same metal footprint. The proposed encoding can be efficiently applied for global interconnects in sub-micron systems-on-chip (SoC).</p>