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Journal articles on the topic 'PVT variations'

Author: Grafiati

Published: 4 June 2021

Last updated: 18 February 2022

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1

Islam, Aminul, and Mohd Hasan. "VARIABILITY ANALYSIS OF 6T AND 7T SRAM CELL IN SUB-45NM TECHNOLOGY." IIUM Engineering Journal 12, no. 1 (2011): 13–30. http://dx.doi.org/10.31436/iiumej.v12i1.25.

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This paper analyses standard 6T and 7T SRAM (static random access memory) cell in light of process, voltage and temperature (PVT) variations to verify their functionality and robustness. The 7T SRAM cell consumes higher hold power due to its extra cell area required for its functionality constraint. It shows 60% improvement in static noise margin (SNM), 71.4% improvement in read static noise margin (RSNM) and 50% improvement in write static noise margin (WSNM). The 6T cell outperforms 7T cell in terms of read access time (TRA) by 13.1%. The write access time (TWA) of 7T cell for writing "1" is

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2

Pable, S. D., Mohd Ajmal Kafeel, A. K. Kureshi, and Mohd Hasan. "Robustness Comparison of Emerging Devices for Portable Applications." Journal of Nanomaterials 2012 (2012): 1–8. http://dx.doi.org/10.1155/2012/242459.

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Extensive development in portable devices imposes pressing need for designing VLSI circuits with ultralow power (ULP) consumption. Subthreshold operating region is found to be an attractive solution for achieving ultralow power. However, it limits the circuit speed due to use of parasitic leakage current as drive current. Maintaining power dissipation at ultralow level with enhanced speed will further broaden the application area of subthreshold circuits even towards the field programmable gate arrays and real-time portable domain. Operating the Si-MOSFET in subthreshold regions degrades the c

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3

Lu, Yingchun, Huaguo Liang, Liang Yao, et al. "Jitter-Quantizing-Based TRNG Robust Against PVT Variations." IEEE Access 8 (2020): 108482–90. http://dx.doi.org/10.1109/access.2020.3000231.

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4

Tang, Aoxiang, Yang Yang, Chun-Yi Lee, and Niraj K. Jha. "McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, no. 9 (2015): 1616–27. http://dx.doi.org/10.1109/tvlsi.2014.2352354.

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5

Sonoda, Masashi, Kentaro Shioura, Takahiro Nakano, et al. "Structural Characterization of the Growth Front of 4H-SiC Boules Grown Using the Physical Vapor Transport Growth Method." Materials Science Forum 924 (June 2018): 15–18. http://dx.doi.org/10.4028/www.scientific.net/msf.924.15.

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The defect structure at the growth front of 4H-SiC boules grown using the physical vapor transport (PVT) method has been investigated using high resolution x-ray diffraction and x-ray topography. The crystal parameters such as the c-lattice constant exhibited characteristic variations across the growth front, which appeared to be caused by variation in surface morphology of the as-grown surface of the boules rather than the defect structure underneath the surface. X-ray topography also revealed that basal plane dislocations are hardly nucleated at the growth front during PVT growth of 4H-SiC c

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6

Roslita Rusli, Julie, Suhaidi Shafie, Roslina Mohd Sidek, Hasmayadi Abdul Majid, W. Z. Wan Hassan, and M. A. Mustafa. "Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation." Indonesian Journal of Electrical Engineering and Computer Science 17, no. 2 (2020): 783. http://dx.doi.org/10.11591/ijeecs.v17.i2.pp783-792.

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Power consumption and speed are the main criteria in designing comparator for analog-to-digital converter (ADC). This paper presents an optimized low voltage low power dynamic comparator which is robust to process, voltage and temperature (PVT) variations with adequate speed. The comparator circuit was designed using 0.18µm CMOS technology with low voltage supply of 0.8V. The method used to verify the robustness of the comparator circuit across 45 PVT is presented. The circuit is simulated with 10% voltage supply variation, five process corners and temperature variation from 0°C to 100°C. The

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7

Sharma, Neha, and Rajeevan Chandel. "Variation tolerant and stability simulation of low power SRAM cell analysis using FGMOS." International Journal of Modeling, Simulation, and Scientific Computing 12, no. 04 (2021): 2150029. http://dx.doi.org/10.1142/s179396232150029x.

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With technology scaling, stability, power dissipation, and device variability, the impact of process, voltage and temperature (PVT) variations has become dominant for static random access memory (SRAM) analysis for productivity and failure. In this paper, ten-transistors (10T) and low power eight-transistors SRAM cells are redesigned using floating-gate MOS transistors (FGMOS). Power centric parameters viz. read power, write power, hold power and delay are the performance analysis metrics. Further, the stochastic parameter variation to study the variability tolerance of the redesigned cell, PV

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8

WANG, Jinn-Shyan, Yu-Juey CHANG, and Chingwei YEH. "Design of High-Performance CMOS Level Converters Considering PVT Variations." IEICE Transactions on Electronics E94-C, no. 5 (2011): 913–16. http://dx.doi.org/10.1587/transele.e94.c.913.

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9

Yang, Yang, and Niraj K. Jha. "FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT Variations." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, no. 12 (2014): 2462–75. http://dx.doi.org/10.1109/tvlsi.2013.2293886.

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10

LEE, JANGJOON, SRIKAR BHAGAVATULA, SWARUP BHUNIA, KAUSHIK ROY, and BYUNGHOO JUNG. "SELF-HEALING DESIGN IN DEEP SCALED CMOS TECHNOLOGIES." Journal of Circuits, Systems and Computers 21, no. 06 (2012): 1240011. http://dx.doi.org/10.1142/s0218126612400117.

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CMOS technologies are suffering from increased variability due to process, supply voltage and temperature (PVT) variations as we enter the tens-of-nanometer regime. Analog and mixed-signal circuits have failed to effectively exploit the high-speed and low-noise properties that deep scaled CMOS technologies provide due to marginality issues. Large variations in leakage current and threshold voltage also make highly integrated digital designs challenging. In addition, device aging introduces a temporal dimension to variations in circuit performance. Consequently, there is an increasing need for

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11

Sharma, Suruchi, Santosh Kumar, Alok Kumar Mishra, D. Vaithiyanathan, and Baljit Kaur. "Process, Voltage, and Temperature Aware Analysis of ISCAS C17 Benchmark Circuit." Advanced Science, Engineering and Medicine 12, no. 10 (2020): 1289–95. http://dx.doi.org/10.1166/asem.2020.2707.

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High leakage currents such as sub-threshold leakage, junction leakage, and gate leakage currents have become prominent sources of power consumption in CMOS VLSI circuits due to rapid technology scaling in the nanometer regimen accompanied by supply voltage reduction. Consequently, in the nanometer regime, it is imperative to estimate and reduce leakage capacity. However, this continuous aggressive scaling makes the CMOS circuits more prone to Process, Voltage, and Temperature (PVT) variations at nanometer technologies. This paper explores a systematic analysis of various leakage power reductio

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12

Sharma, Vijay Kumar. "Design of Low Leakage PVT Variations Aware CMOS Bootstrapped Driver Circuit." Journal of Circuits, Systems and Computers 26, no. 09 (2017): 1750137. http://dx.doi.org/10.1142/s0218126617501377.

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This paper describes a novel complementary metal oxide semiconductor (CMOS) bootstrapped driver circuit for driving large resistive capacitive (RC) loads. The proposed bootstrapped driver reduces the leakage as well as process, voltage and temperature (PVT) variations from the boosted nodes with higher switching speed. Very large scale integration (VLSI) designers need boosted output for the logic circuits which are operating in ultra-deep submicron regime under widespread use of low voltage. Proposed CMOS bootstrapped driver circuit is easy in design; built with minimum number of transistors

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13

Sharma, Vijay Kumar, Manisha Pattanaik, and Balwinder Raj. "PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits." Microelectronics Reliability 54, no. 1 (2014): 90–99. http://dx.doi.org/10.1016/j.microrel.2013.09.018.

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14

Bou-Sleiman, Sleiman, and Mohammed Ismail. "Dynamic Self-Regulated Charge Pump With Improved Immunity to PVT Variations." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, no. 8 (2014): 1716–26. http://dx.doi.org/10.1109/tvlsi.2013.2278375.

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15

Yang, Yu, Jianqiu Guo, Ouloide Goue, et al. "Effect of Doping Concentration Variations in PVT-Grown 4H-SiC Wafers." Journal of Electronic Materials 45, no. 4 (2016): 2066–70. http://dx.doi.org/10.1007/s11664-016-4378-8.

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16

Rashdan, Mostafa. "Effect of PVT variations on differential-time signaling data link architecture." Analog Integrated Circuits and Signal Processing 99, no. 1 (2018): 71–79. http://dx.doi.org/10.1007/s10470-018-1304-4.

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17

Saha, Aloke, Sushil Kumar, Debajit Das та Mrinmoy Chakraborty. "LP-HS Logic Evaluation on TSMC 0.18μm CMOS Technology". International Journal of High Speed Electronics and Systems 26, № 04 (2017): 1740024. http://dx.doi.org/10.1142/s0129156417400249.

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Present paper analyses different aspects of “Low Power-High Speed” (LP-HS) logic in favour of present day ULSI system focus. At first, the speed-power efficiency of LP-HS logic is investigated by designing some basic digital building blocks like Buffer, OR, AND, XOR etc. Next, the Voltage Transfer Characteristics (VTC), Noise Margin (NM) and the temperature effect on logic threshold with respect to LP-HS Buffer circuit are examined. The robustness and reliability of LP-HS Logic has been measured in terms of corner analysis with TT (Typical), FF (Fastest) and SS (Slowest) PVT (Process Voltage T

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18

Li, Lin An, Ming Tang, Wen Ou, and Yang Hong. "An All CMOS Current Reference." Applied Mechanics and Materials 135-136 (October 2011): 192–97. http://dx.doi.org/10.4028/www.scientific.net/amm.135-136.192.

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In this paper, an all CMOS current reference circuit which generates a reference current independent of PVT (Process, supply Voltage, and Temperature) variations is presented. The circuit consists of a self-biased current source (SBCS) and two nested connected transistors which supply a voltage with positive temperature coefficient and the resulting reference circuit has low temperature coefficient. It is based on CSMC 0.5um mixed-signal process with the supply voltage of 5V. The precision of reference current is about ±3.05% when considering the process, supply voltage and temperature variati

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19

Carbajal-Gomez, Victor Hugo, Esteban Tlelo-Cuautle, Jesus Manuel Muñoz-Pacheco, Luis Gerardo de la Fraga, Carlos Sanchez-Lopez, and Francisco Vidal Fernandez-Fernandez. "Optimization and CMOS design of chaotic oscillators robust to PVT variations: INVITED." Integration 65 (March 2019): 32–42. http://dx.doi.org/10.1016/j.vlsi.2018.10.010.

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20

Tang, Aoxiang, Xun Gao, Lung-Yen Chen, and Niraj K. Jha. "Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations." ACM Journal on Emerging Technologies in Computing Systems 12, no. 4 (2016): 1–21. http://dx.doi.org/10.1145/2795231.

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21

Agwa, Shady, Eslam Yahya, and Yehea Ismail. "ERSUT: A Self-Healing Architecture for Mitigating PVT Variations Without Pipeline Flushing." IEEE Transactions on Circuits and Systems II: Express Briefs 63, no. 11 (2016): 1069–73. http://dx.doi.org/10.1109/tcsii.2016.2548261.

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22

Riemens, W. G., A. M. Schulte, and L. N. J. de Jong. "Birba Field PVT Variations Along the Hydrocarbon Column and Confirmatory Field Tests." Journal of Petroleum Technology 40, no. 01 (1988): 83–88. http://dx.doi.org/10.2118/13719-pa.

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23

Chaudhuri, Sourindra M., and Niraj K. Jha. "3D vs. 2D Device Simulation of FinFET Logic Gates under PVT Variations." ACM Journal on Emerging Technologies in Computing Systems 10, no. 3 (2014): 1–19. http://dx.doi.org/10.1145/2567670.

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24

Ren, Wenhua, Jing Zhang, Yuying Chen, et al. "Evaluation of Coagulation, Fibrinolysis and Endothelial Biomarkers in Cirrhotic Patients With or Without Portal Venous Thrombosis." Clinical and Applied Thrombosis/Hemostasis 26 (January 1, 2020): 107602962098266. http://dx.doi.org/10.1177/1076029620982666.

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To evaluate variations in coagulation, fibrinolysis and endothelial marker expression in cirrhotic patients and to explore their clinical value and predictive performance in cirrhotic patients with or without portal vein thrombosis (PVT), we performed a case-control study with 175 cirrhotic patients and 50 healthy individuals. 99 patients had PVT and another 76 patients did not. All participants were evaluated for plasma levels of conventional hemostatic markers. Thrombin-antithrombin complex (TAT), plasmin-α2-plasmin inhibitor complex (PIC), thrombomodulin (TM), tissue plasminogen activator i

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25

Carbajal-Gomez, Victor, Esteban Tlelo-Cuautle, Carlos Sanchez-Lopez, and Francisco Fernandez-Fernandez. "PVT-Robust CMOS Programmable Chaotic Oscillator: Synchronization of Two 7-Scroll Attractors." Electronics 7, no. 10 (2018): 252. http://dx.doi.org/10.3390/electronics7100252.

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Designing chaotic oscillators using complementary metal-oxide-semiconductor (CMOS) integrated circuit technology for generating multi-scroll attractors has been a challenge. That way, we introduce a current-mode piecewise-linear (PWL) function based on CMOS cells that allow programmable generation of 2–7-scroll chaotic attractors. The mathematical model of the chaotic oscillator designed herein has four coefficients and a PWL function, which can be varied to provide a high value of the maximum Lyapunov exponent. The coefficients are implemented electronically by designing operational transcond

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26

Li, Xin, and Jin Sun. "Genetic Algorithm-Based Multi-Objective Optimization for Statistical Yield Analysis Under Parameter Variations." Journal of Circuits, Systems and Computers 26, no. 01 (2016): 1750009. http://dx.doi.org/10.1142/s0218126617500098.

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Due to process scaling, variability in process, voltage, and temperature (PVT) parameters leads to a significant parametric yield loss, and thus impacts the optimization for circuit designs seriously. Previous parametric yield optimization algorithms are limited to optimizing either power yield or timing yield separately, without combining them together for simultaneous optimization. However, neglecting the negative correlation between the performance metrics, such as power and timing measurements, will bring on significant accuracy loss. This paper suggests an efficient multi-objective optimi

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27

Ghorbel, Imen, Fayrouz Haddad, Wenceslas Rahajandraibe, and Mourad Loulou. "A subthreshold low-power CMOS LC-VCO with high immunity to PVT variations." Analog Integrated Circuits and Signal Processing 93, no. 3 (2017): 415–26. http://dx.doi.org/10.1007/s10470-017-1047-7.

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28

Yan, Aibin, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Yiming Ouyang, and Xuejun Li. "An SEU resilient, SET filterable and cost effective latch in presence of PVT variations." Microelectronics Reliability 63 (August 2016): 239–50. http://dx.doi.org/10.1016/j.microrel.2016.06.004.

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29

Ramanjaneyulu, N., D. Satyanarayana, and K. Satya. "Design of a Three Stage Ring VCO in 0.18 µm CMOS under PVT Variations." International Journal of Computer Applications 170, no. 8 (2017): 35–39. http://dx.doi.org/10.5120/ijca2017914932.

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30

Yu, Ye, and Niraj K. Jha. "Statistical Optimization of FinFET Processor Architectures under PVT Variations Using Dual Device-Type Assignment." ACM Journal on Emerging Technologies in Computing Systems 14, no. 1 (2018): 1–25. http://dx.doi.org/10.1145/3110714.

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31

Wellmann, Peter J., Ralf Müller, and Michel Pons. "Modeling and Experimental Verification of SiC M-PVT Bulk Crystal Growth." Materials Science Forum 527-529 (October 2006): 75–78. http://dx.doi.org/10.4028/www.scientific.net/msf.527-529.75.

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We have studied the impact of the chemical nature of additional gases fed into the modified physical vapor transport (M-PVT) growth cell. In particular experiments were carried out using helium, argon, nitrogen and propane in the growth setup. Numerical modeling was used to address the underlying physical and chemical effects that impact the global temperature field. It is found that chemical decomposition of complex gases plays a secondary role as heat source or sink. However, temperature variations related to varying gas compositions fed to the systems are primarily induced by changes of the

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32

Silva, Juliano Fernandes da, Fábio Yuzo Nakamura, Lorival José Carminatti, et al. "The peak velocity of Carminatti’s Test for aerobic-fitness training in male soccer players." Brazilian Journal of Kinanthropometry and Human Performance 19, no. 6 (2017): 652–62. http://dx.doi.org/10.5007/1980-0037.2017v19n6p652.

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Aerobic energy transference is highly required and accounts for more than 90% of total energy consumption during a soccer match. In addition high aerobic fitness contributes to recovery from high-intensity intermittent exercise, specific to performance in soccer. The aim of the present study was to examine whether the peak velocity in the Carminatti’s test (PVT-CAR) for prescribing interval-training drills is effective in eliciting aerobic-fitness development intensities in male soccer-players. Fifteen Brazilian male elite soccer-players (U20) were tested for T-CAR and monitored for heart rate

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33

HASAN, S. M. REZAUL. "A NOVEL LOW-VOLTAGE CMOS VARIABLE GAIN AMPLIFIER WITH GAIN-INDEPENDENT INPUT IMPEDANCE MATCHING FOR DTV TUNING APPLICATIONS." Journal of Circuits, Systems and Computers 18, no. 06 (2009): 1119–36. http://dx.doi.org/10.1142/s0218126609005563.

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This paper presents a novel low-voltage single stage CMOS RF Variable Gain Amplifier (RFVGA) designed in 130 nm IBM CMOS process technology using current feed-back gain-independent impedance matching. The proposed RFVGA has a nearly constant gain over the 400 MHz–1 GHz frequency band. Also, it has a 70 dB gain variation (-40 dB to 30 dB) which is decibel-linear within this frequency band for a control voltage in the range of 0.41 V–0.81 V. The RFVGA demonstrates high linearity (THD ≈ -60 dB) and noise immunity (average Noise Figure ≤ 6 dB). It has an input referred third-order intercept point

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34

Leighton, Angela, Michael Weinborn, and Murray Maybery. "Bridging the Gap Between Neurocognitive Processing Theory and Performance Validity Assessment among the Cognitively Impaired: A Review and Methodological Approach." Journal of the International Neuropsychological Society 20, no. 9 (2014): 873–86. http://dx.doi.org/10.1017/s135561771400085x.

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AbstractBigler (2012) and Larrabee (2012) recently addressed the state of the science surrounding performance validity tests (PVTs) in a dialogue highlighting evidence for the valid and increased use of PVTs, but also for unresolved problems. Specifically, Bigler criticized the lack of guidance from neurocognitive processing theory in the PVT literature. For example, individual PVTs have applied the simultaneous forced-choice methodology using a variety of test characteristics (e.g., wordvs. picture stimuli) with known neurocognitive processing implications (e.g., the “picture superiority effe

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35

Goyanes, S., W. Salgueiro, A. Somoza, J. A. Ramos, and I. Mondragon. "Direct relationships between volume variations at macro and nanoscale in epoxy systems. PALS/PVT measurements." Polymer 45, no. 19 (2004): 6691–97. http://dx.doi.org/10.1016/j.polymer.2004.07.057.

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36

Lee, Seng Siong, Lini Lee, Fabian Wai Lee Kung, Ahmed Saad, and Gim Heng Tan. "A fully integrated and high precision 350 mV amplitude regulated LVDS transmitter compensating PVT variations." Microelectronics Journal 81 (November 2018): 192–99. http://dx.doi.org/10.1016/j.mejo.2018.05.003.

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37

Abbasizadeh, Hamed, Imran Ali, Behnam Samadpoor Rikan, et al. "260- $\mu$ W DCO With Constant Current Over PVT Variations Using FLL and Adjustable LDO." IEEE Transactions on Circuits and Systems II: Express Briefs 65, no. 6 (2018): 739–43. http://dx.doi.org/10.1109/tcsii.2018.2792786.

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38

Ghorbel, Imen, Fayrouz Haddad, Wenceslas Rahajandraibe, and Mourad Loulou. "Correction to: A subthreshold low-power CMOS LC-VCO with high immunity to PVT variations." Analog Integrated Circuits and Signal Processing 93, no. 3 (2017): 427. http://dx.doi.org/10.1007/s10470-017-1068-2.

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39

Pourahmad, Ali, Rasoul Dehghani, and Seyed Amir-Reza Ahmadi-Mehr. "Low-voltage high-linear Gm-transimpedance instrumentation amplifier with robust feedforward biasing against PVT variations." AEU - International Journal of Electronics and Communications 131 (March 2021): 153585. http://dx.doi.org/10.1016/j.aeue.2020.153585.

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40

Castañeda-Aviña, Perla Rubi, Esteban Tlelo-Cuautle, and Luis Gerardo de la Fraga. "Single-Objective Optimization of a CMOS VCO Considering PVT and Monte Carlo Simulations." Mathematical and Computational Applications 25, no. 4 (2020): 76. http://dx.doi.org/10.3390/mca25040076.

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The optimization of analog integrated circuits requires to take into account a number of considerations and trade-offs that are specific to each circuit, meaning that each case of design may be subject to different constraints to accomplish target specifications. This paper shows the single-objective optimization of a complementary metal-oxide-semiconductor (CMOS) four-stage voltage-controlled oscillator (VCO) to maximize the oscillation frequency. The stages are designed by using CMOS current-mode logic or differential pairs and are connected in a ring structure. The optimization is performed

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41

Zhang, Li, Liwen Liu, Yiqi Zhuang, et al. "A novel sense amplifier to mitigate the impact of NBTI and PVT variations for STT-MRAM." IEICE Electronics Express 16, no. 12 (2019): 20190238. http://dx.doi.org/10.1587/elex.16.20190238.

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42

Reddy, K. Niranjan, and P. V. Y. Jayasree. "Low power process, voltage, and temperature (PVT) variations aware improved tunnel FET on 6T SRAM cells." Sustainable Computing: Informatics and Systems 21 (March 2019): 143–53. http://dx.doi.org/10.1016/j.suscom.2019.01.005.

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43

Kyung Ki Kim and Yong-Bin Kim. "A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, no. 4 (2009): 517–28. http://dx.doi.org/10.1109/tvlsi.2008.2007958.

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44

Chaudhuri, Sourindra M., Prateek Mishra, and Niraj K. Jha. "Accurate Leakage/Delay Estimation for FinFET Standard Cells under PVT Variations using the Response Surface Methodology." ACM Journal on Emerging Technologies in Computing Systems 11, no. 2 (2014): 1–20. http://dx.doi.org/10.1145/2665066.

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45

Luo, Pu. "DLL-Based Receiver for High Speed Data Transmission." Advanced Materials Research 753-755 (August 2013): 2471–74. http://dx.doi.org/10.4028/www.scientific.net/amr.753-755.2471.

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For modern high speed DAC, receiving data reliably from FPGA is a big challenge, data-independent skew is the major problem. usually system employ data clock while transmitting LVDS data from FPGA. then LVDS data is latched by delayed data clock which generated by DLL in chip. Because DLL has a negative feedback loop, system suffer small effect of PVT variations, robustness is guaranteed. The receiving circuits were implemented in a all-digital 0.18μm CMOS technology ,occupies 0.7 mm2 of area. It operates in the frequency range of 20 MHz~600 MHz.

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46

Van Bockel, Bjorn, Jeffrey Prinzie, and Paul Leroux. "Radiation Assessment of a 15.6ps Single-Shot Time-to-Digital Converter in Terms of TID." Electronics 8, no. 5 (2019): 558. http://dx.doi.org/10.3390/electronics8050558.

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This article presents a radiation tolerant single-shot time-to-digital converter (TDC) with a resolution of 15.6 ps, fabricated in a 65 nm complementary metal oxide semiconductor (CMOS) technology. The TDC is based on a multipath pseudo differential ring oscillator with reduced phase delay, without the need for calibration or interpolation. The ring oscillator is placed inside a Phase Locked Loop (PLL) to compensate for Process, Voltage and Temperature (PVT) variations- and variations due to ionizing radiation. Measurements to evaluate the performance of the TDC in terms of the total ionizing

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47

Tardif, Xavier, Nicolas Boyard, Vincent Sobotka, Nicolas Lefèvre, and Didier Delaunay. "A New PvT Device for the Thermoplastics Characterization in Extreme Thermal Conditions." Key Engineering Materials 554-557 (June 2013): 1619–27. http://dx.doi.org/10.4028/www.scientific.net/kem.554-557.1619.

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In this work, we present an apparatus associated to a methodology that is able to determine simultaneously and according to temperature (up to 400°C) the specific volume (up to 200MPa), the thermal conductivity and the temperature function of the crystallization kinetics. The PvT-XT is a home-built device that is able to impose and quantify 1D heat transfer through the radius of a sample. This apparatus controls the applied pressure on the sample while measuring its volume variations. The associated moving boundary model takes into account the temperature and crystallinity gradients. Specific

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48

Nawab, Yasir, Nicolas Boyard, Vincent Sobotka, Pascal Casari, and Frédéric Jacquemin. "Measurement and Modelling of Chemical Shrinkage of Thermoset Composites." Key Engineering Materials 504-506 (February 2012): 1129–34. http://dx.doi.org/10.4028/www.scientific.net/kem.504-506.1129.

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Knowledge of resin chemical shrinkage is crucial for the determination of residual strains, stresses and warpage of composite parts during curing. Shrinkage measurement is more accurate on several millimetre thick samples. However, in that case thermal properties of resin and the strong coupling between thermoset chemical reactions (generally rapid and strongly exothermal) and thermal fields lead to non-negligible thermal and curing gradients in the piece. It is then necessary to take these variations into account to have an accurate description of the shrinkage. In the present study, a home b

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GYOHTEN, T., F. MORISHITA, I. HAYASHI, et al. "An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design." IEICE Transactions on Electronics E89-C, no. 11 (2006): 1519–25. http://dx.doi.org/10.1093/ietele/e89-c.11.1519.

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Yan, Guihai, Xiaoyao Liang, Yinhe Han, and Xiaowei Li. "Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors." ACM SIGARCH Computer Architecture News 38, no. 3 (2010): 485–96. http://dx.doi.org/10.1145/1816038.1816025.

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