Relevant bibliographies by topics / QPSK demodulator

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'QPSK demodulator'

Author: Grafiati
Published: 4 June 2021
Last updated: 13 February 2022

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Journal articles on the topic "QPSK demodulator"

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Mohamed Moubark, Asraf, and Sawal Hamid Md Ali. "A Novel Sample Based Quadrature Phase Shift Keying Demodulator." Scientific World Journal 2014 (2014): 1–7. http://dx.doi.org/10.1155/2014/107831.

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This paper presents a new practical QPSK receiver that uses digitized samples of incoming QPSK analog signal to determine the phase of the QPSK symbol. The proposed technique is more robust to phase noise and consumes up to 89.6% less power for signal detection in demodulation operation. On the contrary, the conventional QPSK demodulation process where it uses coherent detection technique requires the exact incoming signal frequency; thus, any variation in the frequency of the local oscillator or incoming signal will cause phase noise. A software simulation of the proposed design was successfully carried out using MATLAB Simulink software platform. In the conventional system, at least 10 dB signal to noise ratio (SNR) is required to achieve the bit error rate (BER) of 10−6, whereas, in the proposed technique, the same BER value can be achieved with only 5 dB SNR. Since some of the power consuming elements such as voltage control oscillator (VCO), mixer, and low pass filter (LPF) are no longer needed, the proposed QPSK demodulator will consume almost 68.8% to 99.6% less operational power compared to conventional QPSK demodulator.
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Sadchenko, Andrey, and Oleg Kushnirenko. "QPSK-Modulation Modem Invariant to the Rotation of the Signal Constellation Plane." Electrical, Control and Communication Engineering 14, no. 2 (December 1, 2018): 149–56. http://dx.doi.org/10.2478/ecce-2018-0018.

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AbstractIn order to increase the efficiency of dedicated frequency channels, i.e. to increase the specific data transfer rate, multipositional quadrature phase shift keying (QPSK, aka 4-PSK) should be used. The problems with QPSK signal demodulation is a rotation of the signal constellation plane by an angle multiple of 90° and a slow response of the carrier oscillation recovery scheme. The study considers the existing methods for eliminating the phase ambiguity of the recovered carrier frequency in typical QPSK modems, and identifies the shortcoming of a low-speed response oscillation recovery circuit. The authors propose a QPSK demodulator circuit with a fast adjustment of the reference oscillator, which is due to the fact that no loop filter is used in the feedback and that a digital calculator of the required phase shift is used. An algorithm for the frame synchronization restoration with the simultaneous elimination of the phase ambiguity multiple of 90° was also developed using synthesized binary sequences with an ideal non-periodic autocorrelation function (NACF) at even shifts that do not have the rotary symmetry property. The phase ambiguity elimination algorithm proposed in the article can be used as an alternative to standard modems with differential coding.
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Shehab, Maisoon, Ibrahim Saber, Mustafa Eltokhy, Fathy Amer, and Zaki Nossair. "Development of QPSK Demodulator using DSP Techniques." Engineering Research Journal 163 (September 1, 2019): 1–15. http://dx.doi.org/10.21608/erj.2019.114093.

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Kim, D., M. Ko, K. C. Choi, and W. Y. Choi. "Mixed-mode QPSK demodulator for home networking applications." Electronics Letters 47, no. 2 (2011): 92. http://dx.doi.org/10.1049/el.2010.2656.

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Zhu, Jin, Qiu Xu, and Dan Dan Yan. "Design of QPSK Modem Based on FPGA." Applied Mechanics and Materials 427-429 (September 2013): 884–87. http://dx.doi.org/10.4028/www.scientific.net/amm.427-429.884.

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Quadrature Phase Shift Keying as a efficient modulation mode to be used in wireless communication. it is significant to study its implement. This paper presents a method to design QPSK modulator and demodulator, which use field programmable gate array. We will analysis the principle of QPSK modem and will give the design method, display the block diagram of the system in this paper and discuss its feasibility. The whole system is divided into several small models. Because space is limited, we can only introduce some key modules. Such as carrier recover and bit synchronization
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Trambarulo, R., M. Schneider, and M. J. Gans. "High-speed QPSK modulator and demodulator with subharmonic pumping." IEEE Transactions on Microwave Theory and Techniques 36, no. 12 (December 1988): 1714–19. http://dx.doi.org/10.1109/22.17404.

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Chen, Fei, Ryan Bespalko, and Brian M. Frank. "A CMOS QPSK demodulator frontend for a PON ONU." Microwave and Optical Technology Letters 53, no. 5 (March 21, 2011): 1056–62. http://dx.doi.org/10.1002/mop.25902.

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Van der Wal, R., and L. Montreuil. "QPSK and BPSK demodulator chip-set for satellite applications." IEEE Transactions on Consumer Electronics 41, no. 1 (1995): 30–41. http://dx.doi.org/10.1109/30.370307.

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Hamed, K. W., A. P. Freundorfer, Y. M. M. Antar, P. Frank, and D. Sawatzky. "A High-Bit Rate Ka-Band Direct Conversion $QPSK$ Demodulator." IEEE Microwave and Wireless Components Letters 18, no. 5 (May 2008): 365–67. http://dx.doi.org/10.1109/lmwc.2008.922134.

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Cao, YuXiong, DanYu Wu, XinYu Liu, and Zhi Jin. "Broad-band direct QPSK modulator/demodulator for wireless gigabit communication." Chinese Science Bulletin 58, no. 3 (January 2013): 427–32. http://dx.doi.org/10.1007/s11434-012-5566-4.

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Dissertations / Theses on the topic "QPSK demodulator"

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Kotze, P. P. A. (Pieter Paul Adriaan). "Development of a QPSK demodulator for the Sunsat 1 groundstation." Thesis, Stellenbosch : Stellenbosch University, 2000. http://hdl.handle.net/10019.1/51689.

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Thesis (MEng)--Stellenbosch University, 2000.
ENGLISH ABSTRACT: The purpose of this thesis is the description of the development of a QPSK demodulator for the Sunsat 1 groundstation. A general overview of the functioning and requirements of a typical QPSK demodulator system is given. Several methods or algorithms for clock and carrier recovery are discussed. Specific attention is given to the QPSK demodulator chipset from Philips used for the implementation of the demodulator. The digital decoding logic used to serialize the parallel I and Q datastream is explained. Finally measurement techniques for performance evaluation of QPSK systems are investigated. As part of this the implementation loss of the developed QPSK demodulator is measured.
AFRIKAANSE OPSOMMING: Die doelwit van hierdie tesis is om die ontwikkeling van 'n QPSK demodulator vir die Sunsat 1 grondstasie te beskryf. 'n Algemene oorsig oor die funksionering en vereistes van 'n tipiese QPSK demodulator stelsel word gegee. Verskeie algoritmes en tegnieke vir klok en draersein herwinning word ondersoek en bespreek. Spesifieke verwysing word telkens gemaak na die QPSK demodulasie vlokkie paar van Philips gebruik vir die implementering van die demodulator. Die digitale dekodering logika benodig vir die datastroom verpakking word ondersoek en beskryf. Laastens word daar gekyk na meettegnieke en evaluasie van QPSK demodulasie stelsels se prestasie. As deel hiervan word die implementasie verlies van die ontwikkelde QPSK demodulator stelsel gemeet.
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Biyoghe, Joel S. "Design and implementation of a high data rate QPSK demodulator for nanosatellites." Thesis, Cape Peninsula University of Technology, 2017. http://hdl.handle.net/20.500.11838/2744.

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Thesis (Master of Engineering in Electrical Engineering)--Cape Peninsula University of Technology, 2017.
This dissertation presents the development of a quadrature phase shift keying (QPSK) demodulator for nanosatellites that complies with both the limited resources associated with nanosatellites as well as the flexibility and configurability required for a software defined radio (SDR) platform. This research project is a component of a bigger project, which is to develop a high-speed receiver for nanosatellites, and aims to provide a practical solution to the need for communication technologies that support emerging nanosatellite applications, such as Earth observation and communications. The development of the QPSK demodulator follows an all-digital implementation approach. The main reason for selecting this approach is to have a system that is flexible and reconfigurable to comply with the SDR requirements. Another reason for selecting this approach is to comply with the low noise system, low power consumption as well as the small size and weight requirements associated with nanosatellites. The QPSK demodulator is implemented on an IGLOO2 Field Programmable Gate Array (FPGA), due to its robustness to radiation and high-speed capability. Initially, the techniques used to design each subsystem of the QPSK demodulator are selected. Then, algorithms to digitally implement the designed subsystems are produced. Thereafter, the code for the digital QPSK demodulator is written and verified in Matlab first. The simulation of the Matlab-based QPSK demodulator performs satisfactorily. Subsequently, the code to implement the QPSK demodulator on an FPGA (IGLOO2) has been written in Libero, using VHSIC Hardware Description Language (VHDL). The resulting FPGA-based QPSK demodulator has been emulated in Libero (an integration and development environment (IDE) for Microsemi FPGAs) using a test-bench as well as other analysis tools. The test-bench results are visualized using Modelsim. The results show that the demodulator can support data rates up to 13.25 Mbps if 16 samples-per-symbols are used, and up to 26.5 Mbps if 8 samples-per-symbols are used. It also has a very good bit-error-rate performance, which is simulated to be within a factor of 5 of the theoretical limit of QPSK modulation. Finally, the demodulator consumes less than 15 mW at the maximum operating speed. and has been coded to mitigate the effects of space radiation and noise contriution by the demodulator itself.
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Booysen, Samuel. "The design of a high speed topology for a QPSK demodulator with emphasis on the synchronization algorithms needed for demodulation." Thesis, Stellenbosch : University of Stellenbosch, 2010. http://hdl.handle.net/10019.1/4107.

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Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2010.
ENGLISH ABSTRACT: This thesis describes the design and implementation of a software based QPSK demodulator with a demodulation speed of 100 Mbps. The objective of the thesis was to identify a topology for the QPSK demodulator that would allow for high data rates and the design of the synchronization algorithms for carrier and symbol recovery. The QPSK demodulator was implemented on an Altera Stratix II field programmable gate array (FPGA), which does complex I and Q sampling on a down converted 720 MHz QPSK signal. The I and Q down converted baseband signals are sent through matched filters which are implemented with discrete components to maximize the signal to noise ratio of the received rectangular baseband pulses. A 1 GSPS direct digital synthesizer (DDS) is used to generate the synchronous clock for the analog to digital converters which samples the matched filter outputs. The demodulator uses two samples per symbol to demodulate the QPSK signal. A dual locking system is implemented to have a wide pre-locking filter for symbol synchronization and a narrow band post-lock filter to minimize the loop noise. A symbol lock detection algorithm decides when the symbol recovery loop is locked and switches between the loop filters. A second 1 GSPS DDS output is mixed with a local oscillator to generate the 1.44 GHz LO signal for the quadrature down conversion. The carrier recovery loop uses a numerically controlled oscillator inside the FPGA for initial carrier acquisition which allows for very wide locking bandwidth. After lock is achieved, the external carrier recovery loop takes over and removes any frequency offset in the complex baseband signal by changing the frequency of the DDS. A QPSK modulator was also developed to provide a QPSK signal with known data. The modulator can generate any constellation diagram up to 256 points.
AFRIKAANSE OPSOMMING: Hierdie tesis bespreek die ontwerp en implementasie van ’n sagteware gebaseerde QPSK demodulator met ’n demodulasie spoed van 100 Mbps. Die doelstelling is om ’n topologie te identifiseer vir ’n QPSK demodulator wat ’n hoë datatempo sal toelaat en ook om sinkronisasie algoritmes te ontwikkel vir draer en simbool herkenning. Die QPSK demodulator is geïmplimenteer op ’n Stratix II FPGA van Altera wat kompleks basisband monstering doen op infase en kwadratuur basisband seine. Die basisband seine word gegenereer van ’n 720 MHz QPSK sein met ’n kwadratuur menger wiese uittrees deur puls passende filters gestuur word om die sein tot ruis verhouding te maksimeer. ’n Een gigamonster per sekonde direk digitale sintetiseerder (DDS) is gebruik om die klok vir die analoog na digitaal omsetters te genereer vir sinkrone monstering van die pulse passende filter uittrees. Die demodulator gebruik twee monsters per simbool om ’n QPSK sein te demoduleer. ’n Tweevoudige sluit algoritme word gebruik vir die simbool sinkronisasie waar ’n wyeband filter die inisiële sluit funksie verrig en dan word daar oorgeslaan na ’n nouband filter vir fase volging wat die ruis in die terugvoerlus verminder. Daar is ’n simbool sluit detektor wat identifiseer wanneer die simbool beheerlus gesluit is en selekteer dan die gepaste filter. ’n Tweede DDS en ’n sintetiseerder se uittrees word gemeng om ’n 1.44 GHz draer te genereer vir kohurente frekwensie translasie in die kwadratuur menger. Die draer sinkronisasie gebruik ’n numeries beheerbare ossilator vir die inisiële frekwensie en fase sluit wat baie vinnig geimplenteer kan word omdat dit alles in sagteware binne in die FPGA gebeur. Na die interne draer beheerlus gesluit is, neem die eksterne beheerlus oor om enige fase of frekwensie afsette in die kompleks basisband seine van die kwadratuur menger te verwyder deur die frekwensie van die draer DDS te beheer. ’n QPSK modulator is ook ontwikkel om verwysings data te genereer. Enige konstelasie vorm tot 256 punte kan geimplementeer word.
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Wahlgren, Max, and Daniel Forsberg. "Hårdvarubaserade SOQPSK-algoritmer : En VHDL-implementation av algoritmer för att modulera & demodulera SOQPSK-signaler." Thesis, Linköping University, Department of Science and Technology, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-12327.

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Beroende på i vilken miljö man har tänkt att använda trådlös kommunikation behöver man hitta en modulationsteknik som passar under rådande förhållanden. I början på 1980-talet utvecklade den Amerikanska militären en modulationsteknik som kallas för Shaped BPSK (SBPSK) avsedd att tillämpas i kommunikationslänkar med satelliter. Vidareutveckling av SBPSK ledde sedan fram till en förbättrad variant kallad Shaped Offset QPSK (SOQPSK). På senare år har denna modulationsteknik börjat användas i civila tillämpningar och vidareutvecklats ytterligare för att ge den än bättre prestanda. År 2004 antogs SOQPSK som en modulationsteknik i den internationella flygplanskommunikationsstandarden, IRIG-106. Versionen av SOQPSK som antogs i IRIG-106 har flera bra egenskaper som t. ex. dess spektraltäthet. Detta gör denna typ av modulationsteknik lämpad för kommunikationslänkar med bl.a. flygplan, satelliter och rymdsonder (‘deep-space’).

Målet med examensarbetet har varit att implementera algoritmer för att skicka och ta emot SOQPSK-modulerade signaler. Dessa algoritmer skulle utvecklas i VHDL för att sedan syntetiseras och programmera en FPGA. Uppgiften har givits av Syncore Technologies AB i Linköping.

Arbetet har resulterat i fungerande implementationer både i mjukvara och hårdvara. Hårdvarulösningen är verifierad att klara bithastiheter upp till 30 Mbit/s. Teoretisk information om allmän modulering/demodulering och specifikt kring SOQPSK behandlas i rapporten. Uppbyggnaden av en teoretisk sändar- och mottagarmodell utformad för SOQPSK-kommunikation beskrivs också i rapporten för att ge en bättre helhetsbild av implementationen som utförts.

Arbetets syfte är att ligga till grund för Syncore AB som utvecklar en kom- munikationslänk med SOQPSK-kompatibilitet.

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Martinec, Matěj. "Modulátor a demodulátor pro mikrovlnný spoj." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-221252.

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This work is dealing with the design of intermediate part of transmitter and reciever that use digital BPSK and QPSK modulations for microwave link that works in 24 – 26 GHz bands. Besides choosing the suitable modulator and demodulator there was need to provide proper connection of this part with transceiver Nortel CTR26-01M. Input and output of this intermediate part was take out to baseband, where was need to ensure the transfer of diferential inputs of modulator and demodulator to symetric leading for reason of data communication with PC, for which was created the algorithms to provide transmitting and receiving data. Complete structure controlled by the microcontroller has been enliven and furthemore there was created the measurement of chosen parameteres.
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Rosmansyah, Yusep. "Soft-demodulation of QPSK and 16-QAM for turbo coded WCDMA mobile communication systems." Thesis, University of Surrey, 2003. http://epubs.surrey.ac.uk/792192/.

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Hischke, Sven. "New receivers for differentially encoded Offset-QPSK : investigation in differential demodulation and per-survivor-processing algorithms." Thesis, City University London, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.310449.

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Chen, Fei. "A CMOS QPSK Demodulator Frontend for GPON." Thesis, 2010. http://hdl.handle.net/1974/5910.

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This thesis examines the design of a QPSK demodulator frontend for GPON transceiver at end user's side. Since lowering the cost of the terminal transceivers in an access network like GPON is a key requirement, CMOS technology is used and several area-saving design techniques are applied. The designed frontend circuit saved more than 80% area of the key components like the mixers and the QVCO than some published designs which can also fit the application. A measurement in frequency domain and a simulation in time domain verified that this frontend is able to demodulate a QPSK signal with a data rate as high as 5 Gbit/s. Two structures of quadrature oscillators are firstly presented and compared. One is an LC QVCO centered at 5 GHz, which has a tuning range of 3 GHz, a phase noise of -100.8 dBc/Hz at 1 MHz offset, and an area of 0.15 mm2 excluding pads. The other is a ring QVCO which only takes an area of 0.019 mm2. But it has a higher phase noise of -81 dBc/Hz at 1 MHz offset. Then two broadband mixers are described separately. The first one provides a high conversion gain, but its input linearity is insufficient to meet the input power requirement. The second mixer obtains required input linearity but with a trade-off of conversion gain. Both mixers have a broadband input impedance match from 2 GHz to 8 GHz. The first mixer has a conversion gain of 8.5 dB and an input 1 dB compresion point at -17 dBm. The second mixer has a conversion gain of -7 dB with an on-chip buffer or -2.1 dB without buffer, but an input 1 dB compresion point at -5 dBm. A frontend circuit is lastly presented. It integrates the compact ring QVCO, two broadband mixers with high input linearity, and two second-order LC ladder low pass filters. A Frequency domain measurement shows the expected spectrum down conversion of a 2.5 Gsym/s QPSK signal centered at 5 GHz. The whole frontend circuit including pads takes 1 mm2 area, and consumed 157 mW power.
Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2010-06-29 10:59:45.312
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Hsin-FangLi and 李欣芳. "A Low Power O-QPSK Receiver with Injection-Locked Demodulator." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/rz8c38.

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Yang, Kai-Chieh, and 楊凱傑. "A Non-coherent QPSK Demodulator in 13.56MHz ISM Band Applications." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/17833668679584298127.

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碩士
國立中正大學
電機工程研究所
101
The thesis develops two QPSK demodulators for 13.56MHz ISM band. First, the first demodulator is implemented without phase-locked loop structure. The transition waveform is detected for the demodulation. Furthermore, the phase-locked loop is adopted for the second demodulator. The modified single bit sampling method is used for the this demodulation. The design challenges for these two demodulators are low power and high data rate which are suitable for retinal prosthesis. The first demodulator is an offset QPSK demodulator which has the advantage of fewer transition between the transformation of quadrature signals. Two circuits including edge counter and small signal detection can be sued for demodulation, because four offset QPSK transitions can be detected and the data can be easily recovered. The proposed demodulator only consumes 5.2μw at 6.78-MHz data rate. This circuit also achieves ultra-low energy with 0.77 pJ/bit. The second demodulator is a QPSK demodulator which has the tolerance for the noise and distortion from transmitted device and channel. The modified single bit sampling method is used for the noise and distortion robustness. A phase-locked loop is used to generate the sampling clock for the data detection. Moreover, the symbol timing recovery and training sequence are designed for clock synchronization and data decision. The demodulator only consumes 109.7μw at 3.39 MHz Data rate. This circuit also achieves ultra-low energy with 0.0323nJ/bit.
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Books on the topic "QPSK demodulator"

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Tok, Mehmet Kubilay. Use of a coherent square wave reference to demodulate BPSK carriers and a visual indicator of the quality of received QPSK carriers. 1987.

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Book chapters on the topic "QPSK demodulator"

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Cardells-Tormo, Francisco, Javier Valls-Coquillat, Vicenc Almenar-Terre, and Vicente Torres-Carot. "Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard." In Lecture Notes in Computer Science, 102–11. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-46117-5_12.

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Conference papers on the topic "QPSK demodulator"

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Scofield, Adam C., George A. Seller, Thomas J. Shaw, Daniele M. Monahan, and George C. Valley. "Speckle-based BPSK/QPSK demodulator." In Optical Fiber Communication Conference. Washington, D.C.: OSA, 2019. http://dx.doi.org/10.1364/ofc.2019.th2a.38.

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Rai, Akanksh, and Vaegae Naveen Kumar. "Wideband acquisition technique for QPSK demodulator." In 2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT). IEEE, 2016. http://dx.doi.org/10.1109/rteict.2016.7807869.

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Harabi, Ferid, Sawssen Lakdhar, and Ali Gharsallah. "QPSK demodulator based on six port junction." In 2015 IEEE 15th Mediterranean Microwave Symposium (MMS). IEEE, 2015. http://dx.doi.org/10.1109/mms.2015.7375442.

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Raghavendra, M. R., S. Sharada, K. Chandrasekharam, Anshuman Sharma, Pooja Gupta, and M. Midhun. "Design and development of high bit rate QPSK demodulator." In 2013 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT). IEEE, 2013. http://dx.doi.org/10.1109/conecct.2013.6469295.

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Zafar, Adnan, and S. Zaineb Farooq. "Implementation and analysis of QPSK & 16QAM modulator & demodulator." In 2008 2nd International Conference on Advances in Space Technologies (ICAST). IEEE, 2008. http://dx.doi.org/10.1109/icast.2008.4747688.

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Karam, G. "A variable-rate QPSK demodulator for digital satellite TV reception." In International Broadcasting Convention - IBC '94. IEE, 1994. http://dx.doi.org/10.1049/cp:19940825.

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Martirosov, V. E., and G. A. Alekseev. "Investigation of the QPSK-GLSS Demodulator using Phase Space Method." In 2021 Systems of Signals Generating and Processing in the Field of on Board Communications. IEEE, 2021. http://dx.doi.org/10.1109/ieeeconf51389.2021.9416093.

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Bondariev, Andriy, Ivan Maksymiv, and Serhiy Altunin. "Simulation and Experimental Research of the Enhanced BPSK and QPSK Demodulator." In 2020 IEEE 15th International Conference on Advanced Trends in Radioelectronics, Telecommunications and Computer Engineering (TCSET). IEEE, 2020. http://dx.doi.org/10.1109/tcset49122.2020.235538.

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Sebesta, Jiri, and Ales Prokes. "Timing Recovery Modification for High-rate BPSK and QPSK Digital Demodulator." In 2006 International Conference on Communication Technology. IEEE, 2006. http://dx.doi.org/10.1109/icct.2006.341888.

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Rieth, Dominik, Christoph Heller, and Gerd Ascheid. "Fully coherent shaped offset QPSK demodulator architecture with superior hardware efficiency." In 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). IEEE, 2016. http://dx.doi.org/10.1109/apccas.2016.7803924.

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