Dissertations / Theses on the topic 'QPSK demodulator'

Thesis (MEng)--Stellenbosch University, 2000.
ENGLISH ABSTRACT: The purpose of this thesis is the description of the development of a QPSK demodulator for the Sunsat 1 groundstation. A general overview of the functioning and requirements of a typical QPSK demodulator system is given. Several methods or algorithms for clock and carrier recovery are discussed. Specific attention is given to the QPSK demodulator chipset from Philips used for the implementation of the demodulator. The digital decoding logic used to serialize the parallel I and Q datastream is explained. Finally measurement techniques for performance evaluation of QPSK systems are investigated. As part of this the implementation loss of the developed QPSK demodulator is measured.
AFRIKAANSE OPSOMMING: Die doelwit van hierdie tesis is om die ontwikkeling van 'n QPSK demodulator vir die Sunsat 1 grondstasie te beskryf. 'n Algemene oorsig oor die funksionering en vereistes van 'n tipiese QPSK demodulator stelsel word gegee. Verskeie algoritmes en tegnieke vir klok en draersein herwinning word ondersoek en bespreek. Spesifieke verwysing word telkens gemaak na die QPSK demodulasie vlokkie paar van Philips gebruik vir die implementering van die demodulator. Die digitale dekodering logika benodig vir die datastroom verpakking word ondersoek en beskryf. Laastens word daar gekyk na meettegnieke en evaluasie van QPSK demodulasie stelsels se prestasie. As deel hiervan word die implementasie verlies van die ontwikkelde QPSK demodulator stelsel gemeet.

Thesis (Master of Engineering in Electrical Engineering)--Cape Peninsula University of Technology, 2017.
This dissertation presents the development of a quadrature phase shift keying (QPSK) demodulator for nanosatellites that complies with both the limited resources associated with nanosatellites as well as the flexibility and configurability required for a software defined radio (SDR) platform. This research project is a component of a bigger project, which is to develop a high-speed receiver for nanosatellites, and aims to provide a practical solution to the need for communication technologies that support emerging nanosatellite applications, such as Earth observation and communications. The development of the QPSK demodulator follows an all-digital implementation approach. The main reason for selecting this approach is to have a system that is flexible and reconfigurable to comply with the SDR requirements. Another reason for selecting this approach is to comply with the low noise system, low power consumption as well as the small size and weight requirements associated with nanosatellites. The QPSK demodulator is implemented on an IGLOO2 Field Programmable Gate Array (FPGA), due to its robustness to radiation and high-speed capability. Initially, the techniques used to design each subsystem of the QPSK demodulator are selected. Then, algorithms to digitally implement the designed subsystems are produced. Thereafter, the code for the digital QPSK demodulator is written and verified in Matlab first. The simulation of the Matlab-based QPSK demodulator performs satisfactorily. Subsequently, the code to implement the QPSK demodulator on an FPGA (IGLOO2) has been written in Libero, using VHSIC Hardware Description Language (VHDL). The resulting FPGA-based QPSK demodulator has been emulated in Libero (an integration and development environment (IDE) for Microsemi FPGAs) using a test-bench as well as other analysis tools. The test-bench results are visualized using Modelsim. The results show that the demodulator can support data rates up to 13.25 Mbps if 16 samples-per-symbols are used, and up to 26.5 Mbps if 8 samples-per-symbols are used. It also has a very good bit-error-rate performance, which is simulated to be within a factor of 5 of the theoretical limit of QPSK modulation. Finally, the demodulator consumes less than 15 mW at the maximum operating speed. and has been coded to mitigate the effects of space radiation and noise contriution by the demodulator itself.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2010.
ENGLISH ABSTRACT: This thesis describes the design and implementation of a software based QPSK demodulator with a demodulation speed of 100 Mbps. The objective of the thesis was to identify a topology for the QPSK demodulator that would allow for high data rates and the design of the synchronization algorithms for carrier and symbol recovery. The QPSK demodulator was implemented on an Altera Stratix II field programmable gate array (FPGA), which does complex I and Q sampling on a down converted 720 MHz QPSK signal. The I and Q down converted baseband signals are sent through matched filters which are implemented with discrete components to maximize the signal to noise ratio of the received rectangular baseband pulses. A 1 GSPS direct digital synthesizer (DDS) is used to generate the synchronous clock for the analog to digital converters which samples the matched filter outputs. The demodulator uses two samples per symbol to demodulate the QPSK signal. A dual locking system is implemented to have a wide pre-locking filter for symbol synchronization and a narrow band post-lock filter to minimize the loop noise. A symbol lock detection algorithm decides when the symbol recovery loop is locked and switches between the loop filters. A second 1 GSPS DDS output is mixed with a local oscillator to generate the 1.44 GHz LO signal for the quadrature down conversion. The carrier recovery loop uses a numerically controlled oscillator inside the FPGA for initial carrier acquisition which allows for very wide locking bandwidth. After lock is achieved, the external carrier recovery loop takes over and removes any frequency offset in the complex baseband signal by changing the frequency of the DDS. A QPSK modulator was also developed to provide a QPSK signal with known data. The modulator can generate any constellation diagram up to 256 points.
AFRIKAANSE OPSOMMING: Hierdie tesis bespreek die ontwerp en implementasie van ’n sagteware gebaseerde QPSK demodulator met ’n demodulasie spoed van 100 Mbps. Die doelstelling is om ’n topologie te identifiseer vir ’n QPSK demodulator wat ’n hoë datatempo sal toelaat en ook om sinkronisasie algoritmes te ontwikkel vir draer en simbool herkenning. Die QPSK demodulator is geïmplimenteer op ’n Stratix II FPGA van Altera wat kompleks basisband monstering doen op infase en kwadratuur basisband seine. Die basisband seine word gegenereer van ’n 720 MHz QPSK sein met ’n kwadratuur menger wiese uittrees deur puls passende filters gestuur word om die sein tot ruis verhouding te maksimeer. ’n Een gigamonster per sekonde direk digitale sintetiseerder (DDS) is gebruik om die klok vir die analoog na digitaal omsetters te genereer vir sinkrone monstering van die pulse passende filter uittrees. Die demodulator gebruik twee monsters per simbool om ’n QPSK sein te demoduleer. ’n Tweevoudige sluit algoritme word gebruik vir die simbool sinkronisasie waar ’n wyeband filter die inisiële sluit funksie verrig en dan word daar oorgeslaan na ’n nouband filter vir fase volging wat die ruis in die terugvoerlus verminder. Daar is ’n simbool sluit detektor wat identifiseer wanneer die simbool beheerlus gesluit is en selekteer dan die gepaste filter. ’n Tweede DDS en ’n sintetiseerder se uittrees word gemeng om ’n 1.44 GHz draer te genereer vir kohurente frekwensie translasie in die kwadratuur menger. Die draer sinkronisasie gebruik ’n numeries beheerbare ossilator vir die inisiële frekwensie en fase sluit wat baie vinnig geimplenteer kan word omdat dit alles in sagteware binne in die FPGA gebeur. Na die interne draer beheerlus gesluit is, neem die eksterne beheerlus oor om enige fase of frekwensie afsette in die kompleks basisband seine van die kwadratuur menger te verwyder deur die frekwensie van die draer DDS te beheer. ’n QPSK modulator is ook ontwikkel om verwysings data te genereer. Enige konstelasie vorm tot 256 punte kan geimplementeer word.

Beroende på i vilken miljö man har tänkt att använda trådlös kommunikation behöver man hitta en modulationsteknik som passar under rådande förhållanden. I början på 1980-talet utvecklade den Amerikanska militären en modulationsteknik som kallas för Shaped BPSK (SBPSK) avsedd att tillämpas i kommunikationslänkar med satelliter. Vidareutveckling av SBPSK ledde sedan fram till en förbättrad variant kallad Shaped Offset QPSK (SOQPSK). På senare år har denna modulationsteknik börjat användas i civila tillämpningar och vidareutvecklats ytterligare för att ge den än bättre prestanda. År 2004 antogs SOQPSK som en modulationsteknik i den internationella flygplanskommunikationsstandarden, IRIG-106. Versionen av SOQPSK som antogs i IRIG-106 har flera bra egenskaper som t. ex. dess spektraltäthet. Detta gör denna typ av modulationsteknik lämpad för kommunikationslänkar med bl.a. flygplan, satelliter och rymdsonder (‘deep-space’).

Målet med examensarbetet har varit att implementera algoritmer för att skicka och ta emot SOQPSK-modulerade signaler. Dessa algoritmer skulle utvecklas i VHDL för att sedan syntetiseras och programmera en FPGA. Uppgiften har givits av Syncore Technologies AB i Linköping.

Arbetet har resulterat i fungerande implementationer både i mjukvara och hårdvara. Hårdvarulösningen är verifierad att klara bithastiheter upp till 30 Mbit/s. Teoretisk information om allmän modulering/demodulering och specifikt kring SOQPSK behandlas i rapporten. Uppbyggnaden av en teoretisk sändar- och mottagarmodell utformad för SOQPSK-kommunikation beskrivs också i rapporten för att ge en bättre helhetsbild av implementationen som utförts.

Arbetets syfte är att ligga till grund för Syncore AB som utvecklar en kom- munikationslänk med SOQPSK-kompatibilitet.

This work is dealing with the design of intermediate part of transmitter and reciever that use digital BPSK and QPSK modulations for microwave link that works in 24 – 26 GHz bands. Besides choosing the suitable modulator and demodulator there was need to provide proper connection of this part with transceiver Nortel CTR26-01M. Input and output of this intermediate part was take out to baseband, where was need to ensure the transfer of diferential inputs of modulator and demodulator to symetric leading for reason of data communication with PC, for which was created the algorithms to provide transmitting and receiving data. Complete structure controlled by the microcontroller has been enliven and furthemore there was created the measurement of chosen parameteres.

This thesis examines the design of a QPSK demodulator frontend for GPON transceiver at end user's side. Since lowering the cost of the terminal transceivers in an access network like GPON is a key requirement, CMOS technology is used and several area-saving design techniques are applied. The designed frontend circuit saved more than 80% area of the key components like the mixers and the QVCO than some published designs which can also fit the application. A measurement in frequency domain and a simulation in time domain verified that this frontend is able to demodulate a QPSK signal with a data rate as high as 5 Gbit/s. Two structures of quadrature oscillators are firstly presented and compared. One is an LC QVCO centered at 5 GHz, which has a tuning range of 3 GHz, a phase noise of -100.8 dBc/Hz at 1 MHz offset, and an area of 0.15 mm2 excluding pads. The other is a ring QVCO which only takes an area of 0.019 mm2. But it has a higher phase noise of -81 dBc/Hz at 1 MHz offset. Then two broadband mixers are described separately. The first one provides a high conversion gain, but its input linearity is insufficient to meet the input power requirement. The second mixer obtains required input linearity but with a trade-off of conversion gain. Both mixers have a broadband input impedance match from 2 GHz to 8 GHz. The first mixer has a conversion gain of 8.5 dB and an input 1 dB compresion point at -17 dBm. The second mixer has a conversion gain of -7 dB with an on-chip buffer or -2.1 dB without buffer, but an input 1 dB compresion point at -5 dBm. A frontend circuit is lastly presented. It integrates the compact ring QVCO, two broadband mixers with high input linearity, and two second-order LC ladder low pass filters. A Frequency domain measurement shows the expected spectrum down conversion of a 2.5 Gsym/s QPSK signal centered at 5 GHz. The whole frontend circuit including pads takes 1 mm2 area, and consumed 157 mW power.
Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2010-06-29 10:59:45.312

碩士
國立中正大學
電機工程研究所
101
The thesis develops two QPSK demodulators for 13.56MHz ISM band. First, the first demodulator is implemented without phase-locked loop structure. The transition waveform is detected for the demodulation. Furthermore, the phase-locked loop is adopted for the second demodulator. The modified single bit sampling method is used for the this demodulation. The design challenges for these two demodulators are low power and high data rate which are suitable for retinal prosthesis. The first demodulator is an offset QPSK demodulator which has the advantage of fewer transition between the transformation of quadrature signals. Two circuits including edge counter and small signal detection can be sued for demodulation, because four offset QPSK transitions can be detected and the data can be easily recovered. The proposed demodulator only consumes 5.2μw at 6.78-MHz data rate. This circuit also achieves ultra-low energy with 0.77 pJ/bit. The second demodulator is a QPSK demodulator which has the tolerance for the noise and distortion from transmitted device and channel. The modified single bit sampling method is used for the noise and distortion robustness. A phase-locked loop is used to generate the sampling clock for the data detection. Moreover, the symbol timing recovery and training sequence are designed for clock synchronization and data decision. The demodulator only consumes 109.7μw at 3.39 MHz Data rate. This circuit also achieves ultra-low energy with 0.0323nJ/bit.

碩士
國立交通大學
電信研究所
85
In this thesis, we proposed a bursty DQPSK demodulator which can be used in HFC system uplink. The key component of the demodulator, burst timing recovery, is implemented as a clock phase correlator. The advantages of the clock phase correlator are short acquisition time and minimum jitter. The function of clock phase correlator was verified in a system simulation. The demodulator was implemented using FPGA. Finally, by using commercial QPSK modem chips in an actual cable modem, we have successfully demonstratedthe modem's upstream transmission functions.

碩士
逢甲大學
電子工程所
94
Electromagnetic wave is commonly used as the media for wireless transmission at long distance. Electromagnetic wave is known as carrier wave and it will not be weakened even in airless environments. Using carrier wave to transmit signals is called modulation. Demodulation is the process of extracting signals from carrier wave. There are four methods in analog modulation, such as AM, FM, PM, etc. There are many techniques in the digital modulation include Amplitude Shift Keying (ASK), Frequency Shift Keying (FSK), and Phase Shift Keying (PSK) etc. The ASK technique is easily interfered and attenuated by electromagnetic wave. And electromagnetic wave has the ability to cause bit error rate (BER) to increase. Therefore, there are many technologies adopt FSK or PSK techniques to implement wanted modulation. The Quadrature Phase Shift Keying (QPSK) modulation is 2-bits technique which can transmitted a signal modulation symbol and to reduce symbol error rate. As we understand, QPSK is usually applied when signal is transmitted with high frequency interference noise, for instance, satellite transmission system. This thesis is set in four parts to discuss the design and implementation of QPSK modulator and demodulator for wireless transceiver.

碩士
龍華科技大學
電子工程系碩士班
103
Some front-end designs of receiver in TSMC 0.18μm 1P6M CMOS process are presented in this thesis. These designs include balun low noise amplifier, daul band voltage controlled oscillator (VCO), I/Q Mixer and digital demodulation circuit. The main design is a integrated QPSK receiver for ISM band application. In the receiver, low noise amplifier (LNA) is designed to suppress the effect of the noise effect of the followed stages on the system. The design of mixer tends to high linearity, high conversion gain and good isolations between ports. The design goals of VCO are low phase noise and low power consumption. In the circuit designs, the first chip is “A 0.6-V 2.4/5.8 -GHz dual-band LC VCO in CMOS 0.18-μm Technology“. Based on the need of dual band systems, the single output frequency of oscillator is expanded. Due to low gain of transistor and low quality factor of LC tank over high frequency, even mode circuit is used to double the output frequency from 2.4G Hz to 4.8G Hz. So a dual push-push harmonic oscillator is used to implement the dual band oscillator.Measurement results of the proposed VCO reveal phase-noises of -115 dBc/Hz at 1-MHz offset frequency away from the carrier frequency of 2.4 GHz and -108 dBc/Hz at 1-MHz offset frequency away from 5.8 GHz. The output powers of oscillation are -5.87dBm from the carrier frequency of 2.4 GHz and -11.74dBm from the carrier frequency of 5.8 GHz.The oscillation frequencies can be tuned from 2.4 to 3.318 GHz in the lower band (2.4-GHz band) and from 4.8 to 6.6 GHz in the higher band (5.8-GHz band), the power consumption is only 13.62mW under the supply voltage of 0.6V. The core area is 1.15mm × 0.76 mm2. The second chip is “A Design of Balun Low-Noise Amplifier for ISM band Application“. The technology of source coupling to the gate is used to ensure that the differential output signals of LNA are symmetrically balanced with 180° angle difference. The output terminals are both achieved to wideband via pi type matching networks. The post simulation results of the LNA provides an input matching (S11) and output matching (S22 and S33 ) are lower than -10.67dB and -10dB respectively.The LNA provides a gain (S21and S31) of 15.7dB while drawing 10.32mW from 0.8-V supply voltage. The LNA achieves 2.97dB noise figure (NF) in the frequency of 2.45GHz. The post simulation results P1dB and IIP3 of the proposed LNA are -17.5 and -7.87dBm, respectively. The size of the chip is 1.188× 0.93 mm2。 The third chip is “A Design of a QPSK Demodulator Receiver for 2.4GHz ISM Band“ Application. The current bleeding technique is used to enhance the conversion gain and reduce the consumption power in the proposed I/Q Mixer. In the digital baseband circuit, the digital back-end including parallel to series circuit is synchronized by system clk and the mapping logic technique is used to demodulate the input modulated signal to transmission data.The QPSK demodulator receiver provides a input matching (S11) of 17.67dB while drawing 37.424mW from 1.2-V supply voltage and achieves -32dB LO to RF isolation (dB) in the frequency of 2.45GHz. Using the post simulation, series data rate of the proposed QPSK demodulator receiver is 80Mbps. The size of the chip is 1.2×1.187 mm2。

碩士
大同工學院
電機工程研究所
87
In direct sequence (DS) spread spectrum systems, the delay-locked loop (DLL) is often used as code tracking loop to achieve and maintain a fine phase synchronism between the received and locally generated pseudo-noise (PN) code sequences. This thesis is investigating the performance of decision-directed phase-locked loop (PLL) mainly on the presence of multiuser interference and additive white Gaussian noise (AWGN) channels. The performance of DLL is generally evaluated in terms of root-mean-square (RMS) tracking error (RMS jitter variance) and mean time to lose lock (MTLL). RMS jitter variance serves as a single important parameter to characterize the loop performance under additive white Gaussian noise channels. We explore a method to reduce the RMS jitter variance based on a noncoherent code tracking loop. The simulations indicate that our results get much improvement. Also, we quote the concepts of Huang and Nakagawa’s. Under the same power, the performance is more accurate and nearly optimal for the same Viterbi’s systems. Our approach can also improve RMS jitter variance.

碩士
國立中山大學
電機工程學系研究所
86
The inherent processing gain of a spread spectrum system provides the system with a sufficient degree of interference rejection capability. However, sometimes the processing gain does not provide sufficient improvement due to the bandwidth restriction or strong narrowband interference, the system therefore fails to reject the interference., In some of these cases. the performance of the system can be improved by using extra signal processing techniques to complement the spresad spectrum modulation. In the recent paper [21], it offers the optimum demodulation code instead of the original PN sequence to despread the received signal under a single-tone interference, and the system performance is thus improved. In this paper, we extend some previous results of optimum demodulation code for rejecting multiple-tone interference, and for a QPSK/DS-SS system. In a QPSK/DS-SS system ,we search a complex optimum demodulation code instead of the original PN sequence to despread the received signal in the receiver. However, we first have to know the autocorrelation function of the received signal when using Wiener-Hopf equation to look for the complex optimum demodulation code. To avoid this problem, we design a structure by using a FIR transversal filter and complex LMS algorithm to calculate the approximate optimum solution. According to simulation results, we prove that this approximate solution si very close to the optimum one, and the output signal to interference plus noise ratio (SINR) of this method is obviously larger than that of using the original PN sequence.

碩士
國立交通大學
電機學院IC設計產業專班
98
This paper focusing on QPSK(Quaternary Phase Shift Keying) data demodulator utilizing phase locking technique. The architecture is based on phase locked loop which extracts timing information directly from received RF signal and further demodulates the received data pattern. In other words, it works without reference crystal oscillator and the problem of local oscillator frequency in alignment between transmitter and receiver ends could readily be solved with this new architecture. The main application of this work is for short range wireless communication system. This chip includes PFD, Charge Pump, Loop Filter, VCO, Divider, LNA, Mixer, Post Amplifier, Frequency Discriminator, and Demodulator and several other digital blocks. This is a chip of high integration level and low power consumption. This chip is fabricated in TSMC 0.18μm CMOS technology. It operates at a rate of 2.4GHz and it is well suited for short range data processing. The measured power consumption is below 20mW, the sensitivity for receiving 1Mbps digital modulated QPSK signal is -70dBm with a BER no larger than 10-3. Also the measured phase noise is well below -110dBc/Hz at an frequency offset of 1MHz.