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Dissertations / Theses on the topic 'Quadrature demodulation'
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Campbell, Heather A. (Heather Alyce). "Simulation of quadrature amplitude demodulation in a digital telemetry system." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/38783.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.Includes bibliographical references (leaves 122-123).
by Heather A. Campbell.
M.Eng.
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Ramchander, Rajesh. "Quadrature-point stabilization of Mach-Zehnder interferometers." Thesis, Virginia Tech, 1990. http://hdl.handle.net/10919/41594.
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Optical fiber magnetometers are extremely sensitive devices which are capable of competing with magnetometers implemented using other technologies. Demodulation of the signals detected using these magnetometers can be performed using either homodyne or heterodyne techniques. Higher sensitivities have been achieved using homodyne rather than heterodyne techniques, but with homodyne demodulation there exists the inherent problem of quadrature-point stabilization. Presented here is a review of existing quadrature-point stabilization methods and experimental results concerning the application of one of them which uses a piezoelectric transducer in the reference arm of an all-fiber Mach-Zehnder interferometer.Master of Science
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Ndovi, Lusungu. "Benefits to processor load for quadrature baseband versus radio frequency demodulation algorithms." Thesis, Link to the online version, 2008. http://hdl.handle.net/10019/1946.
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Schaaff, Kevin P. "Monterey Bay acoustic tomography : signal processing using multi-channel data-synchronized quadrature phase demodulation." Thesis, Monterey, California. Naval Postgraduate School, 1989. http://hdl.handle.net/10945/27143.
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Efthymiou, Spyros. "Modelling of pyroelectric detectors detection by digital signal processing algorithms." Thesis, University of Manchester, 2013. https://www.research.manchester.ac.uk/portal/en/theses/modelling-of-pyroelectric-detectors-detection-by-digital-signal-processing-algorithms(61eca3ad-2bb7-4ef1-869c-8ec0c4965f3b).html.
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Pyroelectric Detector (PED) models are developed considering the classical heat balance equation to simulate the detector’s response under specified radiation conditions. Studies on the behaviour of a PED are presented under the conditions of step function and a pulsed load. Finite Element Methods (FEMs) have been used to obtain 3D models of the resulting temperature field in a Lithium Tantalate (LiTaO3) pyroelectric crystal, incorporated in a complete commercial detector, taking into account details of its geometry and thermal connectivity. The novelty is the achieved facility to predict the response to pulsed radiation, which is valuable for the engineering of pulsed-source sensor systems requiring detection at room temperature. In this thesis, we present a signal processing (SP) algorithm, which combines the principle of Quadrature Synchronous Demodulation (QSD) and Gated Integration (GI), to achieve an improved signal-to-noise ratio (SNR) in pulsed signal measurements. As a first step, the pulse is bracketed by a gating window and the samples outside the window are discarded. The gate duration is calculated to ensure that the periodic signal at the output has an 'apparent' duty factor close to 0.5. This signal is then fed continuously for QSD to extract the magnitude and phase of its fundamental component, referenced to a sinusoidal signal with period defined by the gate length. An improved SNR performance results not only from the increase of the average signal energy, but also from the noise suppression inherent to the QSD principle. We introduce this method as Gated Quadrature Synchronous Demodulation (GQSD), emphasizing the synergy between GΙ and QSD.
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Lee, Dennis, Marvin Simon, and Tsun-Yee Yan. "ENHANCED PERFORMANCE OF FQPSK-B RECEIVER BASED ON TRELLIS-CODED VITERBI DEMODULATION." International Foundation for Telemetering, 2000. http://hdl.handle.net/10150/607724.
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International Telemetering Conference Proceedings / October 23-26, 2000 / Town & Country Hotel and Conference Center, San Diego, CaliforniaCommercial FQPSK-B receivers traditionally use symbol-by-symbol detection and have a 2 dB Eb=No loss relative to ideal QPSK at a bit error rate (BER) of 10^(-5). An enhanced FQPSK-B receiver using a Viterbi algorithm (VA) to perform trellis decoding is simulated and shown to have a 1.2 dB Eb=No improvement over symbol-by-symbol detection for 10^(-5)5 BER at the cost of increased complexity. A simplified Viterbi receiver with a reduced trellis and significantly less complexity is introduced with only a slight BER degradation compared to the full Viterbi receiver. In addition, a theoretical bit error probability expression for the symbol-by-symbol FQPSK-B receiver is derived and compared with simulation results.
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Booysen, Samuel. "The design of a high speed topology for a QPSK demodulator with emphasis on the synchronization algorithms needed for demodulation." Thesis, Stellenbosch : University of Stellenbosch, 2010. http://hdl.handle.net/10019.1/4107.
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Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2010.ENGLISH ABSTRACT: This thesis describes the design and implementation of a software based QPSK demodulator with a demodulation speed of 100 Mbps. The objective of the thesis was to identify a topology for the QPSK demodulator that would allow for high data rates and the design of the synchronization algorithms for carrier and symbol recovery. The QPSK demodulator was implemented on an Altera Stratix II field programmable gate array (FPGA), which does complex I and Q sampling on a down converted 720 MHz QPSK signal. The I and Q down converted baseband signals are sent through matched filters which are implemented with discrete components to maximize the signal to noise ratio of the received rectangular baseband pulses. A 1 GSPS direct digital synthesizer (DDS) is used to generate the synchronous clock for the analog to digital converters which samples the matched filter outputs. The demodulator uses two samples per symbol to demodulate the QPSK signal. A dual locking system is implemented to have a wide pre-locking filter for symbol synchronization and a narrow band post-lock filter to minimize the loop noise. A symbol lock detection algorithm decides when the symbol recovery loop is locked and switches between the loop filters. A second 1 GSPS DDS output is mixed with a local oscillator to generate the 1.44 GHz LO signal for the quadrature down conversion. The carrier recovery loop uses a numerically controlled oscillator inside the FPGA for initial carrier acquisition which allows for very wide locking bandwidth. After lock is achieved, the external carrier recovery loop takes over and removes any frequency offset in the complex baseband signal by changing the frequency of the DDS. A QPSK modulator was also developed to provide a QPSK signal with known data. The modulator can generate any constellation diagram up to 256 points.
AFRIKAANSE OPSOMMING: Hierdie tesis bespreek die ontwerp en implementasie van ’n sagteware gebaseerde QPSK demodulator met ’n demodulasie spoed van 100 Mbps. Die doelstelling is om ’n topologie te identifiseer vir ’n QPSK demodulator wat ’n hoë datatempo sal toelaat en ook om sinkronisasie algoritmes te ontwikkel vir draer en simbool herkenning. Die QPSK demodulator is geïmplimenteer op ’n Stratix II FPGA van Altera wat kompleks basisband monstering doen op infase en kwadratuur basisband seine. Die basisband seine word gegenereer van ’n 720 MHz QPSK sein met ’n kwadratuur menger wiese uittrees deur puls passende filters gestuur word om die sein tot ruis verhouding te maksimeer. ’n Een gigamonster per sekonde direk digitale sintetiseerder (DDS) is gebruik om die klok vir die analoog na digitaal omsetters te genereer vir sinkrone monstering van die pulse passende filter uittrees. Die demodulator gebruik twee monsters per simbool om ’n QPSK sein te demoduleer. ’n Tweevoudige sluit algoritme word gebruik vir die simbool sinkronisasie waar ’n wyeband filter die inisiële sluit funksie verrig en dan word daar oorgeslaan na ’n nouband filter vir fase volging wat die ruis in die terugvoerlus verminder. Daar is ’n simbool sluit detektor wat identifiseer wanneer die simbool beheerlus gesluit is en selekteer dan die gepaste filter. ’n Tweede DDS en ’n sintetiseerder se uittrees word gemeng om ’n 1.44 GHz draer te genereer vir kohurente frekwensie translasie in die kwadratuur menger. Die draer sinkronisasie gebruik ’n numeries beheerbare ossilator vir die inisiële frekwensie en fase sluit wat baie vinnig geimplenteer kan word omdat dit alles in sagteware binne in die FPGA gebeur. Na die interne draer beheerlus gesluit is, neem die eksterne beheerlus oor om enige fase of frekwensie afsette in die kompleks basisband seine van die kwadratuur menger te verwyder deur die frekwensie van die draer DDS te beheer. ’n QPSK modulator is ook ontwikkel om verwysings data te genereer. Enige konstelasie vorm tot 256 punte kan geimplementeer word.
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Ghuman, Parminder, Salman Sheikh, Steve Koubek, Scott Hoy, and Andrew Gray. "High Rate Digital Demodulator ASIC." International Foundation for Telemetering, 1998. http://hdl.handle.net/10150/609676.
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International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, CaliforniaThe architecture of the High Rate (600 Mega-bits per second) Digital Demodulator (HRDD) ASIC capable of demodulating BPSK and QPSK modulated data is presented in this paper. The advantages of all-digital processing include increased flexibility and reliability with reduced reproduction costs. Conventional serial digital processing would require high processing rates necessitating a hardware implementation other than CMOS technology such as Gallium Arsenide (GaAs) which has high cost and power requirements. It is more desirable to use CMOS technology with its lower power requirements and higher gate density. However, digital demodulation of high data rates in CMOS requires parallel algorithms to process the sampled data at a rate lower than the data rate. The parallel processing algorithms described here were developed jointly by NASA’s Goddard Space Flight Center (GSFC) and the Jet Propulsion Laboratory (JPL). The resulting all-digital receiver has the capability to demodulate BPSK, QPSK, OQPSK, and DQPSK at data rates in excess of 300 Mega-bits per second (Mbps) per channel. This paper will provide an overview of the parallel architecture and features of the HRDR ASIC. In addition, this paper will provide an overview of the implementation of the hardware architectures used to create flexibility over conventional high rate analog or hybrid receivers. This flexibility includes a wide range of data rates, modulation schemes, and operating environments. In conclusion it will be shown how this high rate digital demodulator can be used with an off-the-shelf A/D and a flexible analog front end, both of which are numerically computer controlled, to produce a very flexible, low cost high rate digital receiver.
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Ong, Chin Siang. "Digital phased array architectures for radar and communications based on off-the-shelf wireless technologies." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2004. http://library.nps.navy.mil/uhtbin/hyperion/04Dec%5FOng.pdf.
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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, December 2004.Thesis advisor(s): David C. Jenn, Siew Yam Yeo. Includes bibliographical references (p. 63-64). Also available online.
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Rejnuš, Milan. "Měřicí zesilovač využívající vektorové synchronní detekce." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2014. http://www.nusl.cz/ntk/nusl-221146.
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The master’s thesis describes known methods of signal measurement using principle of synchronous detection. Various methods are presented, their principles are examined and the problems when using them are analyzed. Further, procedures for reduction of adverse effects are described also. Second part of this thesis is focused on the instrument design. The instrument is intended for detection and processing of the output signals in a given optometric system. The proposed device is designed to operate on the principle of synchronous detection method using a vector signal evaluation. Advantages and disadvantages are discussed below.
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Pavlík, Dušan. "Ultrazvukový měřič rychlosti toku krve." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219209.
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This thesis deals with ultrasound blood flow meter design with emphasis on practical implementation of such device. This medical device is used in ultrasound diagnostic, especially for measuring direction and velocity of blood flow in superficial vessels. This thesis contains consecutive design including description of individual function blocks. Documents for making double-sided printed circuit are included as well.
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Temple, Kip. "ADVANCED RANGE TELEMETRY (ARTM) TIER I COMPATIBLE DEMODULATOR TESTING AND RESULTS." International Foundation for Telemetering, 2002. http://hdl.handle.net/10150/606309.
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International Telemetering Conference Proceedings / October 21, 2002 / Town & Country Hotel and Conference Center, San Diego, CaliforniaThe Nova HYPERMOD demodulator operates in three modes, the classic pulse-code modulation/frequency modulation (PCM/FM), sometimes known as continuous phase frequency shift keying (CPFSK) mode, shaped offset quadrature phase shift keying (SOQPSK) mode, and continuous phase modulation (CPM) mode. Of interest to this paper is SOQPSK mode which is a waveform similar to the Advanced Range Telemetry (ARTM) Tier I waveform, Feher’s Quadrature Phase Shift Keying, B version (FQPSK-B) revision (Rev) A1. Also considered is another variant, FQPSK-JR. This paper will outline the cross compatibility and resynchronization speed of these waveforms based upon ARTM-adopted demodulator performance tests. The results of these laboratory tests comparing the HYPERMOD demodulator, the enhanced Tier I demodulator, and the current Tier I reference demodulator, both from RF Networks, will be presented.
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Cope, Michael K. "Design, simulation, and implementation of a digital quadrature demodulator for a stepped frequency radar." Master's thesis, University of Cape Town, 2003. http://hdl.handle.net/11427/10291.
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Includes bibliographical references.The scope of this thesis project is the design and implementation of a digital quadrature demodulator for a stepped frequency ground penetrating radar. This dissertation presents a theoretical model of the demodulator, simulations characterising the demodulator performance as well as the design, construction, and measurement of the prototype demodulator. The demodulator estimates the amplitude and phase of the intermediate frequency signal of a time-interleaved dual-channel heterodyne radar receiver. A demodulator model is developed from a survey of the relevant literature, paying particular attention to errors introduced in sampling. Simulations predict the demodulator performance in the radar system, suggesting coherent integration improves accuracy by reducing the effect of random sampling errors. The design of the prototype and characterisation of its performance are briefly reported.
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Gálvez, Límaco Ángel Manuel. "Demodulação digital usando sinais em quadratura e controle de fase óptica aplicada a um vibrômetro baseado em um interferômetro de Michelson modificado /." Ilha Solteira, 2020. http://hdl.handle.net/11449/192101.
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Orientador: Cláudio KitanoResumo: Nesta dissertação de mestrado é apresentado um vibrômetro para a medição de deslocamentos nanométricos. O vibrômetro proposto está baseado em um interferômetro de Michelson modificado, homódino e em malha fechada. A demodulação em tempo real é executada inteiramente em modo digital, utilizando uma plataforma embarcada que realiza a aquisição de dados, processamento dos sinais, controle PI (proporcional-integral) e a geração dos sinais que acionam o modulador de fase óptica (baseado em uma célula Pockels) e o atuador piezoelétrico sob estudo. Dois sinais em quadratura de fase são obtidos a partir de um único sinal interferométrico utilizando uma tensão de modulação principal e, em seguida, a conhecida técnica de multiplicação cruzada é aplicada para calcular a variação da fase óptica de interesse. A condição de quadratura é atingida pelo próprio controlador PI por meio da análise da figura de Lissajous dos sinais fora de fase. O novo vibrômetro óptico é capaz de medir deslocamentos nanométricos, e é simples, barato, exato, imune ao desvanecimento e auto-consistente. O controlador PI é robusto, uma vez que o método de demodulação é capaz de trabalhar com elevado ruído eletrônico, variações indesejáveis no ganho do amplificador e na tensão de meia-onda da célula Pockels com a temperatura e outras perturbações externas. O novo sistema foi utilizado para determinar a magnitude da resposta em frequência de dois protótipos de atuadores piezoelétricos flextensionais multiatuados. As ... (Resumo completo, clicar acesso eletrônico abaixo)
Abstract: A vibrometer to measure nanometric displacements is presented in this work. The proposed vibrometer is based on a modified closed loop homodyne Michelson interferometer. Real-time phase demodulation is carried out entirely in a digital mode, using an embedded platform that performs data acquisition, signal processing, PI (proportional-integral) control and the generation of signals that drive the electrooptic Pockels cell phase shifter and the piezoelectric actuator under test. Two phase quadrature signals are generated from a single interferometric output, using the interleaving action, in alternation, of a digitally generated principal modulating signal, and then the well-known cross-multiplication technique is applied to perform the computation of the phase shift of interest. The quadrature condition is reached by the PI control itself, using the length difference between the major axis and the minor axis of the ellipse formed by the Lissajous figure associated with the out of phase signals as the controller error signal. The new optical vibrometer is capable of measuring nanometric displacements, and is simple, inexpensive, accurate, immune to fading and self-consistent. The PI controller is robust, since the demodulation method is able to work under high electronic noise, undesirable variations in Pockels cell half-wave voltage with temperature, amplifier gain and other external entrances. The new method was used to determine the displacement frequency response curves of... (Complete abstract click electronic access below)
Mestre
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Rocha, Manuel Mateus e. Silva. "Digital quadrature demodulation of Doppler signals." Master's thesis, 2009. http://hdl.handle.net/10400.1/745.
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Dissertação de mest., Engenharia Electrónica e Telecomunicações, Faculdade de Ciências e Tecnologia, Universidade do Algarve, 2009Ultrasound has for many years been an important tool in the detection and quantification of various health problems. In vascular diseases, for example, the ultrasound can be applied with different techniques such as Transit-Time Flow Measurements (TTFM) [36], Doppler [28][40][41][42] and elastography [37] [38]. Research has been developed focusing the signal processing of Doppler ultrasound signals. In an ongoing project, named Desarrollo de Sistemas Ultras´onicos y Computacionales para Diagn´ostico Cardiovascular (SUCoDiC), Doppler ultrasound signals are processed by an analog signal processing unit, in order to obtain the inphase (I) and quadrature (Q) components of the Doppler ultrasound signals, to allow directional blood flow separation. Problems associated with unbalanced channels’ gain of the employed analog system have been detected, resulting in an inapropriate directional blood flow separation. This thesis reports the research performed to eliminate such problems by substituting the analog system’s demodulator by digital signal processing approaches aiming at the achievement of the same goals, i.e., obtaining the Doppler ultrasound signal’s inphase (I) and quadrature (Q) components, for efficient directional blood flow separation. Five digital quadrature techniques have been studied to achieve such goal. Also, given technical constraints imposed by the nature of the Doppler ultrasound signals to be used, and limitations of the sampling rate of the Analog-to-Digital Converter (ADC) used, two strategies to acquire the Doppler ultrasound signals were studied. Such strategies involved the sampling of a downconversion version of the Doppler ultrasound signals (by application of the heterodyne function) and direct sampling of the Doppler ultrasound signals using uniform bandpass sampling. From the results obtained, three approaches are selected and proposed for real time implementation. Comparison between both signal sampling strategies employed are also presented
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Cheng, Ching-Ta, and 鄭經達. "A Multi-channel Quadrature Demodulation Receiver for Satellite Digital Video Broadcasting systems." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/34527655066279501590.
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碩士國立臺灣海洋大學
電機工程學系
92
In the field of digital video broadcasting, it pursuing better quality video programs of the receiver is not the only goal. There is also increasing need in functions (such as PIP and POP). Satellite digital video broadcasts use transponders on a satellite to provide video programs. They can provide a wide broadcasting range. In addition, the direct to home service is currently under active development. Satellites will become the most popular video broadcasting transmission media. In this thesis, we investigate the satellite digital video broadcasting system. For the purpose of receiving multiple channel programs, traditional satellite receivers have to increase the number of tuners. This increases the complexity and the cost of the circuit. In this paper, we propose a multi-channel digital quadrature demodulation method to solve this problem. The so-called digital quadrature demodulation technique chooses the sample rate for signals via certain rules. The correctly demodulated multiple channel outputs can then be obtained from the sampled signal using simple operations. The whole digital quadrature demodulation process is done in the digital domain. This means that it can be easily realized by software. In addition, if the bandpass sampling is used, we can substantially reduce the sampling frequency. In this paper, we apply the multi-channel quadrature demodulation technique to the satellite digital video broadcasting system and perform simulation to verify the goodness of our design. The simulated result shows that the proposed structure is able to successfully demodulate multiple signals. We expect the proposed receiver structure to be implemented in the near future. Keywords: Quadrature Sampling, Bandpass Sampling, Digital Quadrature Demodulation, Digital Video Broadcast.
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簡秀峰. "A direct-bandpass-sampling based quadrature demodulation method for two distinct RF signals." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/66192244598240383318.
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LEE, CHAN-HUNG, and 李展宏. "Researches of Microwave Oscillator Phase-Noise Measurement and Quadrature-Tracking Demodulator." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/aj597w.
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博士國立高雄第一科技大學
工學院工程科技博士班
106
Measurement is the basis for the development of microwave circuit system and mastering the skill of accurate and good measurement is the key requirement for the development of an excellent microwave system. However, the high cost of microwave measuring instrument often leaves researchers hesitant to continue research and development in the discipline of microwave technology or in their specialty. In order to resolve the problem, this paper proposed and developed two precise and low-cost phase noise measurement technologies, which were injection-locking frequency discriminator and injection-locking six-port frequency discriminator, respectively, to greatly reduce the developmental cost of microwave oscillator phase noise measurement instrument, while it could be applied to the performance verification of Microwave oscillator prototype circuit in general labs. It could also help researchers to accurately understand the characteristics of circuit design. In order to overcome the increase in bit error rate of receiver due to the quadrature phase imbalance of the conventional co-demodulator for the orthogonal frequency division multiplexing (OFDM) system, an advanced quadrature-tracking demodulator was also proposed. The architecture of proposed quadrature-tracking demodulator was mainly composed of two novel QPLLs that could respectively track the IQ phases of the received OFDM signals and simultaneously demodulate them. In order to maintain the quadrature characteristic of the QPLLs, the two PLLs shared the same quadrature voltage-controlled oscillator (QVCO), synchronous tracking of the received OFDM IQ signal. The design of QVCO chip used two sets of cross-coupled pair QVCO with the same differential, while synchronously control and phase tracking the voltage adjustment ports of these two oscillators to ensure the quadrature characteristics of the QVCO output signal. In addition, since OFDM radio frequency receivers of wireless communication system generally adopted direct frequency down-demodulation architecture to reduce the possible impact of DC-offset, the DC subcarriers in the related OFDM communication protocols were not standardized for use. Therefore, with phase-locked loop bandwidth lower than the subcarrier spacing of the OFDM signal, the QPLL coherent demodulation technology proposed in this paper was especially suitable for the receiver architecture of an OFDM system.
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Wang, Tea-Ta, and 王擇達. "Design of CMOS Coherent Quadrature Demodulator and Low Noise Frequency Synthesizer for 4G Systems." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/36602683824910334370.
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碩士國立高雄第一科技大學
電腦與通訊工程研究所
100
This paper proposes a Sub-harmonic technology designs a frequency synthesizer. Compared with the classical frequency synthesizer, the frequency divider dominates the in-band phase noise, which not only have great power consumption in system, but also have 20logN the gain of noise in in-band. The Sub-harmonic frequency synthesizer no frequency divider is needed in locked state. Hence, divider noise and power can be eliminated. The frequency synthesizer is in implemented in TSMC 0.18-um CMOS process, the in-band phase noise at 10kHz offset is measured to be -99.49dBc/Hz. Designs of coherent quadrature demodulator by TSMC 0.18-um CMOS process. The phase noise at 1MHz offset is measured to be -96.91dBc/Hz. When the carrier frequency at 3GHz hop to 3.02GHz, the locked time is 24us. And the carrier frequency at 3.02GHz hopping to 3GHz, the locked time is 26us. Finally, it could combine the quadrature demodulator with QPSK digital demodulation. Design a low noise frequency synthesizer for 4G by TSMC 0.18um CMOS process. This chip frequency band design in 5.3GHz~5.83GHz.This chip has a measured center frequency of 5.565GHz and tuning range of 530MHz.The phase noise at 1MHz offset is measured to be -101.47dBc/Hz.
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Tsai, Hom-Jung, and 蔡泓政. "Polyphase-Filter-Banks Based Carrier and Symbol-Timing Recovery Techniques for Multiband Digital Quadrature Demodulator." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/23060615070721348016.
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碩士國立臺灣海洋大學
電機工程學系
94
In wireless communications systems, the concept of software radio is to reduce the cost of the hardware modifications by implementing most of the receiver functions with software. The digital quadrature demodulation technique is one way to implement the concept of the software radio. This method first samples the modulated signal using a sampling frequency which satisfies certain conditions, then acquire the demodulated signal from the sampled signal via some very simple rules. If a bandpass sampling frequency is adopted, we can substantially lower the sampling frequency. This in turn reduces the cost and the complexity of the receiver. In this thesis, we try to solve the problems of carrier frequency offset and symbol timing synchronization in multiband digital quadrature demodulators. We propose a method to achieve the symbol-timing and carrier recovery by using half band filters, the band-edge filters , and polyphase filter banks. The goodness of the proposed method is demonstrated by computer simulation.
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Huang, Chun-Ying, and 黃俊穎. "Compensation For Gain/Phase Imbalance And DC Offset At Quadrature Modulator And Demodulator With Adaptive Inverse QRD-RLS Algorithm." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/56002730593536820764.
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碩士國立中山大學
電機工程學系研究所
90
There has been much effort in new design for transceiver used in mobile communications. The general approach is to combine RF functions with DSP to allow linear modulation techniques and permit flexibility of modulation format and receiver processing. In practice, with the quadrature modulation technique there is always some imbalance between the I- and Q channels of modulator and demodulator. This is mainly due to finite tolerances of capacitor and resistor values used to implement the analog components. The unavoidable imbalance between the I- and Q channels is known to degrade the performance of quadrature communication system. The main concern of this thesis is to propose a new blind scheme and with fast convergence algorithm, such as the inverse QRD-RLS algorithm, to deal with the problem described above for compensation in the transmitter and receiver. First, for the transmitter, the so-called adaptive estimation and compensation with power measurement implemented by the inverse QRD-RLS algorithm is employed. While in the receiver, a new blind adaptive filtering approach of the nonlinear parameters estimation and compensation, along with the power measurement in the receiver, is devised to adaptively compensate for the gain/phase imbalance and DC offsets in a quadrature demodulator. Where the conventional inverse QRD-RLS algorithm is employed for estimating the parameters of compensator, without using any reference signal transmitted from the transmitter. To document the merits of the proposed scheme, computer simulation for the coherent 16-PSK-communication system is carried out. With our proposed method a great improvement for eliminating the effects of the imbalance and offset over the existing techniques has verified. It has rapidly convergence rate and the smaller mean square error in steady state.
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Su, Huang-Shiang, and 蘇皇祥. "Chips Design of Analog Current-Mode Quadrature Amplitude Modulation Demodulator and Min-Sum Decoder for (8,4) Regular Low-Density Parity-Check Codes." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/796j96.
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碩士國立臺北科技大學
電腦與通訊研究所
97
It was commonly believed that the analog demodulator and decoder have certainly error-correcting capacity and the advantages of low power consumption and lower silicon area. In this thesis, an analog quadrature amplitude modulation (QAM) demodulator and an analog iterative decoder of VLSI architecture design are proposed. First, we design a novel demodulator with analog circuits. The main design blocks are composed of differential pairs and current buffer circuits. The proposed demodulator architecture could transfer the analog input signals from the channel to the location of belonging constellation effectively and convey signals from the output of demodulator to decoder directly. Also, it can remove the analog to digital converter (ADC) device. The second design is the analog decoder architecture for low-density parity-check (LDPC) codes based on min-sum iterative algorithms. Current buffer circuits and check node accuracy issues are focal point for the architecture. We use the advantages of high output impedance and high accuracy to decrease the channel length modulation effect in cascode current buffers. Then, increase the transfer accuracy and decoding performance in the analog decoder. Finally, a novel analog QAM demodulator and a high accuracy LDPC decoder have been implemented with 0.35μm 2P4M CMOS technology. These two chips include 106 and 1944 transistors respectively and operate in 3.3V power supply. The power consumption are 402.9μW and 12.04mW, the core area are 0.14 × 0.13 mm^2 and 0.52 × 0.2 mm^2 respectively. The advantage of demodulator and decoder chips can achieve low power consumption, low cost and proper error correcting capacity that provides an efficient design for SOC integration in the communication receiver in the future.