Relevant bibliographies by topics / Radix -2 modified booth algorithm

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Academic literature on the topic 'Radix -2 modified booth algorithm'

Author: Grafiati
Published: 4 June 2025
Last updated: 1 August 2025

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Journal articles on the topic "Radix -2 modified booth algorithm"

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Md., Zakir Hussain, and Parvin KaziNikhat. "Low power and high performance FFT with different radices." TELKOMNIKA Telecommunication, Computing, Electronics and Control 8, no. 2 (2019): 99–106. https://doi.org/10.11591/ijres.v8.i2.pp99-106.

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FFT is one of the most active blocks in digital signal processing and in various field of communication systems. FFT has received significant attention over the past years to increase its capability and versatility. This paper describes an extensive study on trade-off of different radices with different computational elements of butterfly such as adders and multipliers. Finding an efficient radix along with computational elements is the key point to find best suite i.e. high precision, low power and low area applications like radar, filtering, image compression etc. The work also considers the
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Seo, Young-Ho, and Dong-Wook Kim. "A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18, no. 2 (2010): 201–8. http://dx.doi.org/10.1109/tvlsi.2008.2009113.

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ISHITA, VERMA, GHOSH PRIYANKA, SONI UPENDRA, and SINGH DHARMENDRA. "A HIGH SPEED ARITHMETIC ARCHITECTURE OF PARALLEL MULTIPLIER-ACCUMULATOR (MAC) BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM." i-manager's Journal on Circuits and Systems 5, no. 3 (2017): 38. http://dx.doi.org/10.26634/jcir.5.3.13866.

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Tabasum, S., and M. P. Chennaiah. "A Parallel Multiplier - Accumulator Based On Radix - 2 Modified Booth Algorithm By Using Spurious Power Suppression Tecnique." i-manager's Journal on Embedded Systems 2, no. 1 (2013): 7–13. http://dx.doi.org/10.26634/jes.2.1.2239.

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Ramesh, Addanki Purna. "Efficient Implementation of 16-Bit Multiplier-Accumulator Using Radix-2 Modified Booth Algorithm and SPST Adder Using Verilog." International Journal of VLSI Design & Communication Systems 3, no. 3 (2012): 107–18. http://dx.doi.org/10.5121/vlsic.2012.3310.

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Hussain, Md Zakir, and Kazi Nikhat Parvin. "Low power and high performance FFT with different radices." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 2 (2019): 99. http://dx.doi.org/10.11591/ijres.v8.i2.pp99-106.

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<p>FFT is one of the most active blocks in digital signal processing and in various field of communication systems. FFT has received significant attention over the past years to increase its capability and versatility. This paper describes an extensive study on trade-off of different radices with different computational elements of butterfly such as adders and multipliers. Finding an efficient radix along with computational elements is the key point to find best suite i.e. high precision, low power and low area applications like radar, filtering, image compression etc. The work also cons
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Et. al., C. Padma,. "Energy Efficient Floating Point Fft/Ifft Processor For Mimo-Ofdm Applications." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 10 (2021): 5248–56. http://dx.doi.org/10.17762/turcomat.v12i10.5319.

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There are several methods to accomplish Fast Fourier Transform and Inverse Fast Fourier Transform processor for multiple inputs multiple output-orthogonal frequency division multiplexing applications. It requires high performance and low power implementation methodologies for reducing the hardware complexity and cost. In conventional fixed point arithmetic calculation is complex to utilize because the dynamic range of computations must be limited in order to overcome overflow and under flow problems. This paper presents floating point arithmetic optimization technique to implement radix-2 butt
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WEI, SHUGANG, and KENSUKE SHIMIZU. "MODULO (2p ± 1) MULTIPLIERS USING A THREE-OPERAND MODULAR SIGNED-DIGIT ADDITION ALGORITHM." Journal of Circuits, Systems and Computers 15, no. 01 (2006): 129–44. http://dx.doi.org/10.1142/s0218126606002976.

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In this paper, a new three-operand modulo (2p ± 1) addition is implemented by performing a carry-save addition and a two-operand modular addition based on the p-digit radix-two signed-digit (SD) number system. Thus, the delay time of the three-operand modular adder is independent of the word length of the operands. A modulo (2p ± 1) multiplier is constructed as a ternary tree of the three-operand modular SD adders, and the modular multiplication time is proportional to log 3 p. When a serial modular multiplier is constructed using the three-operand modular SD adder, two modular partial product
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Bentipalli Sekhar, G Appala Naidu, and K. Babulu. "Optimised Implementation of Adaptive Rns Using Power-Aware CRT." International Journal of Maritime Engineering 1, no. 1 (2024): 499–508. http://dx.doi.org/10.5750/ijme.v1i1.1380.

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In order to get an efficient comprehensive analysis on Doppler estimation in RADAR; need an enhanced arithmetic formulation procedure for density, power and latency optimisations. Modular adders and multipliers are very crucial components in the performance of residue number system-based applications. The Residue Number System (RNS) is a non-positional number system that allows parallel computations without transfers between digits. However, some operations in RNS require knowledge of the positional characteristic of a number. Among these operations is the conversion from RNS to the positional
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R., Merlin Princy, and Arun Kumar*2 S. "BEC BASED FFT ARCHITECTURE USING CORDIC ALGORITHM." GLOBAL JOURNAL OF ENGINEERING SCIENCE AND RESEARCHES 4, no. 6 (2017): 11–20. https://doi.org/10.5281/zenodo.802175.

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Digital signal processing method uses non-linear functions such as Discrete cosine transform and Discrete wavelet transfom.Because it is accomplished by repetative application of addition and multiplication,the speed of multiplication and addition arithnetic determines the execution speed and performance of the entire speed. Because the multiplier requirelongest delay in operational blocks. This paper presents multiplier and accumulator (MAC) architecture is used for high speed arithmetic computation in Binary FFT using selective rotation.By combining multiplication with accumulation and devis
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Book chapters on the topic "Radix -2 modified booth algorithm"

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Sivasaravanababu, S., T. R. Dineshkumar, and G. Saravana Kumar. "Assertion Driven Modified Booth Encoding and Post Computation Model for Speed MAC Applications." In Recent Trends in Intensive Computing. IOS Press, 2021. http://dx.doi.org/10.3233/apc210289.

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The Multiply-Accumulate Unit (MAC) is the core computational block in many DSP and wireless application but comes with more complicated architectures. Moreover the MAC block also decides the energy consumption and the performance of the overall design; due to its lies in the maximal path delay critical propagation. Developing high performance and energy optimized MAC core is essential to optimized DSP core. In this work, a high speed and low power signed booth radix enabled MAC Unit is proposed with highly configurable assertion driven modified booth algorithm (AD-MBE). The proposed booth core
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Chopde, Abhay, Sharvari Bodas, Varada Deshmukh, and Shamish Bramhekar. "Fast Inverse Square Root using FPGA." In Advancements in Communication and Systems. Soft Computing Research Society, 2024. http://dx.doi.org/10.56155/978-81-955020-7-3-21.

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The Fast Inverse Square Root (FISR) algorithm, originally introduced in the Quake III source code, accomplishes the vector normalization task required in graphics application through basic multiplication and bit-shifting operations. The core of this algorithm relies on the use of approximation techniques to enhance an initial estimation, which is primarily based on a designated “magic” constant. The implemented Verilog code utilizes the Newton-Raphson iterations, modified booth’s multiplier, and the inverse square root, featuring a core “Inverse Square Root” module with 32-bit input and output
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Conference papers on the topic "Radix -2 modified booth algorithm"

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Sathya, A., S. Fathimabee, and S. Divya. "Parallel multiplier-accumulator based on radix-2 modified Booth algorithm by using a VLSI architecture." In 2014 International Conference on Electronics and Communication Systems (ICECS). IEEE, 2014. http://dx.doi.org/10.1109/ecs.2014.6892605.

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Cho, Ki-seon, Jong-on Park, Jin-seok Hong, and Goang-seog Choi. "54x54-bit radix-4 multiplier based on modified booth algorithm." In the 13th ACM Great Lakes Symposium. ACM Press, 2003. http://dx.doi.org/10.1145/764808.764869.

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Ul Sadad, Nahin, Afsana Afrin, and Md Nazrul Islam Mondal. "Synchronous and Asynchronous Implementation of Radix-2 Booth Multiplication Algorithm." In 2021 3rd International Conference on Electrical & Electronic Engineering (ICEEE). IEEE, 2021. http://dx.doi.org/10.1109/iceee54059.2021.9718783.

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Bansal, Manish, Sangeeta Nakhate, and Ajay Somkuwar. "High Performance Pipelined Signed 64x64-Bit Multiplier Using Radix-32 Modified Booth Algorithm and Wallace Structure." In 2011 International Conference on Computational Intelligence and Communication Networks (CICN). IEEE, 2011. http://dx.doi.org/10.1109/cicn.2011.86.

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Surendran, E. K. Laya, and P. Rony Antony. "Implementation of fast multiplier using modified Radix-4 booth algorithm with redundant binary adder for low energy applications." In 2014 First International Conference on Computational Systems and Communications (ICCSC). IEEE, 2014. http://dx.doi.org/10.1109/compsc.2014.7032660.

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Mukherjee, Biswarup, and Aniruddha Ghosal. "Design and Analysis of a Low Power High-Performance GDI based Radix 4 Multiplier Using Modified Booth Wallace Algorithm." In 2018 IEEE Electron Devices Kolkata Conference (EDKCON). IEEE, 2018. http://dx.doi.org/10.1109/edkcon.2018.8770494.

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