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Journal articles on the topic 'Radix -2 modified booth algorithm'

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Published: 4 June 2025

Last updated: 20 July 2025

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1

Md., Zakir Hussain, and Parvin KaziNikhat. "Low power and high performance FFT with different radices." TELKOMNIKA Telecommunication, Computing, Electronics and Control 8, no. 2 (2019): 99–106. https://doi.org/10.11591/ijres.v8.i2.pp99-106.

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FFT is one of the most active blocks in digital signal processing and in various field of communication systems. FFT has received significant attention over the past years to increase its capability and versatility. This paper describes an extensive study on trade-off of different radices with different computational elements of butterfly such as adders and multipliers. Finding an efficient radix along with computational elements is the key point to find best suite i.e. high precision, low power and low area applications like radar, filtering, image compression etc. The work also considers the

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2

Seo, Young-Ho, and Dong-Wook Kim. "A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18, no. 2 (2010): 201–8. http://dx.doi.org/10.1109/tvlsi.2008.2009113.

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3

ISHITA, VERMA, GHOSH PRIYANKA, SONI UPENDRA, and SINGH DHARMENDRA. "A HIGH SPEED ARITHMETIC ARCHITECTURE OF PARALLEL MULTIPLIER-ACCUMULATOR (MAC) BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM." i-manager's Journal on Circuits and Systems 5, no. 3 (2017): 38. http://dx.doi.org/10.26634/jcir.5.3.13866.

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4

Tabasum, S., and M. P. Chennaiah. "A Parallel Multiplier - Accumulator Based On Radix - 2 Modified Booth Algorithm By Using Spurious Power Suppression Tecnique." i-manager's Journal on Embedded Systems 2, no. 1 (2013): 7–13. http://dx.doi.org/10.26634/jes.2.1.2239.

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5

Ramesh, Addanki Purna. "Efficient Implementation of 16-Bit Multiplier-Accumulator Using Radix-2 Modified Booth Algorithm and SPST Adder Using Verilog." International Journal of VLSI Design & Communication Systems 3, no. 3 (2012): 107–18. http://dx.doi.org/10.5121/vlsic.2012.3310.

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6

Hussain, Md Zakir, and Kazi Nikhat Parvin. "Low power and high performance FFT with different radices." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 2 (2019): 99. http://dx.doi.org/10.11591/ijres.v8.i2.pp99-106.

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<p>FFT is one of the most active blocks in digital signal processing and in various field of communication systems. FFT has received significant attention over the past years to increase its capability and versatility. This paper describes an extensive study on trade-off of different radices with different computational elements of butterfly such as adders and multipliers. Finding an efficient radix along with computational elements is the key point to find best suite i.e. high precision, low power and low area applications like radar, filtering, image compression etc. The work also cons

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7

Et. al., C. Padma,. "Energy Efficient Floating Point Fft/Ifft Processor For Mimo-Ofdm Applications." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 10 (2021): 5248–56. http://dx.doi.org/10.17762/turcomat.v12i10.5319.

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There are several methods to accomplish Fast Fourier Transform and Inverse Fast Fourier Transform processor for multiple inputs multiple output-orthogonal frequency division multiplexing applications. It requires high performance and low power implementation methodologies for reducing the hardware complexity and cost. In conventional fixed point arithmetic calculation is complex to utilize because the dynamic range of computations must be limited in order to overcome overflow and under flow problems. This paper presents floating point arithmetic optimization technique to implement radix-2 butt

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WEI, SHUGANG, and KENSUKE SHIMIZU. "MODULO (2p ± 1) MULTIPLIERS USING A THREE-OPERAND MODULAR SIGNED-DIGIT ADDITION ALGORITHM." Journal of Circuits, Systems and Computers 15, no. 01 (2006): 129–44. http://dx.doi.org/10.1142/s0218126606002976.

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In this paper, a new three-operand modulo (2p ± 1) addition is implemented by performing a carry-save addition and a two-operand modular addition based on the p-digit radix-two signed-digit (SD) number system. Thus, the delay time of the three-operand modular adder is independent of the word length of the operands. A modulo (2p ± 1) multiplier is constructed as a ternary tree of the three-operand modular SD adders, and the modular multiplication time is proportional to log 3 p. When a serial modular multiplier is constructed using the three-operand modular SD adder, two modular partial product

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Bentipalli Sekhar, G Appala Naidu, and K. Babulu. "Optimised Implementation of Adaptive Rns Using Power-Aware CRT." International Journal of Maritime Engineering 1, no. 1 (2024): 499–508. http://dx.doi.org/10.5750/ijme.v1i1.1380.

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In order to get an efficient comprehensive analysis on Doppler estimation in RADAR; need an enhanced arithmetic formulation procedure for density, power and latency optimisations. Modular adders and multipliers are very crucial components in the performance of residue number system-based applications. The Residue Number System (RNS) is a non-positional number system that allows parallel computations without transfers between digits. However, some operations in RNS require knowledge of the positional characteristic of a number. Among these operations is the conversion from RNS to the positional

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10

R., Merlin Princy, and Arun Kumar*2 S. "BEC BASED FFT ARCHITECTURE USING CORDIC ALGORITHM." GLOBAL JOURNAL OF ENGINEERING SCIENCE AND RESEARCHES 4, no. 6 (2017): 11–20. https://doi.org/10.5281/zenodo.802175.

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Digital signal processing method uses non-linear functions such as Discrete cosine transform and Discrete wavelet transfom.Because it is accomplished by repetative application of addition and multiplication,the speed of multiplication and addition arithnetic determines the execution speed and performance of the entire speed. Because the multiplier requirelongest delay in operational blocks. This paper presents multiplier and accumulator (MAC) architecture is used for high speed arithmetic computation in Binary FFT using selective rotation.By combining multiplication with accumulation and devis

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11

RAO, VISHWAS M., and BEHROUZ NOWROUZIAN. "AN ALTERNATIVE PROOF OF MODIFIED-BOOTH RECODING ALGORITHM BASED ON NUMBER-DOMAIN TRANSFORMATIONS." Journal of Circuits, Systems and Computers 10, no. 01n02 (2000): 23–26. http://dx.doi.org/10.1142/s0218126600000056.

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In this letter, the nonredundant radix-4 representation of two's complement numbers is exploited to develop an alternative proof for the modified-Booth recoding algorithm. This proof is established by showing that the modified-Booth recoding algorithm essentially amounts to successive transformations of the number from its two's complement to its nonredundant radix-4 representation and from its nonredundant radix-4 to its modified radix-4 signed-digit representation. The salient feature of these transformations is that the digits in the resulting modified radix-4 signed-digit number take on va

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12

Mokhtar, Anis Shahida, Chew Sue Ping, Muhamad Faiz Md Din, Nazrul Fariq Makmor, and Muhammad Asyraf Che Mahadi. "Implementation of Booth Multiplier Algorithm using Radix-4 in FPGA." Jurnal Kejuruteraan si4, no. 1 (2021): 161–65. http://dx.doi.org/10.17576/jkukm-2021-si4(1)-20.

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This paper presentsthe performance of Radix-4 Modified Booth Algorithm. Booth algorithm is a multiplication algorithm that multiplies two signed binary numbers in two's complement notation. Multiplier is a fundamental component in general-purpose microprocessors and in digital signal processors. With advances in technology, researchers design multipliers which offer high speed, low power, and less area implementation. Booth multiplier algorithm is designed to reduce number of partial products as compared to conventional multiplier. The proposed design is simulated by using Verilog HDL in Quart

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13

Madrid, P. E., B. Millar, and E. E. Swartzlander. "Modified Booth algorithm for high radix fixed-point multiplication." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1, no. 2 (1993): 164–67. http://dx.doi.org/10.1109/92.238420.

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14

Kim, Hyunpil, Sangook Moon, and Yongsurk Lee. "Radix-16 Booth multiplier using novel weighted 2-stage Booth algorithm." IEICE Electronics Express 11, no. 13 (2014): 20140407. http://dx.doi.org/10.1587/elex.11.20140407.

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15

Dhumal, Ashwini K., and Prof Shirgan S.S. "Comparison between Radix-2 and Radix -4 based on Booth Algorithm." IJARCCE 5, no. 12 (2016): 498–500. http://dx.doi.org/10.17148/ijarcce.2016.512113.

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16

Katti, R. "A modified Booth algorithm for high radix fixed-point multiplication." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2, no. 4 (1994): 522–24. http://dx.doi.org/10.1109/92.335021.

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17

Mohanapriya, R., K. Rajesh, and P. S. Sudarshana. "A Modified Architecture of Multiplier and Accumulator using Radix-4 Modified Booth Algorithm." i-manager's Journal on Circuits and Systems 2, no. 4 (2014): 1–6. http://dx.doi.org/10.26634/jcir.2.4.3218.

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18

SHIN, Ji-Hye, and Young-Beom JANG. "A New DA Implementation Technique for Digital Filters Using Radix-16 Modified Booth Algorithm." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E94-A, no. 4 (2011): 1136–39. http://dx.doi.org/10.1587/transfun.e94.a.1136.

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19

Mary, S. Angel Latha, and N. Dharani. "An Efficient Area and Power 2D-DWT Lifting using Radix-8 Modified Booth Algorithm." International Journal of Communication and Networking System 003, no. 001 (2014): 1–5. http://dx.doi.org/10.20894/ijcnes.103.003.001.001.

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20

Kollannur, Manju Inasu, and Oudaya Coumar Souprayen. "Designing high power efficient finite impulse response filters with three-four inexact adder-integrated Booth multiplier." IAES International Journal of Robotics and Automation (IJRA) 14, no. 2 (2025): 204. https://doi.org/10.11591/ijra.v14i2.pp204-213.

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Finite impulse response (FIR) filters are widely utilized in several applications in digital signal processing, including data transmission, photography, digital audio, and biomedicine. It is necessary to use high sample rates for FIR filters, while moderate sample rates are needed for low-power circuits. To solve these problems, a Booth multiplier based on three-four inexact adder-based multiplication (TFIE-BM) was proposed. The goal of the proposed TFIE-based FIR Booth multiplier is to lower area usage, latency, and power consumption. The proposed method utilizes the spotted hyena optimizer

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21

Liu, Chenghao, Jingyu Sun, and Ruihong Tang. "A design of multiplier based on Radix_4 Booth algorithm and 4-2 Wallace compression tree." Applied and Computational Engineering 37, no. 1 (2024): 166–76. http://dx.doi.org/10.54254/2755-2721/37/20230498.

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In a multitude of computational and signal processing scenarios, the multiplier functions as a fundamental arithmetic component. Given the complex hardware arrangement of multipliers and their usual positioning within the crucial pathway of digital systems, their significance is substantial. Therefore, approximations of multipliers can greatly optimize system performance. This essay examines the fundamental ideas behind the Wallace tree, the Carry ahead adder, and the Radix-4 Booth algorithm. Additionally, instead of the more common 3-2 compressors, a Wallace tree structure with 4-2 compressor

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22

janweja, Preety, and Vipin gupta. "A noval Approch of area efficient and fast radix 2^3 means (8) modified booth multiplier." IOSR journal of VLSI and Signal Processing 4, no. 4 (2014): 14–18. http://dx.doi.org/10.9790/4200-04431418.

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23

Vishwanath, G. "Efficient Hardware Architecture for Ultra-High Sampling Rate FFT Analysis of Acoustic Emission Signals." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 11, no. 3 (2020): 2633–42. http://dx.doi.org/10.61841/turcomat.v11i3.14429.

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In the realm of ultra-high sampling rates, Fast Fourier Transform (FFT) stands as a cornerstone in analyzing acoustic emission signals. This manuscript presents an efficient hardware architecture tailored for executing FFT using the radix-2 Frequency Decimation Algorithm (R2DIF) and a channelled method facilitating effective data sharing via shift registers. The architecture employs an optimal rotation method leveraging the modified Digital Coordinate Rotation Computer Algorithm (mCORDIC) and Radix-2r, dependent on the coding scheme, to replace complex multipliers in FFT computation. The integ

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24

Asadi, Pouya. "A New Array Multiplier Using an Optimized Carry Network and Dynamic CMOS Technology." Journal of Circuits, Systems and Computers 25, no. 02 (2015): 1650004. http://dx.doi.org/10.1142/s0218126616500043.

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In this paper, a new multiplier using array architecture and a fast carry network tree is presented which uses dynamic CMOS technology. Different reforms are performed in multiplier architecture. In the first step of multiplier operator, a novel radix-16 modified Booth encoder is presented which reduces the number of partial products efficiently. In this research, we present a new algorithm for partial product reduction in multiplication operations. The algorithm is based on the implementation of compressor elements by means of carry network. The structure of these compressors into reduction t

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25

Kavitha, G., B. Kirthiga, and N. Kirubanandasarathy. "Performance Analysis of an Area Efficient and Low Power MOD-R2MDC FFT for MIMO OFDM." Applied Mechanics and Materials 573 (June 2014): 176–80. http://dx.doi.org/10.4028/www.scientific.net/amm.573.176.

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In this paper, an area-efficient low power fast fourier transform (FFT) processor is proposed for multi input multi output-orthogonal frequency division multiplexing (MIMO-OFDM) in wireless communication system. It consists of a modified architecture of radix-2 algorithm which is described as modified radix-2 multipath delay commutation (MOD-R2MDC). The OFDM receiver with modified R2MDC (MOD-R2MDC) FFT was designed by Hardware Description Language (HDL) coding The Xilinx ISE Design Suite 10.1 is used as a synthesis tool for getting the power and area. The Model-Sim 6.3c is used for simulation.

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26

Siddiq, F., H. Jamal, T. Muhammad, and M. Iqbal. "Area Efficient Radix 4 2 64 Point Pipeline FFT Architecture Using Modified CSD Multiplier." Nucleus 51, no. 3 (2014): 345–53. https://doi.org/10.71330/thenucleus.2014.689.

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A modified Fast Fourier Transform (FFT) based radix 42 algorithm for Orthogonal Frequency Division Multiplexing (OFDM) systems is presented. When compared with similar schemes like Canonic signed digit (CSD) Constant Multiplier, the modified CSD multiplier can provide a improvement of more than 36% in terms of multiplicative complexity. In Comparison of area being occupied the amount of full adders is reduced by 32% and amount of half adders is reduced by 42%. The modified CSD multiplier scheme is implemented on Xilinx ISE 10.1 using Spartan-III XC3S1000 FPGA as a target device. The synthesis

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27

Kuo, Chao-Tsung, and Yao-Cheng Wu. "Area-Power-Delay-Efficient Multi-Modulus Multiplier Based on Area-Saving Hard Multiple Generator Using Radix-8 Booth-Encoding Scheme on Field Programmable Gate Array." Electronics 13, no. 2 (2024): 311. http://dx.doi.org/10.3390/electronics13020311.

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A multi-modulus architecture based on the radix-8 Booth encoding of a modulo (2n − 1) multiplier, a modulo (2n) multiplier, and a modulo (2n + 1) multiplier is proposed in this paper. It uses the original single circuit and shares many common circuit characteristics with a small extra circuit to carry out multi-modulus operations. Compared with a previous radix-4 study, the radix-8 architecture can increase the modulation multiplication encoding selection from three codes to four codes. This reduces the use of partial products from ⌊n/2⌋ to ⌊n/3⌋ + 1, but it increases the operation complexity

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28

Banerjee, Sandip, Yair Bartal, Lee-Ad Gottlieb, and Alon Hovav. "Improved Fixed-Parameter Bounds for Min-Sum-Radii and Diameters k-Clustering and Their Fair Variants." Proceedings of the AAAI Conference on Artificial Intelligence 39, no. 15 (2025): 15481–88. https://doi.org/10.1609/aaai.v39i15.33699.

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We provide improved upper and lower bounds for the Min-Sum-Radii (MSR) and Min-Sum-Diameters (MSD) clustering problems with a bounded number of clusters k. In particular, we propose an exact MSD algorithm with running-time n^O(k). We also provide (1 + Ɛ) approximation algorithms for both MSR and MSD with running-times of O(kn) + (1/Ɛ)^O(dk) in metrics spaces of doubling dimension d. Our algorithms extend to k-center, improving upon previous results, and to α-MSR, where radii are raised to the α power for α > 1. For α-MSD we prove an exponential time ETH-based lower bound for α > log 3. A

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Montoya-Andrade, D. A., J. A. Rosendo-Macías, and A. Gómez-Expósito. "Efficient computation of the short-time DFT based on a modified radix-2 decimation-in-frequency algorithm." Signal Processing 92, no. 10 (2012): 2525–31. http://dx.doi.org/10.1016/j.sigpro.2012.03.018.

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30

Annapurna, Band Tiwari* Saurabh Sharma. "DESIGN AND DEVELOPMENT OF HYBRID MAC BASED ON CSCS." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 8 (2016): 312–24. https://doi.org/10.5281/zenodo.59642.

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FPGA based MAC has evolved into significant research field within engineering that encompasses the science of signal processing for developing a real-time digital analysis system. Due to the dynamic nature of applications, the MAC unit should offer low processing time and high resource optimization. In this paper, we propose novel multiplier-accumulator (MAC) hybrid architecture based on CSA with focus on development and advancement involving image/video processing based algorithms and other digital constraints. Many of the existing approaches rely on basic factor multiplication and accumulati

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31

Nguyen, Hung, Sheraz Khan, Cheol-Hong Kim, and Jong-Myon Kim. "A Pipelined FFT Processor Using an Optimal Hybrid Rotation Scheme for Complex Multiplication: Design, FPGA Implementation and Analysis." Electronics 7, no. 8 (2018): 137. http://dx.doi.org/10.3390/electronics7080137.

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The fast Fourier transform (FFT) is the most prevalent algorithm for the spectral analysis of acoustic emission signals acquired at ultra-high sampling rates to monitor the condition of rotary machines. The complexity and cost of the associated hardware limit the use of FFT in real-time applications. In this paper, an efficient hardware architecture for FFT implementation is proposed based on the radix-2 decimation in frequency algorithm (R2DIF) and a feedback pipelined technique (FB) that allows effective sharing of storage between the input and output data at each stage of the FFT process vi

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32

Kim, Haechan, Jinmoo Heo, Seongjoo Lee, and Yunho Jung. "SARDIMM: High-Speed Near-Memory Processing Architecture for Synthetic Aperture Radar Imaging." Applied Sciences 14, no. 17 (2024): 7601. http://dx.doi.org/10.3390/app14177601.

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The range-Doppler algorithm (RDA), a key technique for generating synthetic aperture radar (SAR) images, offers high-resolution images but requires significant memory resources and involves complex signal processing. Moreover, the multitude of fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) operations in RDA necessitates high bandwidth and lacks data reuse, leading to bottlenecks. This paper introduces a synthetic aperture radar dual in-line memory module (SARDIMM), which executes RDA operations near memory via near-memory processing (NMP), thereby effectively reducing m

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33

Frederick, Ojiemhende Ehiagwina, Olashile Afolabi Lateef, Mustapha Khadijat, Raheem Kabirat, Jamiu Jibola Anifowose, and O. Salaudeen Wasiu. "A Study on the Performance of GA-Holt-Winters Model in 900 MHz Spectrum Prediction." International Journal of Novel Research in Electrical and Mechanical Engineering 9, no. 1 (2022): 23–31. https://doi.org/10.5281/zenodo.6832380.

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<strong>Abstract:</strong> Continuous spectrum measurement is expensive and time consuming. This has necessitated the concept of spectrum prediction. Spectrum prediction uses historically observed data from spectrum sensing to forecast future channel states. In this research the suitability of the genetic algorithm modified Holt-Winters exponential model in the prediction of spectrum occupancy data was investigated. Minute spectrum duty cycle of selected locations in Ilorin, Nigeria was used in the evaluation of the forecast behaviour of the methods. It was observed that GA-Holt-Winter techniq

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Bagde, Vandana, and Dethe C. G. "Performance improvement of space diversity technique using space time block coding for time varying channels in wireless environment." International Journal of Intelligent Unmanned Systems 10, no. 2/3 (2020): 278–86. http://dx.doi.org/10.1108/ijius-04-2019-0026.

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PurposeA recent innovative technology used in wireless communication is recognized as multiple input multiple output (MIMO) communication system and became popular for quicker data transmission speed. This technology is being examined and implemented for the latest broadband wireless connectivity networks. Though high-capacity wireless channel is identified, there is still requirement of better techniques to get increased data transmission speed with acceptable reliability. There are two types of systems comprising of multi-antennas placed at transmitting and receiving sides, of which first is

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Addanki, Purna Ramesh, N. Tilak A.V., and Dr.A.M.Prasad. "EFFICIENT IMPLEMENTATION OF 16-BIT MULTIPLIER-ACCUMULATOR USING RADIX-2 MODIFIED BOOTH ALGORITHM AND SPST ADDER USING VERILOG." June 30, 2012. https://doi.org/10.5121/vlsic.2012.3310.

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In this paper, we propose a new multiplier-and-accumulator (MAC) architecture for low power and high speed arithmetic. High speed and low power MAC units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. For improving the speed and reducing the dynamic power, there is a need to reduce the glitches (1 to 0 transition) and spikes (0 to 1 transition). Adder designed using spurious power suppression technique (SPST) avoids the unwanted glitches and spikes, thus minimizing the switching power dissipation and hen

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36

"Design of Multiplier through Modified Booth Algorithm with Mig Gate." International Journal of Innovative Technology and Exploring Engineering 9, no. 2 (2019): 3101–5. http://dx.doi.org/10.35940/ijitee.b7476.129219.

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This paper compares different Booth multipliers i.e., Radix-2, 4, 8 is designed using a new carry look-Ahead adder (CLA). In this Delay and Power have been compared and the main aim behind the project is developing Booth multiplier using Reversible Logic Gate (RLG).While comparing with the normal multiplication, Modified Booth Algorithm gives the less amount of delay as the number of partial products gets reduced. In this process CLA is used to reduce the overall multiplier Delay.The reversible logic is considered because it reduces the circuit complexity, loss of information and power consump

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Sathish, Mr M. V., and Mrs Sailaja. "VLSI ARCHITECTURE OF PARALLEL MULTIPLIER– ACCUMULATOR BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM." International Journal of Electronics and Electical Engineering, July 2012, 40–46. http://dx.doi.org/10.47893/ijeee.2012.1009.

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A new architecture of multiplier-andaccumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposing method CSA tree uses 1’s-complement-based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The proposed MAC showed the superior properties to the standard design in

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38

Bala, P. Sasi, and S. Raghavendra. "A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm." International Journal of Instrumentation Control and Automation, October 2011, 196–202. http://dx.doi.org/10.47893/ijica.2011.1036.

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In this paper, we proposed a new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic.By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposed CSA tree uses 1’s-complement-based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The CSA propagates the carries to the least significan

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Альтман, Е. А. "A method of reducing the number of operations in a fast Fourier transform algorithm." Вычислительные технологии, no. 3(23) (August 17, 2018). http://dx.doi.org/10.25743/ict.2018.3.15955.

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Рассмотрен способ сокращения числа арифметических операций в алгоритме быстрого преобразования Фурье (БПФ). Способ основан на сокращении числа операций с поворачивающими множителями. Он применим для алгоритмов БПФ по основанию 2, использующих четырехточечные преобразования. Представлен новый алгоритм БПФ с меньшим по сравнению с ранее известными алгоритмами числом операций. Приведена реализация алгоритма на языке Python. The purpose of this work is studying of methods to reduce the number of calculations which must be performed to calculate the fast Fourier transform (FFT). These methods optim

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Альтман, Е. А. "A method of reducing the number of operations in a fast Fourier transform algorithm." Вычислительные технологии, no. 3(23) (August 17, 2018). http://dx.doi.org/10.25743/ict.2018.3.15955.

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Рассмотрен способ сокращения числа арифметических операций в алгоритме быстрого преобразования Фурье (БПФ). Способ основан на сокращении числа операций с поворачивающими множителями. Он применим для алгоритмов БПФ по основанию 2, использующих четырехточечные преобразования. Представлен новый алгоритм БПФ с меньшим по сравнению с ранее известными алгоритмами числом операций. Приведена реализация алгоритма на языке Python. The purpose of this work is studying of methods to reduce the number of calculations which must be performed to calculate the fast Fourier transform (FFT). These methods optim

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M N, Meghana, Mallikarjuna R. Mulimani, Shiva prasad A S, Venkatesh R, and Vignesh D. "Comparison of Modified Booth Multiplier Techniques." International Journal of Innovative Science and Research Technology, June 3, 2025, 3017–22. https://doi.org/10.38124/ijisrt/25may1725.

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Booth's Algorithm is a multiplication algorithm used to perform signed binary multiplication efficiently. It minimizes the number of addition and subtraction operations by encoding runs of consecutive ones in the binary representation of a multiplier. This algorithm uses a technique called radix-4 encoding, which reduces the number of required arithmetic operations compared to standard long multiplication. Booth's Algorithm is widely used in computer arithmetic, especially in hardware multipliers, due to its ability to handle both positive and negative numbers uniformly. This paper provides an

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SANJEEVARAO, K., and A. RAMKUMAR. "CRBBE ALGORITHM FOR LOW POWER AND HIGH SPEED MULTIPLIER DESIGN." International Journal of Electronics Signals and Systems, October 2014, 104–8. http://dx.doi.org/10.47893/ijess.2014.1206.

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With the advent of the VLSI technology, designers could design simple chips with the more number of transistors. multipliers have large area, long latency and consume considerable power. Reduction of power consumption makes a device reliable. and The use of redundant binary (RB) arithmetic in the design of high-speed digital multipliers is beneficial due to its high modularity and carry-free addition, a high-radix-modified booth encoding algorithm is desired. However its use is hampered by the complexity of generating the hard multiples and the overheads resulting from negative multiples and n

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"Design and Analysis of Multipliers using Radix-8 Booth Encoding Technique for Low Power and Area Consumption." International Journal of Innovative Technology and Exploring Engineering 9, no. 2 (2019): 2630–35. http://dx.doi.org/10.35940/ijitee.b7284.129219.

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As innovation scaling is arriving at its points of confinement, new methodologies have been proposed for computational efficiency. Different techniques have been proposed with advancements in technology to model high-speed along with low power consumption and smaller area multipliers. For the radix-4 booth propagation algorithm for low-power and low complexity applications, an efficient approximate 8 bit redundant multiplier is used. To minimize the complication present in modified booth encoder, approximate Booth RB encoders have been introduced by modifying the truth table with incorrect bit

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"Path Delay Optimized Booth Radix-8 Architecture." International Journal of Recent Technology and Engineering 8, no. 2S5 (2019): 235–37. http://dx.doi.org/10.35940/ijrte.b1048.0782s519.

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In this paper, a quick and low power marked MAC Unit is proposed with reconfigurable Modified stall calculation (MBE). The proposed engineering depends on adjusted corner radix-8 with consolidated 2's supplement and MUX units with a low basic way postponement and low equipment multifaceted nature. Here corner-based methodology for incomplete items ages and Tree based methodology for halfway items decrease in increases. The new decreases design the equipment intricacy of the summation arrange utilizing consolidated swell convey viper and convey look forward (CLA), along these lines lessens the

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Nikhare, Mr Hemantkumar H., and Prof Ashish Singhadia. "Simulation Analysis of 2-D Discrete Wavelet Transform by using Modified Radix-4 Booth Multiplier." IJARCCE, March 30, 2015, 278–85. http://dx.doi.org/10.17148/ijarcce.2015.4368.

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Changela, Ankur, Yogesh Kumar, Marcin Woźniak, Jana Shafi, and Muhammad Fazal Ijaz. "Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations." Scientific Reports 13, no. 1 (2023). http://dx.doi.org/10.1038/s41598-023-47890-3.

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AbstractIn this article, a low-complexity VLSI architecture based on a radix-4 hyperbolic COordinate Rotion DIgital Computer (CORDIC) is proposed to compute the $$N{{\rm th}}$$ N th root and $$N{{\rm th}}$$ N th power of a fixed-point number. The most recent techniques use the radix-2 CORDIC algorithm to compute the root and power. The high computation latency of radix-2 CORDIC is the primary concern for the designers. $$N{{\rm th}}$$ N th root and $$N{{\rm th}}$$ N th power computations are divided into three phases, and each phase is performed by a different class of the proposed modified ra

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C., Paramasivam, and B. Jayanthi K. "Modified Scaling-Free CORDIC Based Pipelined Parallel MDC FFT and IFFT Architecture for Radix 2^2 Algorithm." January 3, 2016. https://doi.org/10.5281/zenodo.1111797.

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An innovative approach to develop modified scaling free CORDIC based two parallel pipelined Multipath Delay Commutator (MDC) FFT and IFFT architectures for radix 2<sup>2</sup> FFT algorithm is presented. Multipliers and adders are the most important data paths in FFT and IFFT architectures. Multipliers occupy high area and consume more power. In order to optimize the area and power overhead, modified scaling-free CORDIC based complex multiplier is utilized in the proposed design. In general twiddle factor values are stored in RAM block. In the proposed work, modified scaling-free CORDIC based

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"A Modified FFT Algorithm for OFDM Based Wireless System." International Journal of Innovative Technology and Exploring Engineering 9, no. 2S5 (2020): 10–14. http://dx.doi.org/10.35940/ijitee.b1003.1292s519.

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The constrained open range and the wastefulness in the range use in a fixed range task strategy, requests another correspondence model to abuse the present remote range unquestionably. This new structures connection point of view is accumulated as bleeding edge sifts through moreover as Dynamic Spectrum Access (DSA) and shrewd radio systems. The FFT and its turn IFFT are fundamental estimations in signal overseeing, programming portrayed radio, and the most encouraging change framework for example Symmetrical OFDM. From the normal organization of OFDM we can locate to FFT/ IFFT modules expect

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Suhasini, M., K. Prabhu Kumar, and P. Srinivas. "Multiplier Design and Performance Estimation with Distributed Arithmetic Algorithm." International Journal of Computer and Communication Technology, April 2016, 90–95. http://dx.doi.org/10.47893/ijcct.2016.1345.

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A new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposed CSA tree uses 1’scomplement- based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. Moreover, depending on data switching activity statistically reduce the power co

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Verba, V. S., V. I. Merkulov, and V. S. Chernov. "Methods of trajectory control of observation in air-based angle-measuring two-position radio monitoring systems. Part 2. Gradient methods." Achievements of Modern Radioelectronics, 2021. http://dx.doi.org/10.18127/j20700784-202109-01.

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To control and monitor the electronic situation, air-based passive angle-measuring two-position systems radio monitoring can be used. A feature of the functioning of these systems is the fact that the accuracy of the estimation of the coordinates and parameters of the movement of radio emission sources (RES) depends largely on the configuration of the relative position of the receiving positions placed on the aircraft and the RES. Therefore, the problem of optimization the relative position of aircraft and AIR is relevant, and various gradient methods of trajectory control of observation have

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