Journal articles on the topic 'Radix -2 modified booth algorithm'
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Md., Zakir Hussain, and Parvin KaziNikhat. "Low power and high performance FFT with different radices." TELKOMNIKA Telecommunication, Computing, Electronics and Control 8, no. 2 (2019): 99–106. https://doi.org/10.11591/ijres.v8.i2.pp99-106.
Full textSeo, Young-Ho, and Dong-Wook Kim. "A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18, no. 2 (2010): 201–8. http://dx.doi.org/10.1109/tvlsi.2008.2009113.
Full textISHITA, VERMA, GHOSH PRIYANKA, SONI UPENDRA, and SINGH DHARMENDRA. "A HIGH SPEED ARITHMETIC ARCHITECTURE OF PARALLEL MULTIPLIER-ACCUMULATOR (MAC) BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM." i-manager's Journal on Circuits and Systems 5, no. 3 (2017): 38. http://dx.doi.org/10.26634/jcir.5.3.13866.
Full textTabasum, S., and M. P. Chennaiah. "A Parallel Multiplier - Accumulator Based On Radix - 2 Modified Booth Algorithm By Using Spurious Power Suppression Tecnique." i-manager's Journal on Embedded Systems 2, no. 1 (2013): 7–13. http://dx.doi.org/10.26634/jes.2.1.2239.
Full textRamesh, Addanki Purna. "Efficient Implementation of 16-Bit Multiplier-Accumulator Using Radix-2 Modified Booth Algorithm and SPST Adder Using Verilog." International Journal of VLSI Design & Communication Systems 3, no. 3 (2012): 107–18. http://dx.doi.org/10.5121/vlsic.2012.3310.
Full textHussain, Md Zakir, and Kazi Nikhat Parvin. "Low power and high performance FFT with different radices." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 2 (2019): 99. http://dx.doi.org/10.11591/ijres.v8.i2.pp99-106.
Full textEt. al., C. Padma,. "Energy Efficient Floating Point Fft/Ifft Processor For Mimo-Ofdm Applications." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 10 (2021): 5248–56. http://dx.doi.org/10.17762/turcomat.v12i10.5319.
Full textWEI, SHUGANG, and KENSUKE SHIMIZU. "MODULO (2p ± 1) MULTIPLIERS USING A THREE-OPERAND MODULAR SIGNED-DIGIT ADDITION ALGORITHM." Journal of Circuits, Systems and Computers 15, no. 01 (2006): 129–44. http://dx.doi.org/10.1142/s0218126606002976.
Full textBentipalli Sekhar, G Appala Naidu, and K. Babulu. "Optimised Implementation of Adaptive Rns Using Power-Aware CRT." International Journal of Maritime Engineering 1, no. 1 (2024): 499–508. http://dx.doi.org/10.5750/ijme.v1i1.1380.
Full textR., Merlin Princy, and Arun Kumar*2 S. "BEC BASED FFT ARCHITECTURE USING CORDIC ALGORITHM." GLOBAL JOURNAL OF ENGINEERING SCIENCE AND RESEARCHES 4, no. 6 (2017): 11–20. https://doi.org/10.5281/zenodo.802175.
Full textRAO, VISHWAS M., and BEHROUZ NOWROUZIAN. "AN ALTERNATIVE PROOF OF MODIFIED-BOOTH RECODING ALGORITHM BASED ON NUMBER-DOMAIN TRANSFORMATIONS." Journal of Circuits, Systems and Computers 10, no. 01n02 (2000): 23–26. http://dx.doi.org/10.1142/s0218126600000056.
Full textMokhtar, Anis Shahida, Chew Sue Ping, Muhamad Faiz Md Din, Nazrul Fariq Makmor, and Muhammad Asyraf Che Mahadi. "Implementation of Booth Multiplier Algorithm using Radix-4 in FPGA." Jurnal Kejuruteraan si4, no. 1 (2021): 161–65. http://dx.doi.org/10.17576/jkukm-2021-si4(1)-20.
Full textMadrid, P. E., B. Millar, and E. E. Swartzlander. "Modified Booth algorithm for high radix fixed-point multiplication." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1, no. 2 (1993): 164–67. http://dx.doi.org/10.1109/92.238420.
Full textKim, Hyunpil, Sangook Moon, and Yongsurk Lee. "Radix-16 Booth multiplier using novel weighted 2-stage Booth algorithm." IEICE Electronics Express 11, no. 13 (2014): 20140407. http://dx.doi.org/10.1587/elex.11.20140407.
Full textDhumal, Ashwini K., and Prof Shirgan S.S. "Comparison between Radix-2 and Radix -4 based on Booth Algorithm." IJARCCE 5, no. 12 (2016): 498–500. http://dx.doi.org/10.17148/ijarcce.2016.512113.
Full textKatti, R. "A modified Booth algorithm for high radix fixed-point multiplication." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2, no. 4 (1994): 522–24. http://dx.doi.org/10.1109/92.335021.
Full textMohanapriya, R., K. Rajesh, and P. S. Sudarshana. "A Modified Architecture of Multiplier and Accumulator using Radix-4 Modified Booth Algorithm." i-manager's Journal on Circuits and Systems 2, no. 4 (2014): 1–6. http://dx.doi.org/10.26634/jcir.2.4.3218.
Full textSHIN, Ji-Hye, and Young-Beom JANG. "A New DA Implementation Technique for Digital Filters Using Radix-16 Modified Booth Algorithm." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E94-A, no. 4 (2011): 1136–39. http://dx.doi.org/10.1587/transfun.e94.a.1136.
Full textMary, S. Angel Latha, and N. Dharani. "An Efficient Area and Power 2D-DWT Lifting using Radix-8 Modified Booth Algorithm." International Journal of Communication and Networking System 003, no. 001 (2014): 1–5. http://dx.doi.org/10.20894/ijcnes.103.003.001.001.
Full textKollannur, Manju Inasu, and Oudaya Coumar Souprayen. "Designing high power efficient finite impulse response filters with three-four inexact adder-integrated Booth multiplier." IAES International Journal of Robotics and Automation (IJRA) 14, no. 2 (2025): 204. https://doi.org/10.11591/ijra.v14i2.pp204-213.
Full textLiu, Chenghao, Jingyu Sun, and Ruihong Tang. "A design of multiplier based on Radix_4 Booth algorithm and 4-2 Wallace compression tree." Applied and Computational Engineering 37, no. 1 (2024): 166–76. http://dx.doi.org/10.54254/2755-2721/37/20230498.
Full textjanweja, Preety, and Vipin gupta. "A noval Approch of area efficient and fast radix 2^3 means (8) modified booth multiplier." IOSR journal of VLSI and Signal Processing 4, no. 4 (2014): 14–18. http://dx.doi.org/10.9790/4200-04431418.
Full textVishwanath, G. "Efficient Hardware Architecture for Ultra-High Sampling Rate FFT Analysis of Acoustic Emission Signals." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 11, no. 3 (2020): 2633–42. http://dx.doi.org/10.61841/turcomat.v11i3.14429.
Full textAsadi, Pouya. "A New Array Multiplier Using an Optimized Carry Network and Dynamic CMOS Technology." Journal of Circuits, Systems and Computers 25, no. 02 (2015): 1650004. http://dx.doi.org/10.1142/s0218126616500043.
Full textKavitha, G., B. Kirthiga, and N. Kirubanandasarathy. "Performance Analysis of an Area Efficient and Low Power MOD-R2MDC FFT for MIMO OFDM." Applied Mechanics and Materials 573 (June 2014): 176–80. http://dx.doi.org/10.4028/www.scientific.net/amm.573.176.
Full textSiddiq, F., H. Jamal, T. Muhammad, and M. Iqbal. "Area Efficient Radix 4 2 64 Point Pipeline FFT Architecture Using Modified CSD Multiplier." Nucleus 51, no. 3 (2014): 345–53. https://doi.org/10.71330/thenucleus.2014.689.
Full textKuo, Chao-Tsung, and Yao-Cheng Wu. "Area-Power-Delay-Efficient Multi-Modulus Multiplier Based on Area-Saving Hard Multiple Generator Using Radix-8 Booth-Encoding Scheme on Field Programmable Gate Array." Electronics 13, no. 2 (2024): 311. http://dx.doi.org/10.3390/electronics13020311.
Full textBanerjee, Sandip, Yair Bartal, Lee-Ad Gottlieb, and Alon Hovav. "Improved Fixed-Parameter Bounds for Min-Sum-Radii and Diameters k-Clustering and Their Fair Variants." Proceedings of the AAAI Conference on Artificial Intelligence 39, no. 15 (2025): 15481–88. https://doi.org/10.1609/aaai.v39i15.33699.
Full textMontoya-Andrade, D. A., J. A. Rosendo-Macías, and A. Gómez-Expósito. "Efficient computation of the short-time DFT based on a modified radix-2 decimation-in-frequency algorithm." Signal Processing 92, no. 10 (2012): 2525–31. http://dx.doi.org/10.1016/j.sigpro.2012.03.018.
Full textAnnapurna, Band Tiwari* Saurabh Sharma. "DESIGN AND DEVELOPMENT OF HYBRID MAC BASED ON CSCS." INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY 5, no. 8 (2016): 312–24. https://doi.org/10.5281/zenodo.59642.
Full textNguyen, Hung, Sheraz Khan, Cheol-Hong Kim, and Jong-Myon Kim. "A Pipelined FFT Processor Using an Optimal Hybrid Rotation Scheme for Complex Multiplication: Design, FPGA Implementation and Analysis." Electronics 7, no. 8 (2018): 137. http://dx.doi.org/10.3390/electronics7080137.
Full textKim, Haechan, Jinmoo Heo, Seongjoo Lee, and Yunho Jung. "SARDIMM: High-Speed Near-Memory Processing Architecture for Synthetic Aperture Radar Imaging." Applied Sciences 14, no. 17 (2024): 7601. http://dx.doi.org/10.3390/app14177601.
Full textFrederick, Ojiemhende Ehiagwina, Olashile Afolabi Lateef, Mustapha Khadijat, Raheem Kabirat, Jamiu Jibola Anifowose, and O. Salaudeen Wasiu. "A Study on the Performance of GA-Holt-Winters Model in 900 MHz Spectrum Prediction." International Journal of Novel Research in Electrical and Mechanical Engineering 9, no. 1 (2022): 23–31. https://doi.org/10.5281/zenodo.6832380.
Full textBagde, Vandana, and Dethe C. G. "Performance improvement of space diversity technique using space time block coding for time varying channels in wireless environment." International Journal of Intelligent Unmanned Systems 10, no. 2/3 (2020): 278–86. http://dx.doi.org/10.1108/ijius-04-2019-0026.
Full textAddanki, Purna Ramesh, N. Tilak A.V., and Dr.A.M.Prasad. "EFFICIENT IMPLEMENTATION OF 16-BIT MULTIPLIER-ACCUMULATOR USING RADIX-2 MODIFIED BOOTH ALGORITHM AND SPST ADDER USING VERILOG." June 30, 2012. https://doi.org/10.5121/vlsic.2012.3310.
Full text"Design of Multiplier through Modified Booth Algorithm with Mig Gate." International Journal of Innovative Technology and Exploring Engineering 9, no. 2 (2019): 3101–5. http://dx.doi.org/10.35940/ijitee.b7476.129219.
Full textSathish, Mr M. V., and Mrs Sailaja. "VLSI ARCHITECTURE OF PARALLEL MULTIPLIER– ACCUMULATOR BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM." International Journal of Electronics and Electical Engineering, July 2012, 40–46. http://dx.doi.org/10.47893/ijeee.2012.1009.
Full textBala, P. Sasi, and S. Raghavendra. "A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm." International Journal of Instrumentation Control and Automation, October 2011, 196–202. http://dx.doi.org/10.47893/ijica.2011.1036.
Full textАльтман, Е. А. "A method of reducing the number of operations in a fast Fourier transform algorithm." Вычислительные технологии, no. 3(23) (August 17, 2018). http://dx.doi.org/10.25743/ict.2018.3.15955.
Full textАльтман, Е. А. "A method of reducing the number of operations in a fast Fourier transform algorithm." Вычислительные технологии, no. 3(23) (August 17, 2018). http://dx.doi.org/10.25743/ict.2018.3.15955.
Full textM N, Meghana, Mallikarjuna R. Mulimani, Shiva prasad A S, Venkatesh R, and Vignesh D. "Comparison of Modified Booth Multiplier Techniques." International Journal of Innovative Science and Research Technology, June 3, 2025, 3017–22. https://doi.org/10.38124/ijisrt/25may1725.
Full textSANJEEVARAO, K., and A. RAMKUMAR. "CRBBE ALGORITHM FOR LOW POWER AND HIGH SPEED MULTIPLIER DESIGN." International Journal of Electronics Signals and Systems, October 2014, 104–8. http://dx.doi.org/10.47893/ijess.2014.1206.
Full text"Design and Analysis of Multipliers using Radix-8 Booth Encoding Technique for Low Power and Area Consumption." International Journal of Innovative Technology and Exploring Engineering 9, no. 2 (2019): 2630–35. http://dx.doi.org/10.35940/ijitee.b7284.129219.
Full text"Path Delay Optimized Booth Radix-8 Architecture." International Journal of Recent Technology and Engineering 8, no. 2S5 (2019): 235–37. http://dx.doi.org/10.35940/ijrte.b1048.0782s519.
Full textNikhare, Mr Hemantkumar H., and Prof Ashish Singhadia. "Simulation Analysis of 2-D Discrete Wavelet Transform by using Modified Radix-4 Booth Multiplier." IJARCCE, March 30, 2015, 278–85. http://dx.doi.org/10.17148/ijarcce.2015.4368.
Full textChangela, Ankur, Yogesh Kumar, Marcin Woźniak, Jana Shafi, and Muhammad Fazal Ijaz. "Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations." Scientific Reports 13, no. 1 (2023). http://dx.doi.org/10.1038/s41598-023-47890-3.
Full textC., Paramasivam, and B. Jayanthi K. "Modified Scaling-Free CORDIC Based Pipelined Parallel MDC FFT and IFFT Architecture for Radix 2^2 Algorithm." January 3, 2016. https://doi.org/10.5281/zenodo.1111797.
Full text"A Modified FFT Algorithm for OFDM Based Wireless System." International Journal of Innovative Technology and Exploring Engineering 9, no. 2S5 (2020): 10–14. http://dx.doi.org/10.35940/ijitee.b1003.1292s519.
Full textSuhasini, M., K. Prabhu Kumar, and P. Srinivas. "Multiplier Design and Performance Estimation with Distributed Arithmetic Algorithm." International Journal of Computer and Communication Technology, April 2016, 90–95. http://dx.doi.org/10.47893/ijcct.2016.1345.
Full textVerba, V. S., V. I. Merkulov, and V. S. Chernov. "Methods of trajectory control of observation in air-based angle-measuring two-position radio monitoring systems. Part 2. Gradient methods." Achievements of Modern Radioelectronics, 2021. http://dx.doi.org/10.18127/j20700784-202109-01.
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