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Journal articles on the topic 'Radix-4 Booth Multiplier'

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Published: 2 June 2025

Last updated: 19 July 2025

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Sadaf, Sumaya, and V. Radha Krishna. "Design and Implementation of Area Efficient Low Latency Radix-8 Multiplier on FPGA." International Journal for Research in Applied Science and Engineering Technology 11, no. 10 (2023): 667–78. http://dx.doi.org/10.22214/ijraset.2023.56018.

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Abstract: Electronic systems are widely used by humans nowadays in all aspects of daily life. Today, there is no living for humans on Earth without any electronic products. High Speed, Low Power, and Low Area Electronic Systems are what the current generation needs. In digital systems, a variety of arithmetic circuits are employed. Adder, multiplier, divider, and other arithmetic circuits are some examples. To acquire Products from Multiplier and Multiplicand, there are various multipliers with various methods. One of the multipliers is Radix-4 Multiplier. The Radix-4 Multiplier produces n/2 partial products, where n is the multiplier's bit count. This multiplier has a high operating speed, power dissipation, and surface area. Area, power dissipation, and propagation delay can all be reduced by reducing the number of partial products of the n-bit multiplier. Radix-8 uses n-bit multiplier integers that are n/3 for partial products. The Area, Delay, and Power Dissipation are reduced as a result. 8- bit booth multipliers for Radix-4 and Radix-8 are designed and implemented using FPGA. For both multipliers, delay, power dissipation, and area are compared. According to the comparison, Radix8 Booth Multiplier performs better than Radix-4 Booth Multiplier in terms of delay, power dissipation, and area. Therefore, the Radix-4 Booth Multiplier can be swapped out for the Radix-8 Booth Multiplier.

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Nandha Kumar, P. "Design of Accuracy Based Fixed-Width Booth Multipliers Using Data Scaling Technology." Asian Journal of Electrical Sciences 11, no. 2 (2022): 24–30. http://dx.doi.org/10.51983/ajes-2022.11.2.3524.

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Multipliers are the basic building blocks in various digital signal processing applications such as convolution, correlation, and filters. However, conventional array multipliers, vedic multipliers were resulted in higher area, power, delay consumptions. Therefore, this work is focused on design and implementation of variable width Radix-4 booth multiplier using Data Scaling Technology (DST). The radix-4 modified booth encoding was used in the production of these incomplete items. In accumulation, the bits of the fractional products are added in a parallel manner with decreased stages using a multi-stage carry propagation adder (MSCPA). The simulation demonstrated that the suggested DST-Radix-4 booth multiplier (DST-R4BM) resulted in higher performance in comparison to traditional multiplies in terms of area, delay, and power.

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Mokhtar, Anis Shahida, Chew Sue Ping, Muhamad Faiz Md Din, Nazrul Fariq Makmor, and Muhammad Asyraf Che Mahadi. "Implementation of Booth Multiplier Algorithm using Radix-4 in FPGA." Jurnal Kejuruteraan si4, no. 1 (2021): 161–65. http://dx.doi.org/10.17576/jkukm-2021-si4(1)-20.

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This paper presentsthe performance of Radix-4 Modified Booth Algorithm. Booth algorithm is a multiplication algorithm that multiplies two signed binary numbers in two's complement notation. Multiplier is a fundamental component in general-purpose microprocessors and in digital signal processors. With advances in technology, researchers design multipliers which offer high speed, low power, and less area implementation. Booth multiplier algorithm is designed to reduce number of partial products as compared to conventional multiplier. The proposed design is simulated by using Verilog HDL in Quartus II and implemented in Cyclone II FPGA. The result shows that the average output delay is 20.78 ns. The whole design has been verified by gate level simulation.

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Bhusare, Saroja S., and V. S. Kanchana Bhaaskaran. "Low-Power High-Accuracy Fixed-Width Radix-8 Booth Multiplier Using Probabilistic Estimation Technique." Journal of Circuits, Systems and Computers 26, no. 05 (2017): 1750079. http://dx.doi.org/10.1142/s0218126617500797.

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In many Multimedia and DSP applications, the fixed-width multipliers are used to avoid infinite growth in the word size. Fixed-width multiplier produces an [Formula: see text]-bit product with two [Formula: see text]-bit inputs. This paper presents probabilistic estimation technique applied for the fixed-width radix-8 Booth multiplier for the generation of the compensation bias circuit. The probabilistic estimation circuit for the fixed-width radix-8 Booth multiplier is derived systematically from theoretical computation in preference to time-consuming exhaustive simulations. Results show that the radix-8 direct truncated multiplier reduces the maximum absolute error by 33%, the average error by 22% and the mean square error by 39% for a 12-bit multiplier compared with the radix-4 direct truncated multiplier. Results also demonstrate that, with the probabilistic estimation technique applied to the fixed-width radix-8 Booth multiplier, there is a reduction of 25% in the maximum absolute error, 13.4% reduction in the average error, and 25.13% reduction in the mean square error have been realized compared with the existing fixed-width radix-4 Booth multiplier with probabilistic estimation technique. Standard EDA design tools are used for simulations.

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Suvarna, S., K. Rajesh, and T. Radhu. "A Modified Architecture for Radix-4 Booth Multiplier with Adaptive Hold Logic." International Journal of Students' Research in Technology & Management 4, no. 1 (2016): 01–05. http://dx.doi.org/10.18510/ijsrtm.2016.411.

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High speed digital multipliers are most efficiently used in many applications such as Fourier transform, discrete cosine transforms, and digital filtering. The throughput of the multipliers is based on speed of the multiplier, and then the entire performance of the circuit depends on it. The pMOS transistor in negative bias cause negative bias temperature instability (NBTI), which increases the threshold voltage of the transistor and reduces the multiplier speed. Similarly, the nMOS transistor in positive bias cause positive bias temperature instability (PBTI).These effects reduce the transistor speed and the system may fail due to timing violations. So here a new multiplier was designed with novel adaptive hold logic (AHL) using Radix-4 Modified Booth Multiplier. By using Radix-4 Modified Booth Encoding (MBE), we can reduce the number of partial products by half. Modified booth multiplier helps to provide higher throughput with low power consumption. This can adjust the AHL circuit to reduce the performance degradation. The expected result will be reduce threshold voltage, increase throughput and speed and also reduce power. This modified multiplier design is coded by Verilog and simulated using Xilinx ISE 12.1 and implemented in Spartan 3E FPGA kit.

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Sivajyothi, Gogula, and Suman Mishra. "Efficient Compressor and Encoder Strategies for Cost-Effective Radix-4 Approximate Booth Multipliers." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 008 (2024): 1–16. http://dx.doi.org/10.55041/ijsrem37197.

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Multiplication operations are essential in digital systems, and the design of efficient and cost- effective multipliers holds significant importance across various applications. This paper presents a novel methodology aimed at improving the affordability of approximate radix-4 Booth multipliers by proposing simplified designs for compressors and encoders. The primary objective is to achieve a balance between computational accuracy and hardware cost, rendering the multiplier suitable for deployment in low-cost embedded systems and applications where a certain degree of approximation is permissible. The proposed approach involves utilization of simplified compressors, meticulously optimized for resource efficiency and seamless integration into the approximate radix-4 Booth multiplier architecture. Furthermore, an innovative encoder design is introduced to further streamline the hardware complexity associated with encoding partial products. These encoder designs are strategically crafted to maintain an acceptable level of accuracy while minimizing resource utilization. Keywords:Approximate Booth multipliers, Booth encoders, Compressors, Xilinx ISE 14.7 tool

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Wani, Towseef Ul Haq, and Ravinder Pal Singh. "Implementation of ALU Using Modified Radix-4 Modified Booth Multiplier." International Journal for Research in Applied Science and Engineering Technology 11, no. 2 (2023): 188–200. http://dx.doi.org/10.22214/ijraset.2023.48914.

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Abstract: In this project, we propose a novel multiplier hardware design based on a radix - 4 modified booth encoder. The standard modified Booth encoding (MBE) provides an uneven partial product array due to the extra partial product bit at the least significant bit position of each partial product row. In this brief, a simple technique for constructing a regular partial product array with fewer partial product rows and low overhead is provided, reducing the complexity of partial product reduction as well as the space, time, and power of MBE multipliers. A SPST-based adder is examined and designed for the reduction of power in partial product reduction

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Fu, Chengjie, Xiaolei Zhu, Kejie Huang, and Zheng Gu. "An 8-bit Radix-4 Non-Volatile Parallel Multiplier." Electronics 10, no. 19 (2021): 2358. http://dx.doi.org/10.3390/electronics10192358.

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The data movement between the processing and storage units has been one of the most critical issues in modern computer systems. The emerging Resistive Random Access Memory (RRAM) technology has drawn tremendous attention due to its non-volatile ability and the potential in computation application. These properties make them a perfect choice for application in modern computing systems. In this paper, an 8-bit radix-4 non-volatile parallel multiplier is proposed, with improved computational capabilities. The corresponding booth encoding scheme, read-out circuit, simplified Wallace tree, and Manchester carry chain are presented, which help to short the delay of the proposed multiplier. While the presence of RRAM save computational time and overall power as multiplicand is stored beforehand. The area of the proposed non-volatile multiplier is reduced with improved computing speed. The proposed multiplier has an area of 785.2 μm2 with Generic Processing Design Kit 45 nm process. The simulation results show that the proposed multiplier structure has a low computing power at 161.19 μW and a short delay of 0.83 ns with 1.2 V supply voltage. Comparative analyses are performed to demonstrate the effectiveness of the proposed multiplier design. Compared with conventional booth multipliers, the proposed multiplier structure reduces the energy and delay by more than 70% and 19%, respectively.

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Kuo, Chao-Tsung, and Yao-Cheng Wu. "FPGA Implementation of a Novel Multifunction Modulo (2n ± 1) Multiplier Using Radix-4 Booth Encoding Scheme." Applied Sciences 13, no. 18 (2023): 10407. http://dx.doi.org/10.3390/app131810407.

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The residue number system is widely used in applications such as communication systems, cryptography, digital filters, digital signal processors, fault-tolerant detection, and so on. This paper proposes a multifunction modulo (2n ± 1) multiplier based on the radix-4 Booth encoding scheme that can operate both modulo (2n − 1) and modulo (2n + 1) multipliers using the same hardware structure with only one control signal. A novel modulo (2n ± 1) multiplier based on radix-4 Booth encoding is proposed that can achieve superior performance, with low power, fast operation, high area efficiency, and low area-delay product (ADP) and power-delay product (PDP) compared with similar modified Booth-encoding methods. In addition, by integrating the separate modulo functions of the modulo (2n − 1) multiplier and modulo (2n + 1) multiplier into a single multifunction modulo (2n ± 1) multiplier, the proposed method can save up to 52.59% (n = 16) of hardware area, up to 5.45% (n = 32) of delay time, up to 49.05% (n = 16) of dynamic power, up to 50.92% (n = 32) of ADP, and up to 50.02% (n = 32) of PDP compared with the original separate circuits merged together. Furthermore, the operation ranges of the multiplicand and multiplier of the proposed modulo (2n + 1) multiplier and modulo (2n − 1) multiplier are {0, 2n + 1} and {0, 2n}, respectively, which are wider than for other reported hardware structures. The hardware area, power consumption, and delay time are simulated and verified using Verilog HDL and Xilinx FPGA (Field Programmable Gate Array) Vivado tools. The Xilinx Artix-7 XC7A35T-CSG324-1 FPGA chipset is adopted in the proposed work.

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Liu, Chenghao, Jingyu Sun, and Ruihong Tang. "A design of multiplier based on Radix_4 Booth algorithm and 4-2 Wallace compression tree." Applied and Computational Engineering 37, no. 1 (2024): 166–76. http://dx.doi.org/10.54254/2755-2721/37/20230498.

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In a multitude of computational and signal processing scenarios, the multiplier functions as a fundamental arithmetic component. Given the complex hardware arrangement of multipliers and their usual positioning within the crucial pathway of digital systems, their significance is substantial. Therefore, approximations of multipliers can greatly optimize system performance. This essay examines the fundamental ideas behind the Wallace tree, the Carry ahead adder, and the Radix-4 Booth algorithm. Additionally, instead of the more common 3-2 compressors, a Wallace tree structure with 4-2 compressors is used to compact these products for the manufacture of partial products. This reduction in compression stages to three significantly curtails delays along critical paths, thereby substantially improving overall performance. The compressed outcomes from the Wallace tree undergo processing via a 64 bit carry ahead adder, effectively addressing delays stemming from mutual carry propagation among sequentially connected regular full adders. Leveraging these principles and processes, a 32-bit signed multiplier is designed. Building upon this foundation, an approximate Booth multiplier is developed, enhancing both computational speed and reducing critical path delays. The functionality of the multiplier was validated using Vivado simulation, demonstrating its correctness. Additionally, the RTL-level circuitry of different segments of the multiplier was showcased.

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K, Soundarya. "DESIGN AND IMPLEMENTATION OF RADIX-4-8 MODIFIED BOOTH’S ENCODER USING FPGA." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 05 (2024): 1–5. http://dx.doi.org/10.55041/ijsrem34671.

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We describe a unique design methodology of approximate radix-4 Booth multipliers that can be produced at a reasonable cost and that can greatly lower the power consumption of signal processing activities that are error-resilient. The suggested method takes into account two important processing steps simultaneously by requiring the generated error directions to be opposite to each other, in contrast to previous studies that only concentrate on the approximation of either the partial product generation with encoders or the partial product reductions with compressors. In comparison to the previous designs, the suggested approximation Booth multiplier can minimize the needed processing energy under the same number of approximate bits since the internal mistakes are naturally balanced to have zero mean. This suggested multiplier design was created in Verilog HDL, simulated using Xilinx and Modelsim 6.4c.

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Adiono, Trio, Hans Herdian, Suksmandhira Harimurti, and Tengku Ahmad Madya Putra. "Design of Compact Modified Radix-4 8-Bit Booth Multiplier." International Journal on Electrical Engineering and Informatics 12, no. 2 (2020): 228–41. http://dx.doi.org/10.15676/ijeei.2020.12.2.4.

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Jiménez, Abimael, and Antonio Muñoz. "Very-Large-Scale Integration (VLSI) Implementation and Performance Comparison of Multiplier Topologies for Fixed- and Floating-Point Numbers." Applied Sciences 15, no. 9 (2025): 4621. https://doi.org/10.3390/app15094621.

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Multiplication is an arithmetic operation that has a significant impact on the performance of several real-life applications such as digital signals, image processing, and machine learning. The main concern of electronic system designers is energy optimization with minimal penalties in terms of speed and area for designing portable devices. In this work, a very-large-scale integration (VLSI) design and delay/area performance comparison of array, Wallace tree, and radix-4 Booth multipliers was performed. This study employs different word lengths, with an emphasis on the design of floating-point multipliers. All multiplier circuits were designed and synthesized using Alliance open-source tools in 350 nm process technology with the minimum delay constraint. The findings indicate that the array multiplier has the highest delay and area for all the multiplier sizes. The Wallace multiplier exhibited the lowest delay in the mantissa multiplication of single-precision floating-point numbers. However, no significant difference was observed when compared with the double-precision floating-point multipliers. The Wallace multiplier uses the lowest area in both the single- and double-precision floating-point multipliers.

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Tang, Xiqin, Yang Li, Chenxiao Lin, and Delong Shang. "A Low-Power Area-Efficient Precision ScalableMultiplier with an Input Vector Systolic Structure." Electronics 11, no. 17 (2022): 2685. http://dx.doi.org/10.3390/electronics11172685.

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In this paper, a small-area low-power 64-bit integer multiplier is presented, which is suitable for portable devices or wireless applications. To save the area cost and power consumption, an input vector systolic (IVS) structure is proposed based on four 16-bit radix-8 Booth multipliers and a data input scheme is proposed to reduce the number of signal transitions. This structure is similar to a systolic array in matrix multiply units of a Convolutional Neural Network (CNN), but it reduces the number of processing elements by 3/4 concerning the same vector systolic accelerator in reference. The comparison results prove that the IVS multiplier reduces at least 61.9% of the area and 45.18% of the power over its counterparts. To increase the hardware resource utilization, a Transverse Carry Array (TCA) structure for Partial Products Accumulation (PPA) was designed by replacing the 32-bit adders with 3/17-bit adders in the 16-bit multipliers. The experiment results show that the optimization could lead to at least a 6.32% and 13.65% reduction in power consumption and area cost, respectively, compared to the standard 16-bit radix-8 Booth multiplier. In the end, the precise scale of the proposed IVS multiplier is discussed. Benefiting from the modular design, the IVS multiplier can be configured to support sixteen different kinds of multiplications at a step of 16 bits [16b, 32b, 48b, 64b] × [16b, 32b, 48b, 64b].

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Kollannur, Manju Inasu, and Oudaya Coumar Souprayen. "Designing high power efficient finite impulse response filters with three-four inexact adder-integrated Booth multiplier." IAES International Journal of Robotics and Automation (IJRA) 14, no. 2 (2025): 204. https://doi.org/10.11591/ijra.v14i2.pp204-213.

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Finite impulse response (FIR) filters are widely utilized in several applications in digital signal processing, including data transmission, photography, digital audio, and biomedicine. It is necessary to use high sample rates for FIR filters, while moderate sample rates are needed for low-power circuits. To solve these problems, a Booth multiplier based on three-four inexact adder-based multiplication (TFIE-BM) was proposed. The goal of the proposed TFIE-based FIR Booth multiplier is to lower area usage, latency, and power consumption. The proposed method utilizes the spotted hyena optimizer (SHO) to find the optimal filter coefficient (FC) by minimizing the pass power consumption and Transition bandwidth. Moreover, a high-performance three-four inexact adder (TIFE adder) has been introduced, which uses fewer XOR gates for sum and carry generation, indicating that the logic has been simplified to reduce hardware complexity. By increasing speed and decreasing the FIR filter's critical path delay, a modified Booth multiplier that uses a 5:2 compressor is introduced. The overall delay of the proposed approach is 23.4%, 18.7%, 12.3%, and 5.7% lower than that of the Radix-4 Booth multiplier, CSA Booth multiplier, hybrid multiplier, and traditional Booth multiplier, respectively.

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Hong, Taeyang, and Jaeyong Chung. "Design and Comparison of Radix-4 and Factored Radix-8 Modified Booth Multiplier for Neural Processing." Journal of the Institute of Electronics and Information Engineers 57, no. 12 (2020): 81–89. http://dx.doi.org/10.5573/ieie.2020.57.12.81.

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Ushanandhini and S. Shivkumar Dr. "Designing of IIR Filter using Radix 4 Multiplier by Precharging Technique." International Journal of Trend in Scientific Research and Development 2, no. 4 (2019): 1100–1107. https://doi.org/10.31142/ijtsrd14208.

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Infinite impulse response IIR filter designs mainly aims on either low area cost or high speed or reduced power consumption. Infinite Impulse Response filters are the most important element in signal processing and communication. IIR filters can achieve a given filtering characteristic using less memory and calculations than a similar FIR filter. Multipliers are the basic building block in DSP, microprocessors and other applications. The system's performance is entirely dependent upon the multipliers because they have large area, long latency and consume considerable power hence there is a need to design high speed, low power consumption, regular and less area multipliers. The speed of the multipliers can be increased by reducing the number of partial products. Parallel multipliers are fastest among all multipliers. Booth multipliers are the parallel multipliers that operate on signed operands in two's complement form and have high performance, low power consumption and does not suffer from bad regularity. This paper presents an efficient implementation of high speed parallel multiplier using Radix-4 which further used in the designing of IIR filter. Pre charging is implemented to increase the lifespan of electronic components and increase reliability of the high voltage system. Pre charge is intended to minimize propagation delay time. Pre charge of the power line voltages in a high voltage DC application is a preliminary mode which limits the inrush current during the power up procedure. In other systems such as vehicle applications, pre charge will occur with each use of the system, multiple times per day. Ushanandhini | Dr. S. Shivkumar "Designing of IIR Filter using Radix-4 Multiplier by Precharging Technique" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-4 , June 2018, URL: https://www.ijtsrd.com/papers/ijtsrd14208.pdf

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.Raut, Prof V. R., and P. R. Loya. "FPGA Implementation of Low Power Booth Multiplier Using Radix-4 Algorithm." International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 03, no. 08 (2014): 11479–86. http://dx.doi.org/10.15662/ijareeie.2014.0308081.

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Chang, Yen-Jen, Yu-Cheng Cheng, Shao-Chi Liao, and Chun-Huo Hsiao. "A Low Power Radix-4 Booth Multiplier With Pre-Encoded Mechanism." IEEE Access 8 (2020): 114842–53. http://dx.doi.org/10.1109/access.2020.3003684.

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Pilipovic, Ratko, and Patricio Bulic. "On the Design of Logarithmic Multiplier Using Radix-4 Booth Encoding." IEEE Access 8 (2020): 64578–90. http://dx.doi.org/10.1109/access.2020.2985345.

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Deng, Weixiang, Wenxiang Cheng, Jie Cheng, Leibin Ni, and Anping He. "8-Bit NCL Asynchronous Multiplier based on Radix-4 Booth Algorithm." IOP Conference Series: Materials Science and Engineering 914 (September 19, 2020): 012024. http://dx.doi.org/10.1088/1757-899x/914/1/012024.

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K, P. Heena. "A Comparative Study on Ripple Carry Adder and Modified Square Root Carry Select Adder in Radix-4 8*8 Booth Multiplier." International Journal of Innovative Science and Research Technology (IJISRT) 9, no. 2 (2024): 4. https://doi.org/10.5281/zenodo.10784386.

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In digital circuits multiplication is a fundamental operation, extensively utilized in various computational tasks. The efficiency and performance of the multiplier circuit significantly impact the overall system performances, especially in applications demanding high-speed computation with minimal power consumption. This study presents a comparative analysis between two distinct implementations of Radix-4 8*8 Booth multiplier employing different adder architectures: Ripple carry adder and Modified Square Root Carry select adder. Multiplier with modified square root carry select adder reduced critical path delay (CPD), power delay product (PDP) and area delay product(ADP). Generic process design kit (gpdk) of 45nm technology is used for design and implementation using Cadence software. Keywords:- Booth Multiplier; Carry Select Adder; Critical Path Delay; Power Delay Product; Area Delay Product; Cadence.

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Md., Zakir Hussain, and Parvin KaziNikhat. "Low power and high performance FFT with different radices." TELKOMNIKA Telecommunication, Computing, Electronics and Control 8, no. 2 (2019): 99–106. https://doi.org/10.11591/ijres.v8.i2.pp99-106.

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FFT is one of the most active blocks in digital signal processing and in various field of communication systems. FFT has received significant attention over the past years to increase its capability and versatility. This paper describes an extensive study on trade-off of different radices with different computational elements of butterfly such as adders and multipliers. Finding an efficient radix along with computational elements is the key point to find best suite i.e. high precision, low power and low area applications like radar, filtering, image compression etc. The work also considers the precision and the data format to represent constant value such as Q-point. The proposed FFT architectures not only uphold better solutions for low power and high-performance application systems, but also open up a new research lines. This paper demonstrates that radix-2^3 consumes 43% less LUTs and 17% less power consumption, 40% increase of frequency in radix-2^2 in comparison with radix-2 algorithm for the combination of CSA with modified booth multiplier and the increment of frequency about 19%, 26% less LUTs consumption and 26% less power in Radix-2^2 when compared to radix-4 with various combination of adder and multiplier. In this work we have used Xilinx 14.7 XST for synthesis and the target device used is Spartan6 XC6SLX100. Simulation is carried out in Xilinx ISIM and also performed timing analysis and generated post-place and route.

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Dr., Vasudeva G. "Floating Point Unit with High Precision Efficiency." International Journal of Soft Computing and Engineering (IJSCE) 15, no. 2 (2025): 24–30. https://doi.org/10.35940/ijsce.B3669.15020525/.

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Abstract: In this paper, we dive into designing a Single Precision Floating Point Unit (FPU), a key player in modern processors. FPUs are essential for handling complex numerical calculations with high precision and a broad range, making them indispensable in scientific research, graphics rendering, and machine learning—our design centers around two main components: the Brent-Kung adder and the radix-4 Booth multiplier. The BrentKung adder is our go-to for fast addition and subtraction. Thanks to its clever parallel-prefix structure, it minimises delays even as the numbers get bigger. For multiplication, we turn to the radix-4 Booth multiplier. This powerhouse streamlines the multiplication process by cutting down the number of partial products and operations needed, efficiently handling both positive and negative numbers. By integrating these components, our FPU can handle floating-point arithmetic with excellent efficiency and reliability. In scientific computing, this means more accurate simulations and data analyses. For graphics processing, it translates to better image rendering and smoother visual effects. And in machine learning, itsupportsrobust training and execution of algorithms on massive datasets, ensuring dependable model performance.

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SINGHAL, Subodh K., Sujit K. PATEL, Anurag MAHAJAN та Gaurav SAXENA. "Area-delay eﬀicient Radix-4 8×8 Booth multiplier for DSP applications". TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES 29, № 4 (2021): 2012–28. http://dx.doi.org/10.3906/elk-2007-179.

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Esther Rani, Dr T. "Design Of High Performance Configurable Radix-4 Booth Multiplier Using Cadence Tools." CVR Journal of Science & Technology 6, no. 1 (2014): 66–74. http://dx.doi.org/10.32377/cvrjst0611.

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Xue, H., R. Patel, N. V. V. K. Boppana, and S. Ren. "Low‐power‐delay‐product radix‐4 8*8 Booth multiplier in CMOS." Electronics Letters 54, no. 6 (2018): 344–46. http://dx.doi.org/10.1049/el.2017.3996.

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Abstract: In this paper, we dive into the design of a Single Precision Floating Point Unit (FPU), a key player in the world of modern processors. FPUs are essential for handling complex numerical calculations with high precision and a broad range, making them indispensable in areas like scientific research, graphics rendering, and machine learning. Our design centers around two main components: the Brent-Kung adder and the radix-4 Booth multiplier. The Brent-Kung adder is our go-to for fast addition and subtraction. Thanks to its clever parallel- prefix structure, it keeps delays minimal even as the numbers get bigger. For multiplication, we turn to the radix-4 Booth multiplier. This powerhouse streamlines the multiplication process by cutting down the number of partial products and operations needed, handling both positive and negative numbers with ease. By integrating these components, our FPU can handle floating-point arithmetic with great efficiency and reliability. In scientific computing, this means more accurate simulations and data analyses. For graphics processing, it translates to better image rendering and smoother visual effects. And in machine learning, it supports robust training and execution of algorithms on massive datasets, ensuring dependable model performance

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Mohanapriya, R., K. Rajesh, and P. S. Sudarshana. "A Modified Architecture of Multiplier and Accumulator using Radix-4 Modified Booth Algorithm." i-manager's Journal on Circuits and Systems 2, no. 4 (2014): 1–6. http://dx.doi.org/10.26634/jcir.2.4.3218.

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Esmaeel, Anwar A., Sa’ed Abed, Bassam J. Mohd, and Abbas A. Fairouz. "POSIT vs. Floating Point in Implementing IIR Notch Filter by Enhancing Radix-4 Modified Booth Multiplier." Electronics 11, no. 1 (2022): 163. http://dx.doi.org/10.3390/electronics11010163.

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The increased demand for better accuracy and precision and wider data size has strained current the floating point system and motivated the development of the POSIT system. The POSIT system supports flexible formats and tapered precision and provides equivalent accuracy with fewer bits. This paper examines the POSIT and floating point systems, comparing the performance of 32-bit POSIT and 32-bit floating point systems using IIR notch filter implementation. Given that the bulk of the calculations in the filter are multiplication operations, an Enhanced Radix-4 Modified Booth Multiplier (ERMBM) is implemented to increase the calculation speed and efficiency. ERMBM enhances area, speed, power, and energy compared to the POSIT regular multiplier by 26.80%, 51.97%, 0.54%, and 52.22%, respectively, without affecting the accuracy. Moreover, the Taylor series technique is adopted to implement the division operation along with cosine arithmetic unit for POSIT numbers. After comparing POSIT with floating point, the accuracy of POSIT is 92.31%, which is better than floating point’s accuracy of 23.08%. Moreover, POSIT reduces area by 21.77% while increasing the delay. However, when the ERMBM is utilized instead of the POSIT regular multiplier in implementing the filter, POSIT outperforms floating point in all the performance metrics including area, speed, power, and energy by 35.68%, 20.66%, 31.49%, and 45.64%, respectively.

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Hussain, Md Zakir, and Kazi Nikhat Parvin. "Low power and high performance FFT with different radices." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 2 (2019): 99. http://dx.doi.org/10.11591/ijres.v8.i2.pp99-106.

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FFT is one of the most active blocks in digital signal processing and in various field of communication systems. FFT has received significant attention over the past years to increase its capability and versatility. This paper describes an extensive study on trade-off of different radices with different computational elements of butterfly such as adders and multipliers. Finding an efficient radix along with computational elements is the key point to find best suite i.e. high precision, low power and low area applications like radar, filtering, image compression etc. The work also considers the precision and the data format to represent constant value such as Q-point. The proposed FFT architectures not only uphold better solutions for low power and high-performance application systems, but also open up a new research lines. This paper demonstrates that radix-2^3 consumes 43% less LUTs and 17% less power consumption, 40% increase of frequency in radix-2^2 in comparison with radix- 2 algorithm for the combination of CSA with modified booth multiplier and the increment of frequency about 19%, 26% less LUTs consumption and 26% less power in Radix-2^2 when compared to radix-4 with various combination of adder and multiplier. In this work we have used Xilinx 14.7 XST for synthesis and the target device used is Spartan6 XC6SLX100. Simulation is carried out in Xilinx ISIM and also performed timing analysis and generated post-place and route.

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Kuo, Chao-Tsung, and Yao-Cheng Wu. "Area-Power-Delay-Efficient Multi-Modulus Multiplier Based on Area-Saving Hard Multiple Generator Using Radix-8 Booth-Encoding Scheme on Field Programmable Gate Array." Electronics 13, no. 2 (2024): 311. http://dx.doi.org/10.3390/electronics13020311.

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A multi-modulus architecture based on the radix-8 Booth encoding of a modulo (2n − 1) multiplier, a modulo (2n) multiplier, and a modulo (2n + 1) multiplier is proposed in this paper. It uses the original single circuit and shares many common circuit characteristics with a small extra circuit to carry out multi-modulus operations. Compared with a previous radix-4 study, the radix-8 architecture can increase the modulation multiplication encoding selection from three codes to four codes. This reduces the use of partial products from ⌊n/2⌋ to ⌊n/3⌋ + 1, but it increases the operation complexity for multiplication by three circuits. A hard multiple generator (HMG) is used to address this problem. Two judgment signals in the multi-modulus circuit can be used to perform three operations of the modulo (2n − 1) multiplier, modulo (2n) multiplier, and modulo (2n + 1) multiplier at the same time. The weighted representation is used to reduce the number of partial products. Compared with previously reported methods in the literature, the proposed approach can achieve better performance by being more area-efficient, being faster, consuming low power, and having a lower area-delay product (ADP) and power-delay product (PDP). With the multi-modulus HMG, the proposed modified architecture can save 34.48–55.23% of hardware area. Compared with previous studies on the multi-modulus multiplier, the proposed architecture can save 22.78–35.46%, 4.12–11.15%, 12.59–24.73%, 27.88–38.88%, and 20.49–27.85% of hardware area, delay time, dissipation power, ADP, and PDP, respectively. Xilinx field programmable gate array (FPGA) Vivado 2019.2 tools and the Verilog hardware description language are used for synthesis and implementation. The Xilinx Artix-7 XC7A35T-CSG324-1 chipset is adopted to evaluate the performance.

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Ghasemi, Mir Majid, Amir Fathi, Morteza Mousazadeh, and Abdollah Khoei. "A new high speed and low power decoder/encoder for Radix‐4 Booth multiplier." International Journal of Circuit Theory and Applications 49, no. 7 (2021): 2199–213. http://dx.doi.org/10.1002/cta.2985.

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S., SUVARNA, RAJESH K., and VEERAKUMAR S. "Aging Aware Radix-4 Booth Multiplier With Adaptive Hold Logic and Razor Flip Flop." i-manager’s Journal on Electronics Engineering 6, no. 1 (2015): 13. http://dx.doi.org/10.26634/jele.6.1.3681.

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Ma, Yanhua, Qican Xu, and Zerui Song. "Resource-Efficient Optimization for FPGA-Based Convolution Accelerator." Electronics 12, no. 20 (2023): 4333. http://dx.doi.org/10.3390/electronics12204333.

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Convolution forms one of the most essential operations for the FPGA-based hardware accelerator. However, the existing designs often neglect the inherent architecture of FPGA, which puts forward an austere challenge on hardware resource. Even though some previous works have proposed approximate multipliers or convolution acceleration algorithms to deal with this issue, the inevitable accuracy loss and resource occupation easily lead to performance degradation. Toward this, we first propose two kinds of resource-efficient optimized accurate multipliers based on LUTs or carry chains. Then, targeting FPGA-based platforms, a generic multiply–accumulate structure is constructed by directly accumulating the partial products produced by our proposed optimized radix-4 Booth multipliers without intermediate multiplication and addition results. Experimental results demonstrate that our proposed multiplier achieves a maximum 51% look-up-table (LUT) reduction compared to the Vivado area-optimized multiplier IP. Furthermore, the convolutional process unit using the proposed structure achieves a 36% LUT reduction compared to existing methods. As case studies, the proposed method is applied to DCT transform, LeNet, and MobileNet-V3 to achieve hardware resource saving without loss of accuracy.

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Dr. Vasudeva G and Dr Bharathi Gururaj. "Floating Point Unit with High Precision Efficiency." International Journal of Soft Computing and Engineering 15, no. 2 (2025): 24–30. https://doi.org/10.35940/ijsce.b3669.15020525.

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In this paper, we dive into designing a Single Precision Floating Point Unit (FPU), a key player in modern processors. FPUs are essential for handling complex numerical calculations with high precision and a broad range, making them indispensable in scientific research, graphics rendering, and machine learning—our design centers around two main components: the Brent-Kung adder and the radix-4 Booth multiplier. The BrentKung adder is our go-to for fast addition and subtraction. Thanks to its clever parallel-prefix structure, it minimises delays even as the numbers get bigger. For multiplication, we turn to the radix-4 Booth multiplier. This powerhouse streamlines the multiplication process by cutting down the number of partial products and operations needed, efficiently handling both positive and negative numbers. By integrating these components, our FPU can handle floating-point arithmetic with excellent efficiency and reliability. In scientific computing, this means more accurate simulations and data analyses. For graphics processing, it translates to better image rendering and smoother visual effects. And in machine learning, it supports robust training and execution of algorithms on massive datasets, ensuring dependable model performance.

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G, Vasudeva, and Bharathi Gururaj. "Design of an Efficient Single Precision Floating Point Unit." International Journal of Electrical Engineering and Computer Science 7 (March 26, 2025): 44–54. https://doi.org/10.37394/232027.2025.7.5.

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In this , we design of a Single Precision Floating Point Unit (FPU), a key player in the world of modern processors. FPUs are essential for handling complex numerical calculations with high precision and a broad range, making them indispensable in areas like scientific research, graphics rendering, and machine learning. Our design centers around two main components: the Brent-Kung adder and the radix-4 Booth multiplier. The Brent-Kung adder is our go-to for fast addition and subtraction. Thanks to its clever parallel- prefix structure, it keeps delays minimal even as the numbers get bigger. For multiplication, we turn to the radix-4 Booth multiplier. This powerhouse streamlines the multiplication process by cutting down the number of partial products and operations needed, handling both positive and negative numbers with ease. By integrating these components, our FPU can handle floating-point arithmetic with great efficiency and reliability. In scientific computing, this means more accurate simulations and data analyses. For graphics processing, it translates to better image rendering and smoother visual effects. And in machine learning, it supports robust training and execution of algorithms on massive datasets, ensuring dependable model performance.

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Mohanapriya, R., and K. Rajesh. "A Modified Architecture of Multiplier and Accumulator Using Spurious Power Suppression Technique." International Journal of Students' Research in Technology & Management 3, no. 2 (2015): 258–63. http://dx.doi.org/10.18510/ijsrtm.2015.324.

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High speed and low power Multiplier and Accumulator (MAC) unit is at most requirement of today’s VLSI systems and digital signal processing (DSP) applications like FFT, Finite Impulse response filters, convolution etc. In this modified architecture, Radix-4 Modified Booth Encoding (MBE) is used to produce the partial products. In this multiplication and accumulation has been combined using a hybrid type of Carry Save Adder (CSA). So the performance will be improved. A Carry Look ahead Adder is inserted in the CSA tree to reduce the number of bits in the final adder. In booth multiplication, when two numbers are multiplied some portion of the data may be zero. By neglecting those data, power has been reduced. For this purpose Spurious Power Suppression Technique (SPST) is used to remove useless portion of the data in addition process. In this modified architecture, the overall process is three stages to produce the result. The modified MAC operation is coded with Verilog and simulated using Xilinx 12.1.

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Immareddy, Srikanth, Arunmetha Sundaramoorthy, and Aravindhan Alagarsamy. "Adaptive FIR Filter Design with Approximate Adder and Hybridized Multiplier for Efficient Noise Eradication in Sensor Nodes." ECS Journal of Solid State Science and Technology 12, no. 9 (2023): 097002. http://dx.doi.org/10.1149/2162-8777/aceaa9.

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Finite Impulse Response (FIR) filter contributes a major role in most of the signal processing applications. However, the Finite Impulse Response filter performance is restricted by its speed, power and area usage. To address these issues, an adaptive FIR filter design using approximate adder and Hybridizing (Radix-8 Booth and TRAM) Approximate Multiplier (DA-AFIR-leadx-hybam-AC) is proposed in this manuscript for eradicating the noise in the sensor nodes. Here, Low error together with area efficient approximate adder (leadx) is used for reducing path delay and area utilization. For approximate multiplier design, proposed Hybridizing (Radix-8 Booth and TRAM) Approximate Multiplier using 15–4 Approximate Compressors (hybam-AC) is used for decreasing power consumption and design complexity. The simulation of the proposed model is implemented in Verilog and the design is synthesized in FPGA utilizing Xilinx ISE 14.5. The proposed DA-AFIR-leadx-hybam-AC filter design attains 33.6%, 22.75%, 29.69% lower power and 43.58%, 11.3%, 33.07% lower delay than the existing approaches, like DA-AFIR-MLDA-RNS, DA-AFIR-Hyb-CSD-ABR, DA-AFIR-SOPOT-MPGBP. Finally, the proposed DA-AFIR-leadx-hybam-AC filter design is applied for noise removal application in sensor nodes. The proposed Filter is implemented in MATLAB/Simulink for reading input signal.

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Kumar V G, Kiran, and Shantharama Rai C,. "Low Power High Speed Arithmetic Circuits." International Journal of Recent Technology and Engineering (IJRTE) 8, no. 2 (2019): 807–13. http://dx.doi.org/10.35940/ijrte.a1064.078219.

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In the Design of arithmetic circuits reducing area, high speed and power are the major areas in VLSI system design. In this paper parallel prefix adders like Kogge-stone adder, Breunt-Kung adder, Ladner-Fischer adder is designed .Radix-4 Booth multiplier is designed by using Kogge-Stone adder. 16 bit Vedic multiplier is done by using Urdhwa Triyambaka sutra .8bit Vedic division is implemented by using Crumbs method so as to reduce the area, LUT tables and increase the speed as well as to reduce the Power dissipiation. The design is synthesized using Xilinx ISE 14.1 design suite.

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Sun, Rongxue, Huimin Liu, Rong Zhang, and Jiale Qu. "Design and Implementation of RISC-V Based Pipelined Multiplier." Journal of Physics: Conference Series 2625, no. 1 (2023): 012006. http://dx.doi.org/10.1088/1742-6596/2625/1/012006.

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Abstract Among the many microprocessors, RISC-V as an open-source instruction set is gradually gaining popularity among academia and industry. The performance of the multiplier in the microprocessor imposes constraints on the computational power of the processor. In order to improve the efficiency of multiplication instructions, a pipeline multiplier is implemented in this paper. Firstly, the partial product is generated using the Radix-4 booth. Secondly, the Wallace tree structure is used to accelerate the compression of the partial product. Then, a parallel prefix adder is used to calculate the resulting partial product to improve the timing. Finally, registers are added as a pipeline to achieve a high-efficiency multiplication calculation. With the operating voltage and temperature set to typical conditions, the integrated multiplier area is 50260.6 μm2, and the power consumption is 20.41 mW. The final frequency of the multiplier is 1 GHz in gate-level simulation.

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James, Britto Pari, Man-Fai Leung, Dhandapani Vaithiyanathan, and Karuthapandian Mariammal. "Optimal Realization of Distributed Arithmetic-Based MAC Adaptive FIR Filter Architecture Incorporating Radix-4 and Radix-8 Computation." Electronics 13, no. 17 (2024): 3551. http://dx.doi.org/10.3390/electronics13173551.

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Finite impulse response (FIR) filters are explicitly used in decisive applications such as communication and signal processing areas. Advancement in the latest technologies necessitates specific designs with optimal characteristics. This research work proposes the realization of an efficient distributed arithmetic adaptive FIR filter (DAAFA) architecture using radix-4 and radix-8 computation. Distributed arithmetic (DA) is extensively used to calculate the sum of products without involving a multiplier. The proposed fixed-point realization of a single multiply and accumulate (MAC) FIR adaptive filter is implemented with minimum complex design. The total longest-way computation time is a combination of the delay that occurred in the error calculation module and the delay involved in updating the filter weights. The longest-way computation time of the filter structure is higher, which results in increased latency. In addition, the approximate design of the radix DA multiplier structure is constructed using Booth recoding, partial product formation block and shifting-based accumulation block. Further, the approximate design of DA offers a reduction in complexity and area with respect to the number of slices and enhances the operating speed. The partial product is created using shifters and efficient adders, which further enhances the performance of the realization. This work is implemented in Xilinx and Altera devices and is compared with the present literature. From the synthesis results, it is observed that the propounded design outperforms in terms of complexity, slice delay product and ultimate speed of exertion. The suggested architecture was found to be decisive in terms of area, delay and complexity abatement. The results indicate that the propounded design achieves area reduction (slices) of about 92.03% compared to the existing design. Also, a speed enhancement of about 90.7% is accomplished for the proposed architecture. Nonetheless, the devised architecture utilizes the least means square approach, which enhances the convergence rate notably.

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James, Britto Pari, Leung Man-Fai, Mariammal Karuthapandian, and Vaithiyanathan Dhandapani. "Delineation of Optimized Single and Multichannel Approximate DA-Based Filter Design Using Influential Single MAC Strategy for Trans-Multiplexer." Sensors 24, no. 22 (2024): 7149. http://dx.doi.org/10.3390/s24227149.

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In this paper, a multichannel FIR filter design based on the Time Division Multiplex (TDM) approach that incorporates one multiply and add unit, regardless of the variable coefficient length and varying channels, by associating the resource sharing doctrine is suggested. A multiplier based on approximate distributed arithmetic (DA) circuits is employed for effective resource optimization. Although no explicit multiplication was conducted in this realization, the radix-8 and radix-4 Booth algorithms are utilized in the DA framework to curtail and optimize the partial products (PPs). Furthermore, the input stream is truncated with an erratum mending unit to roughly construct the partial products. For an aggregation of PPs, an approximate Wallace tree is taken into consideration to further minimize hardware expenses. Consequently, the suggested design’s latency, utilized area, and power usage are largely reduced. The Xilinx Vertex device is expedited, given the synthesis of the suggested multichannel realization with 16 taps, which is simulated using the Verilog formulary. It is observed that the filter structure with one channel produced the desired results, and the system’s frequency can support up to 429 MHz with a reduced area. Utilizing TSMC 180 nm CMOS technology and the Cadence RC compiler, cell-level performance is also achieved.

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Ma, Xiaolong, Jiangtao Xu, and Guican Chen. "Improved Quantization Error Compensation Method for Fixed-Width Booth Multipliers." VLSI Design 2014 (February 6, 2014): 1–9. http://dx.doi.org/10.1155/2014/451310.

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A novel quantization error (QE) compensation method is proposed in design of high accuracy fixed-width radix-4 Booth multipliers, which will effectively reduce the QE and save the area of multipliers when they are employed in cognitive radio (CR) detector and digital signal processor (DSP). The truncated partial-products of the proposed multipliers are finely divided into three sections: reserved section, adaptive compensation section, and constant compensation section. The QE compensation carries of the multipliers are generated by applying probability estimation based on a shrunken minor truncated section which is a combination of the constant compensation and adaptive compensation. The proposed compensation method not only reduces the QE of the fixed-width Booth multipliers, but also avoids the exhaustive computing resources (time and memory) during getting the compensation carries by statistical simulation. The proposed method can achieve higher accuracy than the existing works under the same area and power budgets. Simulation and experiment results show that the improved compensation method has the minimum power-delay products compared with the existing methods under the same area and can save up to 30% area for realization of full-width radix-4 Booth multipliers.

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Muralidharan, Ramya, and Chip-Hong Chang. "Radix-4 and Radix-8 Booth Encoded Multi-Modulus Multipliers." IEEE Transactions on Circuits and Systems I: Regular Papers 60, no. 11 (2013): 2940–52. http://dx.doi.org/10.1109/tcsi.2013.2252642.

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Liu, Weiqiang, Liangyu Qian, Chenghua Wang, Honglan Jiang, Jie Han, and Fabrizio Lombardi. "Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing." IEEE Transactions on Computers 66, no. 8 (2017): 1435–41. http://dx.doi.org/10.1109/tc.2017.2672976.

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Patali, Pramod, and Shahana Thottathikkulam Kassim. "Efficient modular hybrid adders and Radix-4 booth multipliers for DSP applications." Microelectronics Journal 96 (February 2020): 104701. http://dx.doi.org/10.1016/j.mejo.2020.104701.

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Cheng, Xiaoshu, Yiwen Wang, Jiazhi Liu, Weiran Ding, Hongfei Lou, and Ping Li. "Booth Encoded Bit-Serial Multiply-Accumulate Units with Improved Area and Energy Efficiencies." Electronics 12, no. 10 (2023): 2177. http://dx.doi.org/10.3390/electronics12102177.

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Bit-serial multiply-accumulate units (MACs) play a crucial role in various hardware accelerator applications, including deep learning, image processing, and signal processing. Despite the advantages of bit-serial MACs, such as a small footprint, full hardware utilization, and high frequency, their serial nature can lead to high latency and potentially compromised performance. This study investigates the potential of bit-serial solutions by applying Booth encoding to bit-serial multipliers within MACs to enhance area and power efficiencies. We present two types of bit-serial MACs based on radix-2 and radix-4 Booth encoding multipliers, respectively. Their performance is assessed through simulations and synthesis results, demonstrating the benefits of the proposed approach. The radix-4 Booth bit-serial MAC improves power and area efficiencies compared to the original bit-serial MAC. Operating at TSMC 90 nm and 150 MHz, our design exhibits a remarkable 96.39% reduction in area-power-product (APP). Moreover, the prototype verification on a Xilinx Kintex-7 FPGA proved successful. The proposed solution offers significant advantages in energy efficiency, area reduction, and APP, making it a promising candidate for next-generation hardware accelerators in offline inference, low-power devices, and other applications.

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Wang, Ren Ping. "Full-Custom Design and Implementation of High-Performance Multiplier." Advanced Materials Research 631-632 (January 2013): 1445–51. http://dx.doi.org/10.4028/www.scientific.net/amr.631-632.1445.

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I proposed a method of using full-custom design 32 × 32 multiplier to enhance performance, reduce the power consumption and the area of layout. I use improved Wallace tree structure for partial product compression, truncated beyond the 64 part of the plot and the look-ahead logarithmic adder using Radix-4 Kogge-Stone tree algorithm raise the multiplier performance. In the design of Booth2 encoding circuit and compression circuit, I use a transmission gate logic design with higher speed and smaller area. I also use Euler path method and heuristic Euler path method to reduce the layout area. The design use SMIC 0.18μm 1P4M CMOS process, with a layout area of 0.1684mm2. In a large number of test patterns, simulation results show that the computation time of a 32 × 32 multiplication is less than 3.107ns.

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Sajid, Asher, Omar S. Sonbul, Muhammad Rashid, Muhammad Arif, and Amar Y. Jaffar. "An Optimized Hardware Implementation of a Non-Adjacent Form Algorithm Using Radix-4 Multiplier for Binary Edwards Curves." Applied Sciences 14, no. 1 (2023): 54. http://dx.doi.org/10.3390/app14010054.

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Binary Edwards Curves (BEC) play a pivotal role in modern cryptographic processes and applications, offering a combination of robust security as well as computational efficiency. For robust security, this article harnesses the inherent strengths of BEC for the cryptographic point multiplication process by utilizing the Non-Adjacent Form (NAF) algorithm. For computational efficiency, a hardware architecture for the NAF algorithm is proposed. Central to this architecture is an Arithmetic Logic Unit (ALU) designed for streamlined execution of essential operations, including addition, squaring, and multiplication. One notable innovation in our ALU design is the integration of multiplexers, which maximize ALU efficiency with minimal additional hardware requirements. Complementing the optimized ALU, the proposed architecture incorporates a radix-4 multiplier, renowned for its efficiency in both multiplication and reduction. It eliminates resource-intensive divisions, resulting in a substantial boost to overall computational speed. The architecture is implemented on Xilinx Virtex series Field-Programmable Gate Arrays (FPGAs). It achieves throughput-to-area ratios of 14.819 (Virtex-4), 25.5 (Virtex-5), 34.58 (Virtex-6), and 37.07 (Virtex-7). These outcomes underscore the efficacy of our optimizations, emphasizing an equilibrium between computational performance and area utilization.

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