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Journal articles on the topic 'Radix-4 Booth Multiplier'

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Published: 2 June 2025

Last updated: 31 July 2025

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1

Sadaf, Sumaya, and V. Radha Krishna. "Design and Implementation of Area Efficient Low Latency Radix-8 Multiplier on FPGA." International Journal for Research in Applied Science and Engineering Technology 11, no. 10 (2023): 667–78. http://dx.doi.org/10.22214/ijraset.2023.56018.

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Abstract: Electronic systems are widely used by humans nowadays in all aspects of daily life. Today, there is no living for humans on Earth without any electronic products. High Speed, Low Power, and Low Area Electronic Systems are what the current generation needs. In digital systems, a variety of arithmetic circuits are employed. Adder, multiplier, divider, and other arithmetic circuits are some examples. To acquire Products from Multiplier and Multiplicand, there are various multipliers with various methods. One of the multipliers is Radix-4 Multiplier. The Radix-4 Multiplier produces n/2 p

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2

Nandha Kumar, P. "Design of Accuracy Based Fixed-Width Booth Multipliers Using Data Scaling Technology." Asian Journal of Electrical Sciences 11, no. 2 (2022): 24–30. http://dx.doi.org/10.51983/ajes-2022.11.2.3524.

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Multipliers are the basic building blocks in various digital signal processing applications such as convolution, correlation, and filters. However, conventional array multipliers, vedic multipliers were resulted in higher area, power, delay consumptions. Therefore, this work is focused on design and implementation of variable width Radix-4 booth multiplier using Data Scaling Technology (DST). The radix-4 modified booth encoding was used in the production of these incomplete items. In accumulation, the bits of the fractional products are added in a parallel manner with decreased stages using a

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3

Mokhtar, Anis Shahida, Chew Sue Ping, Muhamad Faiz Md Din, Nazrul Fariq Makmor, and Muhammad Asyraf Che Mahadi. "Implementation of Booth Multiplier Algorithm using Radix-4 in FPGA." Jurnal Kejuruteraan si4, no. 1 (2021): 161–65. http://dx.doi.org/10.17576/jkukm-2021-si4(1)-20.

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This paper presentsthe performance of Radix-4 Modified Booth Algorithm. Booth algorithm is a multiplication algorithm that multiplies two signed binary numbers in two's complement notation. Multiplier is a fundamental component in general-purpose microprocessors and in digital signal processors. With advances in technology, researchers design multipliers which offer high speed, low power, and less area implementation. Booth multiplier algorithm is designed to reduce number of partial products as compared to conventional multiplier. The proposed design is simulated by using Verilog HDL in Quart

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Bhusare, Saroja S., and V. S. Kanchana Bhaaskaran. "Low-Power High-Accuracy Fixed-Width Radix-8 Booth Multiplier Using Probabilistic Estimation Technique." Journal of Circuits, Systems and Computers 26, no. 05 (2017): 1750079. http://dx.doi.org/10.1142/s0218126617500797.

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In many Multimedia and DSP applications, the fixed-width multipliers are used to avoid infinite growth in the word size. Fixed-width multiplier produces an [Formula: see text]-bit product with two [Formula: see text]-bit inputs. This paper presents probabilistic estimation technique applied for the fixed-width radix-8 Booth multiplier for the generation of the compensation bias circuit. The probabilistic estimation circuit for the fixed-width radix-8 Booth multiplier is derived systematically from theoretical computation in preference to time-consuming exhaustive simulations. Results show that

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5

Suvarna, S., K. Rajesh, and T. Radhu. "A Modified Architecture for Radix-4 Booth Multiplier with Adaptive Hold Logic." International Journal of Students' Research in Technology & Management 4, no. 1 (2016): 01–05. http://dx.doi.org/10.18510/ijsrtm.2016.411.

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High speed digital multipliers are most efficiently used in many applications such as Fourier transform, discrete cosine transforms, and digital filtering. The throughput of the multipliers is based on speed of the multiplier, and then the entire performance of the circuit depends on it. The pMOS transistor in negative bias cause negative bias temperature instability (NBTI), which increases the threshold voltage of the transistor and reduces the multiplier speed. Similarly, the nMOS transistor in positive bias cause positive bias temperature instability (PBTI).These effects reduce the transist

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Sivajyothi, Gogula, and Suman Mishra. "Efficient Compressor and Encoder Strategies for Cost-Effective Radix-4 Approximate Booth Multipliers." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 008 (2024): 1–16. http://dx.doi.org/10.55041/ijsrem37197.

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Multiplication operations are essential in digital systems, and the design of efficient and cost- effective multipliers holds significant importance across various applications. This paper presents a novel methodology aimed at improving the affordability of approximate radix-4 Booth multipliers by proposing simplified designs for compressors and encoders. The primary objective is to achieve a balance between computational accuracy and hardware cost, rendering the multiplier suitable for deployment in low-cost embedded systems and applications where a certain degree of approximation is permissi

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7

Wani, Towseef Ul Haq, and Ravinder Pal Singh. "Implementation of ALU Using Modified Radix-4 Modified Booth Multiplier." International Journal for Research in Applied Science and Engineering Technology 11, no. 2 (2023): 188–200. http://dx.doi.org/10.22214/ijraset.2023.48914.

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Abstract: In this project, we propose a novel multiplier hardware design based on a radix - 4 modified booth encoder. The standard modified Booth encoding (MBE) provides an uneven partial product array due to the extra partial product bit at the least significant bit position of each partial product row. In this brief, a simple technique for constructing a regular partial product array with fewer partial product rows and low overhead is provided, reducing the complexity of partial product reduction as well as the space, time, and power of MBE multipliers. A SPST-based adder is examined and des

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8

Fu, Chengjie, Xiaolei Zhu, Kejie Huang, and Zheng Gu. "An 8-bit Radix-4 Non-Volatile Parallel Multiplier." Electronics 10, no. 19 (2021): 2358. http://dx.doi.org/10.3390/electronics10192358.

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The data movement between the processing and storage units has been one of the most critical issues in modern computer systems. The emerging Resistive Random Access Memory (RRAM) technology has drawn tremendous attention due to its non-volatile ability and the potential in computation application. These properties make them a perfect choice for application in modern computing systems. In this paper, an 8-bit radix-4 non-volatile parallel multiplier is proposed, with improved computational capabilities. The corresponding booth encoding scheme, read-out circuit, simplified Wallace tree, and Manc

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9

Kuo, Chao-Tsung, and Yao-Cheng Wu. "FPGA Implementation of a Novel Multifunction Modulo (2n ± 1) Multiplier Using Radix-4 Booth Encoding Scheme." Applied Sciences 13, no. 18 (2023): 10407. http://dx.doi.org/10.3390/app131810407.

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The residue number system is widely used in applications such as communication systems, cryptography, digital filters, digital signal processors, fault-tolerant detection, and so on. This paper proposes a multifunction modulo (2n ± 1) multiplier based on the radix-4 Booth encoding scheme that can operate both modulo (2n − 1) and modulo (2n + 1) multipliers using the same hardware structure with only one control signal. A novel modulo (2n ± 1) multiplier based on radix-4 Booth encoding is proposed that can achieve superior performance, with low power, fast operation, high area efficiency, and l

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10

Liu, Chenghao, Jingyu Sun, and Ruihong Tang. "A design of multiplier based on Radix_4 Booth algorithm and 4-2 Wallace compression tree." Applied and Computational Engineering 37, no. 1 (2024): 166–76. http://dx.doi.org/10.54254/2755-2721/37/20230498.

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In a multitude of computational and signal processing scenarios, the multiplier functions as a fundamental arithmetic component. Given the complex hardware arrangement of multipliers and their usual positioning within the crucial pathway of digital systems, their significance is substantial. Therefore, approximations of multipliers can greatly optimize system performance. This essay examines the fundamental ideas behind the Wallace tree, the Carry ahead adder, and the Radix-4 Booth algorithm. Additionally, instead of the more common 3-2 compressors, a Wallace tree structure with 4-2 compressor

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K, Soundarya. "DESIGN AND IMPLEMENTATION OF RADIX-4-8 MODIFIED BOOTH’S ENCODER USING FPGA." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 05 (2024): 1–5. http://dx.doi.org/10.55041/ijsrem34671.

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We describe a unique design methodology of approximate radix-4 Booth multipliers that can be produced at a reasonable cost and that can greatly lower the power consumption of signal processing activities that are error-resilient. The suggested method takes into account two important processing steps simultaneously by requiring the generated error directions to be opposite to each other, in contrast to previous studies that only concentrate on the approximation of either the partial product generation with encoders or the partial product reductions with compressors. In comparison to the previou

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12

Adiono, Trio, Hans Herdian, Suksmandhira Harimurti, and Tengku Ahmad Madya Putra. "Design of Compact Modified Radix-4 8-Bit Booth Multiplier." International Journal on Electrical Engineering and Informatics 12, no. 2 (2020): 228–41. http://dx.doi.org/10.15676/ijeei.2020.12.2.4.

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13

Jiménez, Abimael, and Antonio Muñoz. "Very-Large-Scale Integration (VLSI) Implementation and Performance Comparison of Multiplier Topologies for Fixed- and Floating-Point Numbers." Applied Sciences 15, no. 9 (2025): 4621. https://doi.org/10.3390/app15094621.

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Multiplication is an arithmetic operation that has a significant impact on the performance of several real-life applications such as digital signals, image processing, and machine learning. The main concern of electronic system designers is energy optimization with minimal penalties in terms of speed and area for designing portable devices. In this work, a very-large-scale integration (VLSI) design and delay/area performance comparison of array, Wallace tree, and radix-4 Booth multipliers was performed. This study employs different word lengths, with an emphasis on the design of floating-point

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14

Tang, Xiqin, Yang Li, Chenxiao Lin, and Delong Shang. "A Low-Power Area-Efficient Precision ScalableMultiplier with an Input Vector Systolic Structure." Electronics 11, no. 17 (2022): 2685. http://dx.doi.org/10.3390/electronics11172685.

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In this paper, a small-area low-power 64-bit integer multiplier is presented, which is suitable for portable devices or wireless applications. To save the area cost and power consumption, an input vector systolic (IVS) structure is proposed based on four 16-bit radix-8 Booth multipliers and a data input scheme is proposed to reduce the number of signal transitions. This structure is similar to a systolic array in matrix multiply units of a Convolutional Neural Network (CNN), but it reduces the number of processing elements by 3/4 concerning the same vector systolic accelerator in reference. Th

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15

Kollannur, Manju Inasu, and Oudaya Coumar Souprayen. "Designing high power efficient finite impulse response filters with three-four inexact adder-integrated Booth multiplier." IAES International Journal of Robotics and Automation (IJRA) 14, no. 2 (2025): 204. https://doi.org/10.11591/ijra.v14i2.pp204-213.

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Finite impulse response (FIR) filters are widely utilized in several applications in digital signal processing, including data transmission, photography, digital audio, and biomedicine. It is necessary to use high sample rates for FIR filters, while moderate sample rates are needed for low-power circuits. To solve these problems, a Booth multiplier based on three-four inexact adder-based multiplication (TFIE-BM) was proposed. The goal of the proposed TFIE-based FIR Booth multiplier is to lower area usage, latency, and power consumption. The proposed method utilizes the spotted hyena optimizer

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16

Hong, Taeyang, and Jaeyong Chung. "Design and Comparison of Radix-4 and Factored Radix-8 Modified Booth Multiplier for Neural Processing." Journal of the Institute of Electronics and Information Engineers 57, no. 12 (2020): 81–89. http://dx.doi.org/10.5573/ieie.2020.57.12.81.

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17

Ushanandhini and S. Shivkumar Dr. "Designing of IIR Filter using Radix 4 Multiplier by Precharging Technique." International Journal of Trend in Scientific Research and Development 2, no. 4 (2019): 1100–1107. https://doi.org/10.31142/ijtsrd14208.

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Infinite impulse response IIR filter designs mainly aims on either low area cost or high speed or reduced power consumption. Infinite Impulse Response filters are the most important element in signal processing and communication. IIR filters can achieve a given filtering characteristic using less memory and calculations than a similar FIR filter. Multipliers are the basic building block in DSP, microprocessors and other applications. The system's performance is entirely dependent upon the multipliers because they have large area, long latency and consume considerable power hence there is a

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18

.Raut, Prof V. R., and P. R. Loya. "FPGA Implementation of Low Power Booth Multiplier Using Radix-4 Algorithm." International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 03, no. 08 (2014): 11479–86. http://dx.doi.org/10.15662/ijareeie.2014.0308081.

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19

Chang, Yen-Jen, Yu-Cheng Cheng, Shao-Chi Liao, and Chun-Huo Hsiao. "A Low Power Radix-4 Booth Multiplier With Pre-Encoded Mechanism." IEEE Access 8 (2020): 114842–53. http://dx.doi.org/10.1109/access.2020.3003684.

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20

Pilipovic, Ratko, and Patricio Bulic. "On the Design of Logarithmic Multiplier Using Radix-4 Booth Encoding." IEEE Access 8 (2020): 64578–90. http://dx.doi.org/10.1109/access.2020.2985345.

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21

Deng, Weixiang, Wenxiang Cheng, Jie Cheng, Leibin Ni, and Anping He. "8-Bit NCL Asynchronous Multiplier based on Radix-4 Booth Algorithm." IOP Conference Series: Materials Science and Engineering 914 (September 19, 2020): 012024. http://dx.doi.org/10.1088/1757-899x/914/1/012024.

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22

K, P. Heena. "A Comparative Study on Ripple Carry Adder and Modified Square Root Carry Select Adder in Radix-4 8*8 Booth Multiplier." International Journal of Innovative Science and Research Technology (IJISRT) 9, no. 2 (2024): 4. https://doi.org/10.5281/zenodo.10784386.

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In digital circuits multiplication is a fundamental operation, extensively utilized in various computational tasks. The efficiency and performance of the multiplier circuit significantly impact the overall system performances, especially in applications demanding high-speed computation with minimal power consumption. This study presents a comparative analysis between two distinct implementations of Radix-4 8*8 Booth multiplier employing different adder architectures: Ripple carry adder and Modified Square Root Carry select adder. Multiplier with modified square root carry select adder reduced

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23

Md., Zakir Hussain, and Parvin KaziNikhat. "Low power and high performance FFT with different radices." TELKOMNIKA Telecommunication, Computing, Electronics and Control 8, no. 2 (2019): 99–106. https://doi.org/10.11591/ijres.v8.i2.pp99-106.

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FFT is one of the most active blocks in digital signal processing and in various field of communication systems. FFT has received significant attention over the past years to increase its capability and versatility. This paper describes an extensive study on trade-off of different radices with different computational elements of butterfly such as adders and multipliers. Finding an efficient radix along with computational elements is the key point to find best suite i.e. high precision, low power and low area applications like radar, filtering, image compression etc. The work also considers the

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24

Dr., Vasudeva G. "Floating Point Unit with High Precision Efficiency." International Journal of Soft Computing and Engineering (IJSCE) 15, no. 2 (2025): 24–30. https://doi.org/10.35940/ijsce.B3669.15020525/.

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<strong>Abstract:</strong> In this paper, we dive into designing a Single Precision Floating Point Unit (FPU), a key player in modern processors. FPUs are essential for handling complex numerical calculations with high precision and a broad range, making them indispensable in scientific research, graphics rendering, and machine learning—our design centers around two main components: the Brent-Kung adder and the radix-4 Booth multiplier. The BrentKung adder is our go-to for fast addition and subtraction. Thanks to its clever parallel-prefix structure, it minimises delays even as the numbe

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SINGHAL, Subodh K., Sujit K. PATEL, Anurag MAHAJAN та Gaurav SAXENA. "Area-delay eﬀicient Radix-4 8×8 Booth multiplier for DSP applications". TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES 29, № 4 (2021): 2012–28. http://dx.doi.org/10.3906/elk-2007-179.

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26

Esther Rani, Dr T. "Design Of High Performance Configurable Radix-4 Booth Multiplier Using Cadence Tools." CVR Journal of Science & Technology 6, no. 1 (2014): 66–74. http://dx.doi.org/10.32377/cvrjst0611.

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Xue, H., R. Patel, N. V. V. K. Boppana, and S. Ren. "Low‐power‐delay‐product radix‐4 8*8 Booth multiplier in CMOS." Electronics Letters 54, no. 6 (2018): 344–46. http://dx.doi.org/10.1049/el.2017.3996.

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Dr., Vasudeva G. "Floating Point Unit with High Precision Efficiency." International Journal of Soft Computing and Engineering (IJSCE) 15, no. 2 (2025): 24–30. https://doi.org/10.35940/ijsce.B3669.15020525.

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<strong>Abstract:</strong> In this paper, we dive into the design of a Single Precision Floating Point Unit (FPU), a key player in the world of modern processors. FPUs are essential for handling complex numerical calculations with high precision and a broad range, making them indispensable in areas like scientific research, graphics rendering, and machine learning. Our design centers around two main components: the Brent-Kung adder and the radix-4 Booth multiplier. The Brent-Kung adder is our go-to for fast addition and subtraction. Thanks to its clever parallel- prefix structure, it keeps del

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29

Mohanapriya, R., K. Rajesh, and P. S. Sudarshana. "A Modified Architecture of Multiplier and Accumulator using Radix-4 Modified Booth Algorithm." i-manager's Journal on Circuits and Systems 2, no. 4 (2014): 1–6. http://dx.doi.org/10.26634/jcir.2.4.3218.

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30

Esmaeel, Anwar A., Sa’ed Abed, Bassam J. Mohd, and Abbas A. Fairouz. "POSIT vs. Floating Point in Implementing IIR Notch Filter by Enhancing Radix-4 Modified Booth Multiplier." Electronics 11, no. 1 (2022): 163. http://dx.doi.org/10.3390/electronics11010163.

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The increased demand for better accuracy and precision and wider data size has strained current the floating point system and motivated the development of the POSIT system. The POSIT system supports flexible formats and tapered precision and provides equivalent accuracy with fewer bits. This paper examines the POSIT and floating point systems, comparing the performance of 32-bit POSIT and 32-bit floating point systems using IIR notch filter implementation. Given that the bulk of the calculations in the filter are multiplication operations, an Enhanced Radix-4 Modified Booth Multiplier (ERMBM)

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31

Hussain, Md Zakir, and Kazi Nikhat Parvin. "Low power and high performance FFT with different radices." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 2 (2019): 99. http://dx.doi.org/10.11591/ijres.v8.i2.pp99-106.

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<p>FFT is one of the most active blocks in digital signal processing and in various field of communication systems. FFT has received significant attention over the past years to increase its capability and versatility. This paper describes an extensive study on trade-off of different radices with different computational elements of butterfly such as adders and multipliers. Finding an efficient radix along with computational elements is the key point to find best suite i.e. high precision, low power and low area applications like radar, filtering, image compression etc. The work also cons

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32

Kuo, Chao-Tsung, and Yao-Cheng Wu. "Area-Power-Delay-Efficient Multi-Modulus Multiplier Based on Area-Saving Hard Multiple Generator Using Radix-8 Booth-Encoding Scheme on Field Programmable Gate Array." Electronics 13, no. 2 (2024): 311. http://dx.doi.org/10.3390/electronics13020311.

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A multi-modulus architecture based on the radix-8 Booth encoding of a modulo (2n − 1) multiplier, a modulo (2n) multiplier, and a modulo (2n + 1) multiplier is proposed in this paper. It uses the original single circuit and shares many common circuit characteristics with a small extra circuit to carry out multi-modulus operations. Compared with a previous radix-4 study, the radix-8 architecture can increase the modulation multiplication encoding selection from three codes to four codes. This reduces the use of partial products from ⌊n/2⌋ to ⌊n/3⌋ + 1, but it increases the operation complexity

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Ghasemi, Mir Majid, Amir Fathi, Morteza Mousazadeh, and Abdollah Khoei. "A new high speed and low power decoder/encoder for Radix‐4 Booth multiplier." International Journal of Circuit Theory and Applications 49, no. 7 (2021): 2199–213. http://dx.doi.org/10.1002/cta.2985.

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S., SUVARNA, RAJESH K., and VEERAKUMAR S. "Aging Aware Radix-4 Booth Multiplier With Adaptive Hold Logic and Razor Flip Flop." i-manager’s Journal on Electronics Engineering 6, no. 1 (2015): 13. http://dx.doi.org/10.26634/jele.6.1.3681.

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35

Ma, Yanhua, Qican Xu, and Zerui Song. "Resource-Efficient Optimization for FPGA-Based Convolution Accelerator." Electronics 12, no. 20 (2023): 4333. http://dx.doi.org/10.3390/electronics12204333.

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Convolution forms one of the most essential operations for the FPGA-based hardware accelerator. However, the existing designs often neglect the inherent architecture of FPGA, which puts forward an austere challenge on hardware resource. Even though some previous works have proposed approximate multipliers or convolution acceleration algorithms to deal with this issue, the inevitable accuracy loss and resource occupation easily lead to performance degradation. Toward this, we first propose two kinds of resource-efficient optimized accurate multipliers based on LUTs or carry chains. Then, target

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36

Dr. Vasudeva G and Dr Bharathi Gururaj. "Floating Point Unit with High Precision Efficiency." International Journal of Soft Computing and Engineering 15, no. 2 (2025): 24–30. https://doi.org/10.35940/ijsce.b3669.15020525.

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In this paper, we dive into designing a Single Precision Floating Point Unit (FPU), a key player in modern processors. FPUs are essential for handling complex numerical calculations with high precision and a broad range, making them indispensable in scientific research, graphics rendering, and machine learning—our design centers around two main components: the Brent-Kung adder and the radix-4 Booth multiplier. The BrentKung adder is our go-to for fast addition and subtraction. Thanks to its clever parallel-prefix structure, it minimises delays even as the numbers get bigger. For multiplication

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37

G, Vasudeva, and Bharathi Gururaj. "Design of an Efficient Single Precision Floating Point Unit." International Journal of Electrical Engineering and Computer Science 7 (March 26, 2025): 44–54. https://doi.org/10.37394/232027.2025.7.5.

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In this , we design of a Single Precision Floating Point Unit (FPU), a key player in the world of modern processors. FPUs are essential for handling complex numerical calculations with high precision and a broad range, making them indispensable in areas like scientific research, graphics rendering, and machine learning. Our design centers around two main components: the Brent-Kung adder and the radix-4 Booth multiplier. The Brent-Kung adder is our go-to for fast addition and subtraction. Thanks to its clever parallel- prefix structure, it keeps delays minimal even as the numbers get bigger. Fo

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Mohanapriya, R., and K. Rajesh. "A Modified Architecture of Multiplier and Accumulator Using Spurious Power Suppression Technique." International Journal of Students' Research in Technology & Management 3, no. 2 (2015): 258–63. http://dx.doi.org/10.18510/ijsrtm.2015.324.

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High speed and low power Multiplier and Accumulator (MAC) unit is at most requirement of today’s VLSI systems and digital signal processing (DSP) applications like FFT, Finite Impulse response filters, convolution etc. In this modified architecture, Radix-4 Modified Booth Encoding (MBE) is used to produce the partial products. In this multiplication and accumulation has been combined using a hybrid type of Carry Save Adder (CSA). So the performance will be improved. A Carry Look ahead Adder is inserted in the CSA tree to reduce the number of bits in the final adder. In booth multiplication, wh

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Immareddy, Srikanth, Arunmetha Sundaramoorthy, and Aravindhan Alagarsamy. "Adaptive FIR Filter Design with Approximate Adder and Hybridized Multiplier for Efficient Noise Eradication in Sensor Nodes." ECS Journal of Solid State Science and Technology 12, no. 9 (2023): 097002. http://dx.doi.org/10.1149/2162-8777/aceaa9.

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Finite Impulse Response (FIR) filter contributes a major role in most of the signal processing applications. However, the Finite Impulse Response filter performance is restricted by its speed, power and area usage. To address these issues, an adaptive FIR filter design using approximate adder and Hybridizing (Radix-8 Booth and TRAM) Approximate Multiplier (DA-AFIR-leadx-hybam-AC) is proposed in this manuscript for eradicating the noise in the sensor nodes. Here, Low error together with area efficient approximate adder (leadx) is used for reducing path delay and area utilization. For approximat

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Kumar V G, Kiran, and Shantharama Rai C,. "Low Power High Speed Arithmetic Circuits." International Journal of Recent Technology and Engineering (IJRTE) 8, no. 2 (2019): 807–13. http://dx.doi.org/10.35940/ijrte.a1064.078219.

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In the Design of arithmetic circuits reducing area, high speed and power are the major areas in VLSI system design. In this paper parallel prefix adders like Kogge-stone adder, Breunt-Kung adder, Ladner-Fischer adder is designed .Radix-4 Booth multiplier is designed by using Kogge-Stone adder. 16 bit Vedic multiplier is done by using Urdhwa Triyambaka sutra .8bit Vedic division is implemented by using Crumbs method so as to reduce the area, LUT tables and increase the speed as well as to reduce the Power dissipiation. The design is synthesized using Xilinx ISE 14.1 design suite.

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Sun, Rongxue, Huimin Liu, Rong Zhang, and Jiale Qu. "Design and Implementation of RISC-V Based Pipelined Multiplier." Journal of Physics: Conference Series 2625, no. 1 (2023): 012006. http://dx.doi.org/10.1088/1742-6596/2625/1/012006.

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Abstract Among the many microprocessors, RISC-V as an open-source instruction set is gradually gaining popularity among academia and industry. The performance of the multiplier in the microprocessor imposes constraints on the computational power of the processor. In order to improve the efficiency of multiplication instructions, a pipeline multiplier is implemented in this paper. Firstly, the partial product is generated using the Radix-4 booth. Secondly, the Wallace tree structure is used to accelerate the compression of the partial product. Then, a parallel prefix adder is used to calculate

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James, Britto Pari, Man-Fai Leung, Dhandapani Vaithiyanathan, and Karuthapandian Mariammal. "Optimal Realization of Distributed Arithmetic-Based MAC Adaptive FIR Filter Architecture Incorporating Radix-4 and Radix-8 Computation." Electronics 13, no. 17 (2024): 3551. http://dx.doi.org/10.3390/electronics13173551.

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Finite impulse response (FIR) filters are explicitly used in decisive applications such as communication and signal processing areas. Advancement in the latest technologies necessitates specific designs with optimal characteristics. This research work proposes the realization of an efficient distributed arithmetic adaptive FIR filter (DAAFA) architecture using radix-4 and radix-8 computation. Distributed arithmetic (DA) is extensively used to calculate the sum of products without involving a multiplier. The proposed fixed-point realization of a single multiply and accumulate (MAC) FIR adaptive

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James, Britto Pari, Leung Man-Fai, Mariammal Karuthapandian, and Vaithiyanathan Dhandapani. "Delineation of Optimized Single and Multichannel Approximate DA-Based Filter Design Using Influential Single MAC Strategy for Trans-Multiplexer." Sensors 24, no. 22 (2024): 7149. http://dx.doi.org/10.3390/s24227149.

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In this paper, a multichannel FIR filter design based on the Time Division Multiplex (TDM) approach that incorporates one multiply and add unit, regardless of the variable coefficient length and varying channels, by associating the resource sharing doctrine is suggested. A multiplier based on approximate distributed arithmetic (DA) circuits is employed for effective resource optimization. Although no explicit multiplication was conducted in this realization, the radix-8 and radix-4 Booth algorithms are utilized in the DA framework to curtail and optimize the partial products (PPs). Furthermore

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Ma, Xiaolong, Jiangtao Xu, and Guican Chen. "Improved Quantization Error Compensation Method for Fixed-Width Booth Multipliers." VLSI Design 2014 (February 6, 2014): 1–9. http://dx.doi.org/10.1155/2014/451310.

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A novel quantization error (QE) compensation method is proposed in design of high accuracy fixed-width radix-4 Booth multipliers, which will effectively reduce the QE and save the area of multipliers when they are employed in cognitive radio (CR) detector and digital signal processor (DSP). The truncated partial-products of the proposed multipliers are finely divided into three sections: reserved section, adaptive compensation section, and constant compensation section. The QE compensation carries of the multipliers are generated by applying probability estimation based on a shrunken minor tru

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Muralidharan, Ramya, and Chip-Hong Chang. "Radix-4 and Radix-8 Booth Encoded Multi-Modulus Multipliers." IEEE Transactions on Circuits and Systems I: Regular Papers 60, no. 11 (2013): 2940–52. http://dx.doi.org/10.1109/tcsi.2013.2252642.

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Liu, Weiqiang, Liangyu Qian, Chenghua Wang, Honglan Jiang, Jie Han, and Fabrizio Lombardi. "Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing." IEEE Transactions on Computers 66, no. 8 (2017): 1435–41. http://dx.doi.org/10.1109/tc.2017.2672976.

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Patali, Pramod, and Shahana Thottathikkulam Kassim. "Efficient modular hybrid adders and Radix-4 booth multipliers for DSP applications." Microelectronics Journal 96 (February 2020): 104701. http://dx.doi.org/10.1016/j.mejo.2020.104701.

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Cheng, Xiaoshu, Yiwen Wang, Jiazhi Liu, Weiran Ding, Hongfei Lou, and Ping Li. "Booth Encoded Bit-Serial Multiply-Accumulate Units with Improved Area and Energy Efficiencies." Electronics 12, no. 10 (2023): 2177. http://dx.doi.org/10.3390/electronics12102177.

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Bit-serial multiply-accumulate units (MACs) play a crucial role in various hardware accelerator applications, including deep learning, image processing, and signal processing. Despite the advantages of bit-serial MACs, such as a small footprint, full hardware utilization, and high frequency, their serial nature can lead to high latency and potentially compromised performance. This study investigates the potential of bit-serial solutions by applying Booth encoding to bit-serial multipliers within MACs to enhance area and power efficiencies. We present two types of bit-serial MACs based on radix

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Wang, Ren Ping. "Full-Custom Design and Implementation of High-Performance Multiplier." Advanced Materials Research 631-632 (January 2013): 1445–51. http://dx.doi.org/10.4028/www.scientific.net/amr.631-632.1445.

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I proposed a method of using full-custom design 32 × 32 multiplier to enhance performance, reduce the power consumption and the area of layout. I use improved Wallace tree structure for partial product compression, truncated beyond the 64 part of the plot and the look-ahead logarithmic adder using Radix-4 Kogge-Stone tree algorithm raise the multiplier performance. In the design of Booth2 encoding circuit and compression circuit, I use a transmission gate logic design with higher speed and smaller area. I also use Euler path method and heuristic Euler path method to reduce the layout area. The

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Sajid, Asher, Omar S. Sonbul, Muhammad Rashid, Muhammad Arif, and Amar Y. Jaffar. "An Optimized Hardware Implementation of a Non-Adjacent Form Algorithm Using Radix-4 Multiplier for Binary Edwards Curves." Applied Sciences 14, no. 1 (2023): 54. http://dx.doi.org/10.3390/app14010054.

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Binary Edwards Curves (BEC) play a pivotal role in modern cryptographic processes and applications, offering a combination of robust security as well as computational efficiency. For robust security, this article harnesses the inherent strengths of BEC for the cryptographic point multiplication process by utilizing the Non-Adjacent Form (NAF) algorithm. For computational efficiency, a hardware architecture for the NAF algorithm is proposed. Central to this architecture is an Arithmetic Logic Unit (ALU) designed for streamlined execution of essential operations, including addition, squaring, an

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