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Journal articles on the topic 'Rail-to-rail folded cascode amplifier'

Author: Grafiati

Published: 4 June 2025

Last updated: 15 July 2025

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1

Lee, Min Chin, Zth Ru Yang, and Zth Jing Hu. "Implementation of Rail-to-Rail Operational Amplifier for Biomedical Applications." Applied Mechanics and Materials 130-134 (October 2011): 434–37. http://dx.doi.org/10.4028/www.scientific.net/amm.130-134.434.

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This paper proposes gain boosting architecture of a rail-to-rail folded cascaded operational amplifier with CMFB scheme that employing fully differential pair amplifier for applications to biomedical signal process. The proposed rail-to-rail folded cascaded single stage OPA is design and implemented using the TSMC 0.35μm CMOS 2P4M process. Based on simulated and measured results , the chip size is with power dissipation about 1.6mW, input common mode votage range from 0V to 3.3 V, maximum DC gain 82 dB, 114 dB CMRR and 86 dB PSRR.

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2

An, Chang-Ho, and Bai-Sun Kong. "High-Speed Rail-to-Rail Class-AB Buffer Amplifier with Compact, Adaptive Biasing for FPD Applications." Electronics 9, no. 12 (2020): 2018. http://dx.doi.org/10.3390/electronics9122018.

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A high-slew-rate, low-power, CMOS, rail-to-rail buffer amplifier for large flat-panel-display (FPD) applications is proposed. The major circuit of the output buffer is a rail-to-rail, folded-cascode, class-AB amplifier which can control the tail current source using a compact, novel, adaptive biasing scheme. The proposed output buffer amplifier enhances the slew rate throughout the entire rail-to-rail input signal range. To obtain a high slew rate and low power consumption without increasing the static current, the tail current source of the adaptive biasing generates extra current during the

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3

Vasudeva, Gowdagere, and Bidikinamane Venkataramanaiah Uma. "Operational transconductance amplifier-based comparator for high frequency applications using 22 nm FinFET technology." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 2 (2022): 2158–68. https://doi.org/10.11591/ijece.v12i2.pp2158-2168.

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Fin field-effect transistor (FinFET) based analog circuits are gaining importance over metal oxide semiconductor field effect transistor (MOSFET) based circuits with stability and high frequency operations. Comparator that forms the sub block of most of the analog circuits is designed using operational transconductance amplifier (OTA). The OTA is designed using new design procedures and the comparator circuit is designed integrating the sub circuits with OTA. The building blocks of the comparator design such as input level shifter, differential pair with cascode stage and class AB amplifier fo

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4

Zhong, Yi, Faming Yang, Wanjun Yin, and Qing Liu. "A Time-Interleaved Charge Pump Internal Power Supply Generation Circuit." Journal of Physics: Conference Series 2356, no. 1 (2022): 012015. http://dx.doi.org/10.1088/1742-6596/2356/1/012015.

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A charge pump internal power supply generation circuit for rail-to-rail operational amplifier is proposed, which combines a non-overlapping clock signal and a time-interleaved boost charge pump to achieve an internal power supply which is higher than the power supply voltage. A voltage follower is used to avoid glitch during time-interleaving switching. The charge pump internal power supply circuit is realized by 0.5μm CMOS process. The simulation results show that the internal power supply circuit of the charge pump can generate an internal power supply signal which is 1.8V higher than the po

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5

Baghtash, Hassan Faraji, and Rasoul Pakdel. "A Low-Power, High-Gain Amplifier with Rail-to-Rail Operating Capability: Applications to Biomedical Signal Processing." Proceedings of the Pakistan Academy of Sciences: A. Physical and Computational Sciences 58, no. 1 (2021): 71–76. http://dx.doi.org/10.53560/ppasa(58-1)684.

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low-voltage, low-power, rail-to-rail, two-stage trans-conductance amplifier is presented. The structure exploits body-driven transistors, configured in folded-cascode structure. To reduce the power consumption, the transistors are biased in the subthreshold region. The Specter RF simulation results which are conducted in TSMC 180nm CMOS standard process proves the well-performance of the proposed structure. The performance of the proposed structure against process variations is checked through process corners and Monte Carlo simulations. The results prove the robustness of the proposed amplifi

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6

Lai, Jui-Lin, Ting-You Lin, Cheng-Fang Tai та Rong-Jian Chen. "To Design a Cascode LNA by Using Channel-Length-Split Device with Constant-gm in a 0.35 μm Silicon CMOS Technology". Open Materials Science Journal 10, № 1 (2016): 79–88. http://dx.doi.org/10.2174/1874088x01610010079.

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In the paper, the folded-cascode low-noise operational amplifier (LNA) with constant-gm is proposed and analyzed. The channel-length split technique adopted to expand ratio of W/L of the differential pair transistor to improve the performance of LNA for the gain bandwidth product, noise and offset voltage. The channel-length split method is separated differential input transistor into 2 transistors in series. The area of the transistor (W, L) can be properly increased to effectively decrease the flick noise. The double indirect-frequency compensation technique and the clamping circuit are adop

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7

Gowdagere, Vasudeva, and Uma Bidikinamane Venkataramanaiah. "Operational transconductance amplifier-based comparator for high frequency applications using 22 nm FinFET technology." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 2 (2022): 2158. http://dx.doi.org/10.11591/ijece.v12i2.pp2158-2168.

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<p><span>Fin field-effect transistor (FinFET) based analog circuits are gaining importance over metal oxide semiconductor field effect transistor (MOSFET) based circuits with stability and high frequency operations. Comparator that forms the sub block of most of the analog circuits is designed using operational transconductance amplifier (OTA). The OTA is designed using new design procedures and the comparator circuit is designed integrating the sub circuits with OTA. The building blocks of the comparator design such as input level shifter, differential pair with cascode stage and

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8

Hasan, S. M. Rezaul, and Nazmul Ula. "A novel feed-forward compensation technique for single-stage fully-differential CMOS folded cascode rail-to-rail amplifier." Electrical Engineering 88, no. 6 (2005): 509–17. http://dx.doi.org/10.1007/s00202-005-0306-2.

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9

Astrie, Nurasyeila Fifie, and Chiew Wong Yan. "128 mA CMOS LDO with 108 dB PSRR at 2.4 MHz frequency." TELKOMNIKA Telecommunication, Computing, Electronics and Control 17, no. 5 (2019): 2434–44. https://doi.org/10.12928/TELKOMNIKA.v17i5.12795.

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A low dropout (LDO) voltage regulator with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is presented in this paper. Large 1µF off-chip load capacitor is used to achieve the high PSRR. However, this decreases the gain and pushes the LDO’s output pole to lower frequency causing the circuit to become unstable. The proposed LDO uses rail-to-rail folded cascode amplifier to compensate the gain and stability problems. 2nd order curvature characteristic is used in bandgap voltage reference circuit that is applied at the input of the amplifier to minimize t

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10

Jiang, Zhan Peng, Rui Xu, Hai Huang, and Chang Chun Dong. "Design of a Rail-to-Rail Operational Amplifier with Low Supply Voltage and Low Power Dissipation." Applied Mechanics and Materials 380-384 (August 2013): 3275–78. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3275.

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An rail-to-rail operational amplifier is presented in this paper, which is designed by with two op amp, the first level of the structure is the complementary differential structure which will providing input for the operational amplifier, the second level is designed with the structure of folding cascode to get a high gain. The operational amplifier is designed with the TSMC 0.35u m3.3VCMOS mixed analog-digital technology library. The simulated results show that the operational amplifier has a DC gain of 110dB,a GBW of 9.5MHz,a static power dissipation of 0.95mW,a phase margin of 73°,a voltage

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11

Guo, Min, Lixin Wang, Shixin Wang, Jiacheng Lu, and Mengyao Cui. "A Low Mismatch Current Charge Pump Applied to Phase-Locked Loops." Micromachines 15, no. 7 (2024): 913. http://dx.doi.org/10.3390/mi15070913.

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This paper presents a charge pump circuit with a wide output range and low current mismatch applied to phase-locked loops. In this designed structure, T-shaped analog switches are adopted to suppress the non-ideal effects of clock feedthrough, switching time mismatch, and charge injection. A source follower and current splitting circuits are proposed to improve the matching accuracy of the charging and discharging currents and reduce the current mismatch rate. A rail-to-rail high-gain amplifier with a negative feedback connection is introduced to suppress the charge-sharing effect of the charg

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12

Yang, Zhong, Jiaqi Li, Jiangduo Fu, Jiayin Song, Qingsong Cai, and Shushan Qiao. "A 250 °C Low-Power, Low-Temperature-Drift Offset Chopper-Stabilized Operational Amplifier with an SC Notch Filter for High-Temperature Applications." Applied Sciences 15, no. 2 (2025): 849. https://doi.org/10.3390/app15020849.

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This paper proposes a three-stage op amp based on the SOI (silicon-on-insulator) process, which achieves a low offset voltage and temperature coefficient across a wide temperature range from −40 °C to 250 °C. It can be used in aerospace, oil and gas exploration, automotive electronics, nuclear industry, and in other fields where the ability of electronic devices to withstand high-temperature environments is strongly required. By utilizing a SC (Switched Capacitor) notch filter, the op amp achieves low input offset in a power-efficient manner. The circuit features a multi-path nested Miller com

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13

Yoo, Mookyoung, Kyeongsik Nam, Gyuri Choi, et al. "A Single-Bit Incremental Second-Order Delta-Sigma Modulator with Coarse-Fine Input Buffer." Applied Sciences 12, no. 22 (2022): 11651. http://dx.doi.org/10.3390/app122211651.

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This paper presents an incremental second-order delta-sigma modulator with a coarse-fine input buffer in 180-nm CMOS. The modulator’s architecture was implemented as a second-order cascade of integrators with a feedback structure. The switched-capacitor integrator was operated in discrete time, with high-gain amplifiers required to achieve improved performance during the integration phase. The amplifier comprised rail-to-rail input and gain-boosted cascode intermediate stages, thus achieving a high gain and wide input voltage range. The circuit adopts a coarse-fine buffer for higher performanc

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14

Sharan, Tripurari, and Vijaya Bhadauria. "Fully Differential, Bulk-Driven, Class AB, Sub-Threshold OTA With Enhanced Slew Rates and Gain." Journal of Circuits, Systems and Computers 26, no. 01 (2016): 1750001. http://dx.doi.org/10.1142/s0218126617500013.

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This paper presents a single-stage ultra-low-power fully differential operational transconductance amplifier (FD-OTA) with rail-to-rail linear input range operating in weak inversion region. The input core of the OTA is comprised of source degenerated, flipped voltage follower (FVF)-based bulk-driven class AB input pair, into which a regenerative feedback loop has been inserted to boost its bulk transconductance ([Formula: see text]). The proposed FD-OTA has utilized self-cascode current mirror (SC-CM) loads, which increase its open loop gain from nominal intrinsic value of 42[Formula: see tex

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15

Kang, Weilian. "Methods and Designs for Improving Operational Amplifier Performance." Science and Technology of Engineering, Chemistry and Environmental Protection 1, no. 10 (2024). https://doi.org/10.61173/m11xk231.

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This paper reviews recent improvements in operational amplifier design, focusing on key performance aspects such as noise reduction, gain enhancement, gain-bandwidth product improvement, accuracy enhancement, slew rate improvement, and bandwidth increase. The article begins by explaining the fundamental principles of operational amplifiers, including open-loop gain, bandwidth, and noise sources. It then explores various design modifications aimed at enhancing specific characteristics. Five innovative designs are presented: a CMOS operational amplifier with high gain and output swing, a two-sta

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16

Muhaned, Zaidi, Grout Ian, and Khari bin A'ain Abu. "Rail-To-Rail Output Op-Amp Design with Negative Miller Capacitance Compensation." January 2, 2017. https://doi.org/10.5281/zenodo.1129191.

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In this paper, a two-stage op-amp design is considered using both Miller and negative Miller compensation techniques. The first op-amp design uses Miller compensation around the second amplification stage, whilst the second op-amp design uses negative Miller compensation around the first stage and Miller compensation around the second amplification stage. The aims of this work were to compare the gain and phase margins obtained using the different compensation techniques and identify the ability to choose either compensation technique based on a particular set of design requirements. The two o

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