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Relevant bibliographies by topics / RapidSmith2

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Academic literature on the topic 'RapidSmith2'

Author: Grafiati

Published: 4 June 2021

Last updated: 13 February 2022

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Journal articles on the topic "RapidSmith2"

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Yu, Hoyoung, Hansol Lee, Sangil Lee, Youngmin Kim, and Hyung-Min Lee. "Recent Advances in FPGA Reverse Engineering." Electronics 7, no. 10 (October 12, 2018): 246. http://dx.doi.org/10.3390/electronics7100246.

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In this paper, we review recent advances in reverse engineering with an emphasis on FPGA devices and experimentally verified advantages and limitations of reverse engineering tools. The paper first introduces essential components for programming Xilinx FPGAs (Xilinx, San Jose, CA, USA), such as Xilinx Design Language (XDL), XDL Report (XDLRC), and bitstream. Then, reverse engineering tools (Debit, BIL, and Bit2ncd), which extract the bitstream from the external memory to the FPGA and utilize it to recover the netlist, are reviewed, and their limitations are discussed. This paper also covers supplementary tools (Rapidsmith) that can adjust the FPGA design flow to support reverse engineering. Finally, reverse engineering projects for non-Xilinx products, such as Lattice FPGAs (Icestorm) and Altera FPGAs (QUIP), are introduced to compare the reverse engineering capabilities by various commercial FPGA products.

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Sari, Aitzan, and Mihalis Psarakis. "A Flexible Fault Injection Platform for the Analysis of the Symptoms of Soft Errors in FPGA Soft Processors." Journal of Circuits, Systems and Computers 26, no. 08 (April 11, 2017): 1740009. http://dx.doi.org/10.1142/s0218126617400096.

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Due to the high vulnerability of SRAM-based FPGAs in single-event upsets (SEUs), effective fault tolerant soft processor architectures must be considered when we use FPGAs to build embedded systems for critical applications. In the past, the detection of symptoms of soft errors in the behavior of microprocessors has been used for the implementation of low-budget error detection techniques, instead of costly hardware redundancy techniques. To enable the development of such low-cost error detection techniques for FPGA soft processors, we propose an in-depth analysis of the symptoms of SEUs in the FPGA configuration memory. To this end, we present a flexible fault injection platform based on an open-source CAD framework (RapidSmith) for the soft error sensitivity analysis of soft processors in Xilinx SRAM-based FPGAs. Our platform supports the estimation of soft error sensitivity per configuration bit/frame, processor component and benchmark. The fault injection is performed on-chip by a dedicated microcontroller which also monitors processor behavior to identify specific symptoms as consequences of soft errors. The performed analysis showed that these symptoms can be used to build an efficient, low-cost error detection scheme. The proposed platform is demonstrated through an extensive fault injection campaign in the Leon3 soft processor.

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Dissertations / Theses on the topic "RapidSmith2"

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Townsend, Thomas James. "Vivado Design Interface: Enabling CAD-Tool Design for Next Generation Xilinx FPGA Devices." BYU ScholarsArchive, 2017. https://scholarsarchive.byu.edu/etd/6492.

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The popularity of field-programmable gate arrays (FPGA) has grown in recent years due to their potential performance advantages over sequential software, and as a prototyping platform for application-specific integrated circuits (ASIC). Vendors such as Xilinx offer automated tool suites that can be used to program FPGAs based on a RTL description. These tool suites are sufficient forgeneral users, but they usually don't provide the opportunity to integrate custom computer-aideddesign (CAD) tools into the regular design flow. Xilinx first offered this capability in their ISE tool suite with the Xilinx Design Language (XDL). Using XDL, a Xilinx design could be extracted from the regular CAD flow, run through an external tool, and injected back into the flow. Research tools targeting commercial FPGAs have most commonly been based on XDL. Vivado (Xilinx's newest tool suite) no longer supports XDL, preventing similar tools from being created for next-generation devices. Instead, Vivado includes a Tcl interface that exposes Xilinx's internal design and device data structures. Considerable challenges still remain to users attempting to leverage this Tcl interface to develop external CAD tools. This thesis presents the Vivado Design Interface (VDI), a set of file formats and Tcl functions that address the challenges of exporting and importing designs to and from Vivado. To demonstrate its use, VDI has been integrated with RapidSmith2, an external FPGA CAD framework. To the best of our knowledge this work is the first successful attempt to provide an opensource tool-flow that can export designs from Vivado, manipulate them with external CAD tools, and re-import an equivalent representation back into Vivado.

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White, Brad S. "Tincr: Integrating Custom CAD Tool Frameworks with the Xilinx Vivado Design Suite." BYU ScholarsArchive, 2014. https://scholarsarchive.byu.edu/etd/4338.

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The field programmable gate array (FPGA) is appealing as a computational platform because of its ability to be repurposed for a number of different applications and its relatively low design cost. Traditionally, FPGA vendors provide a set of electronic design automation (EDA) tools to assist customers with the implementation of their designs. These tools are necessarily general purpose, and the resulting tool flow does not provide the user much in the way of customization. Frameworks such as RapidSmith and Torc allow for the creation of custom CAD tools that are able to target actual Xilinx FPGA devices. However, they are built on the Xilinx Design Language (XDL), which was discontinued with the introduction of Xilinx's new tool suite Vivado. Instead, Vivado provides direct access to its data structures through a Tcl interface, as well as EDIF and Xilinx Design Constraint (XDC) files. This thesis discusses Vivado's ability to support a custom CAD tool framework similar to RapidSmith and Torc. It provides a detailed description of the CAD-related aspects of Vivado's Tcl API and shows how its command set can be used to integrate a custom CAD tool framework. This is demonstrated through the introduction of Tincr, a suite of two Tcl-based libraries that each encapsulate a separate method for implementing such a framework. The first is the TincrCAD library, a high-level CAD tool framework built within Vivado's Tcl environment. The second is TincrIO, a set of Tcl commands that comprise a file-based interface into Vivado, similar to XDL. These libraries are offered up as evidence that the Vivado Design Suite can provide a foundation for the implementation of custom CAD tools that operate on Xilinx FPGAs for the foreseeable future.

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Lavin, Christopher Michael. "Using Hard Macros to Accelerate FPGA Compilation for Xilinx FPGAs." BYU ScholarsArchive, 2012. https://scholarsarchive.byu.edu/etd/2933.

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Field programmable gate arrays (FPGAs) offer an attractive compute platform because of their highly parallel and customizable nature in addition to the potential of being reconfigurable to any almost any desired circuit. However, compilation time (the time it takes to convert user design input into a functional implementation on the FPGA) has been a growing problem and is stifling designer productivity. This dissertation presents a new approach to FPGA compilation that more closely follows the software compilation model than that of the application specific integrated circuit (ASIC). Instead of re-compiling every module in the design for each invocation of the compilation flow, the use of pre-compiled modules that can be "linked" in the final stage of compilation are used. These pre-compiled modules are called hard macros and contain the necessary physical information to ultimately implement a module or building block of a design. By assembling hard macros together, a complete and fully functional implementation can be created within seconds. This dissertation describes the process of creating a rapid compilation flow based on hard macros for Xilinx FPGAs. First, RapidSmith, an open source framework that enabled the creation of custom CAD tools for this work is presented. Second, HMFlow, the hard macro-based rapid compilation flow is described and presented as tuned to compile Xilinx FPGA designs as fast as possible. Finally, several modifications to HMFlow are made such that it produces circuits with clock rates that run at more than 75% of Xilinx-produced implementations while compiling more than 30X faster than the Xilinx tools.

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Conference papers on the topic "RapidSmith2"

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Haroldsen, Travis, Brent Nelson, and Brad Hutchings. "RapidSmith 2." In FPGA '15: The 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. New York, NY, USA: ACM, 2015. http://dx.doi.org/10.1145/2684746.2689085.

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Lavin, Christopher, Marc Padilla, Philip Lundrigan, Brent Nelson, and Brad Hutchings. "Rapid prototyping tools for FPGA designs: RapidSmith." In 2010 International Conference on Field-Programmable Technology (FPT). IEEE, 2010. http://dx.doi.org/10.1109/fpt.2010.5681429.

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Haroldsen, Travis, Brent Nelson, and Brad Hutchings. "Packing a modern Xilinx FPGA using RapidSmith." In 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, 2016. http://dx.doi.org/10.1109/reconfig.2016.7857180.

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Townsend, Thomas, Brent Nelson, and Mike Wirthlin. "An XDL alternative for interfacing RapidSmith and Vivado." In 2016 26th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2016. http://dx.doi.org/10.1109/fpl.2016.7577385.

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Lavin, Christopher, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent Nelson, and Brad Hutchings. "RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs." In 2011 International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2011. http://dx.doi.org/10.1109/fpl.2011.69.

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