Dissertations / Theses on the topic 'Rasterization'
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Dahlberg, Marina. "Rasterization of Fragmented Spatial Data." Thesis, Umeå universitet, Institutionen för datavetenskap, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:umu:diva-85411.
Full textEker, Steven Mark. "Formal foundations for the design of rasterization algorithms and architectures." Thesis, University of Leeds, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.278276.
Full textDiebel, James Richard. "Bayesian image vectorization : the probabilistic inversion of vector image rasterization /." May be available electronically:, 2008. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.
Full textÖrtegren, Kevin. "Clustered Shading : Assigning arbitrarily shaped convex light volumes using conservative rasterization." Thesis, Blekinge Tekniska Högskola, Institutionen för kreativa teknologier, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-10418.
Full textLinder, Magnus, and Emil Palm. "Asynchronous Shading in Object Space Lighting Compared to Forward Rendering." Thesis, Blekinge Tekniska Högskola, Institutionen för datalogi och datorsystemteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-14878.
Full textHansson, Karl, and Mikael Hernvall. "Performance and Perceived Realism in Rasterized 3D Sound Propagation for Interactive Virtual Environments." Thesis, Blekinge Tekniska Högskola, Institutionen för programvaruteknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-18251.
Full textBakgrund. 3D-ljudpropagering är viktig för inlevelse och realism i interaktiva och dynamiska virtuella miljöer. Dock är detta svårt att modellera på fysiskt träffsäkert sätt med realtidsbegränsningar. Tekniker inom datorgrafik används inom akustikforskning för att öka prestanda, ändock används knappt de synnerligen effektiva rasteriseringsteknikerna, möjligtvis på grund av osäkerhet kring fysisk träffsäkerhet. Lyckligtvis har psykoakustiken visat att uppfattad realism inte är detsamma som fysisk träffsäkerhet. Detta är en indikation på att högpresterande och perceptuellt realistisk 3D-ljudpropagering kan åstadkommas med rasteriseringstekniker. Syfte. Denna avhandling undersöker huruvida 3D-ljudpropagering kan modelleras med hög prestanda och perceptuell realism med rasteriseringstekniker. Metod. En rasteriseringsbaserad lösning för 3D-ljudpropagering implementeras. Dess perceptuella realism mäts genom psykoakustiska utvärderingar. Dess prestanda analyseras genom körtidsmätningar vid varierande antal ljudkällor och trianglar, och teoretiska uträkningar över minnesanvändning. Den perceptuella realismen och prestandan hos den rasteriseringsbaserade lösningen jämförs med en existerande lösning. Resultat. Den rasteriseringsbaserade lösningen påvisar både högre perceptuell realism och prestanda än den existerande lösningen. Slutsatser. 3D-ljudpropagering kan modelleras med hög prestanda och perceptuell realism med rasteriseringsbaserade tekniker. Alltså kan rasteriserad 3D-ljudpropagering bistå med effektivt, billigt och perceptuellt realistiskt 3D-ljud för områden där inlevelse och perceptuell realism är viktiga, såsom videospel, seriösa spel, live underhållningsevents, arkitekturdesign, konstproduktion och träningssimulationer.
Ramachandruni, Radha Krishna. "Design of 3D Accelerator for Mobile Platform." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7082.
Full textImplement a high-level model of computationally intensive part of 3D graphics pipe-line. Increasing popularity of handheld devices along with developments in hardware technology, 3D graphics on mobile devices is fast becoming a reality. Graphics processing is essentially complex and computationally demanding. In order to achieve scene realism and perception of motion, identifying and accelerating bottle necks is crucial. This thesis is about Open-GL graphics pipe-line in general. Software which implements computationally intensive part of graphics pipe-line is built. In essence a rasterization unit that gets triangles with 2D screen, texture co-ordinates and color. Triangles go through scan conversion, texturing and a set of other per-fragment operations before getting displayed on screen.
Ek, Joel. "A Data-Parallel Graphics Pipeline Implemented in OpenCL." Thesis, Linköpings universitet, Institutionen för systemteknik, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-85679.
Full textDufay, Arthur. "High quality adaptive rendering of complex photometry virtual environments." Thesis, Bordeaux, 2017. http://www.theses.fr/2017BORD0692/document.
Full textImage synthesis for movie production never stopped evolving over the last decades. It seems it has reached a level of realism that cannot be outperformed. However, the software tools available for visual effects (VFX) artists still need to progress. Indeed, too much time is still wasted waiting for results of long computations, especially when previewing VFX. The delays or poor quality of previsualization software poses a real problem for artists. However, the evolution of graphics processing units (GPUs) in recent years suggests a potential improvement of these tools. In particular, by implementing hybrid rasterization/ray tracing algorithms, taking advantage of the computing power of these processors and their massively parallel architecture. This thesis explores the different software bricks needed to set up a complex rendering pipeline on the GPU, that enables a better previsualization of VFX. Several contributions have been brought during this thesis. First, a hybrid rendering pipeline was developed (cf. Chapter 2). Subsequently, various implementation schemes of the Path Tracing algorithm have been tested (cf. Chapter 3), in order to increase the performance of the rendering pipeline on the GPU. A spatial acceleration structure has been implemented (cf. Chapter 4), and an improvement of the traversal algorithm of this structure on GPU has been proposed (cf. Section 4.3.2). Then, a new sample decorrelation method, in the context of random number generation was proposed (cf. Section 5.4) and resulted in a publication [Dufay et al., 2016]. Finally, we combined the Path Tracing algorithm with the Many Lights solution, always with the aim of improving the preview of global illumination. This thesis also led to the submission of three patents and allowed the development of two software tools presented in Appendix A
Murray, David. "Legible Visualization of Semi-Transparent Objects using Light Transport." Thesis, Bordeaux, 2018. http://www.theses.fr/2018BORD0326/document.
Full textExploring and understanding volumetric or surface data is one of the challenges of Computer Graphics. The appearance of these data can be modeled and visualized using light transport theory. For the sake of understanding such a data visualization, transparent materials are widely used. If solutions exist to correctly simulate the light propagation and display semi-transparent objects, offering a understandable visualization remains an open research topic. The goal of this thesis is twofold. First, an in-depth analysis of the optical model for light transport and its implication on computer generated images is performed. Second, this knowledge can be used to tackle the problematic of providing efficient and reliable solution to visualize transparent and semi-transparent media. In this manuscript, we first introduce the general optical model for light transport in participating media, its simplification to surfaces, and how it is used in computer graphics to generate images. Second, we present a solution to improve shape depiction in the special case of surfaces. The proposed technique uses light transport as a basis to change the lighting process and modify the materials appearance and opacity. Third, we focus on the problematic of using full volumetric data instead of the simplified case of surfaces. In this case, changing only the material properties has a limited impact, thus we study how light transport can be used to provide useful information for participating media. Last, we present our light transport model for participating media that aims at exploring part of interest of a volume
Lipa, Matúš. "Interaktivní webové výukové aplikace z oblasti vektorové grafiky." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2019. http://www.nusl.cz/ntk/nusl-400884.
Full textPolášek, Tomáš. "Hybridní raytracing v rozhraní DXR." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2019. http://www.nusl.cz/ntk/nusl-403161.
Full textTolunay, John. "Parallel gaming related algorithms for an embedded media processor." Thesis, Linköpings universitet, Informationskodning, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-86154.
Full textMalina, Jakub. "Vytvoření interaktivních pomůcek z oblasti 2D počítačové grafiky." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-219924.
Full text"Rasterization techniques for Chinese outline fonts." Chinese University of Hong Kong, 1994. http://library.cuhk.edu.hk/record=b5887282.
Full textThesis (M.Phil.)--Chinese University of Hong Kong, 1994.
Includes bibliographical references (leaves 72-75).
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Outline Fonts --- p.2
Chapter 1.1.1 --- Advantages and Disadvantages --- p.4
Chapter 1.1.2 --- Representations --- p.4
Chapter 1.1.3 --- Rasterization --- p.5
Chapter 1.2 --- Introduction to This Thesis --- p.6
Chapter 1.2.2 --- Organization --- p.7
Chapter 1.2.1 --- Objectives --- p.7
Chapter 2 --- Chinese Characters Fonts --- p.8
Chapter 2.1 --- Large Character Set --- p.8
Chapter 2.2 --- Font Styles --- p.8
Chapter 2.3 --- Storage Problems --- p.9
Chapter 2.4 --- Hierarchical Structure --- p.10
Chapter 2.5 --- High Stroke Count --- p.11
Chapter 3 --- Rasterization --- p.13
Chapter 3.1 --- The Basic Rasterization --- p.13
Chapter 3.1.1 --- Scan Conversion --- p.14
Chapter 3.1.2 --- Filling Outline --- p.16
Chapter 3.2 --- Font Rasterization --- p.17
Chapter 3.2.1 --- Outline Scaling --- p.17
Chapter 3.2.2 --- Hintings --- p.17
Chapter 3.2.3 --- Basic Rasterization Approach for Chinese Fonts --- p.18
Chapter 3.3 --- Hintings --- p.20
Chapter 3.3.1 --- Phase Control --- p.20
Chapter 3.3.2 --- Auto-Hints --- p.21
Chapter 3.3.3 --- Storage of Hintings Information in TrueType Font and Postscript Font --- p.22
Chapter 4 --- An Improved Chinese Font Rasterizer --- p.24
Chapter 4.1 --- Floating Point Avoidance --- p.24
Chapter 4.2 --- Filling --- p.25
Chapter 4.2.1 --- Filling with Horizontal Scan Line --- p.25
Chapter 4.2.2 --- Filling with Vertical Scan Line --- p.27
Chapter 4.3 --- Hintings --- p.30
Chapter 4.3.1 --- Assumptions --- p.30
Chapter 4.3.2 --- Maintaining Regular Strokes Width --- p.30
Chapter 4.3.3 --- Maintaining Regular Spacing Among Strokes --- p.34
Chapter 4.3.4 --- Hintings of Single Stroke Contour --- p.42
Chapter 4.3.5 --- Storing the Hinting Information in Font File --- p.49
Chapter 4.4 --- A Rasterization Algorithm for Printing --- p.51
Chapter 4.4.1 --- A Simple Algorithm for Generating Smooth Characters --- p.52
Chapter 4.4.2 --- Algorithm --- p.54
Chapter 4.4.3 --- Results --- p.54
Chapter 5 --- Experiments --- p.56
Chapter 5.1 --- Apparatus --- p.56
Chapter 5.2 --- Experiments for Investigating Rasterization Speed --- p.56
Chapter 5.2.1 --- Investigation into the Effects of Features of Chinese Fonts on Rasterization Time --- p.56
Chapter 5.2.2 --- Improvement of Fast Rasterizer --- p.57
Chapter 5.2.3 --- Details of Experiments --- p.57
Chapter 5.3 --- Experiments for Rasterization Speed of Font File with Hints --- p.57
Chapter 6 --- Results and Conclusions --- p.58
Chapter 6.1 --- Observations --- p.58
Chapter 6.1.1 --- Relationship Between Time for Rasterization and Stroke Count --- p.58
Chapter 6.1.2 --- Effects of Style --- p.61
Chapter 6.1.3 --- Investigation into the Observed Relationship --- p.62
Chapter 6.2 --- Improvement of the Improved Rasterizer --- p.64
Chapter 6.3 --- Gain and Cost of Inserting Hints into Font File --- p.68
Chapter 6.3.1 --- Cost --- p.68
Chapter 6.3.2 --- Gain --- p.68
Chapter 6.4 --- Conclusions --- p.69
Chapter 6.5 --- Future Work --- p.69
Appendix
Wu, Yi-Jeng, and 吳怡正. "Clip Space Sample Culling for Stochastic Rasterization." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/02164102420086016468.
Full text國立交通大學
多媒體工程研究所
101
To render realistic camera images, two effects are common : motion blur and defocus blur. We present a novel clip space culling test of stochastic rasterization of motion and defocus blur. This 2-stage test use the clip space information to reduce the samples needed to be coverage tested over camera lens domain (uv) and time domain (t). First we do a rough test to get a conservative range of the camera lens uv bound, and cull the samples outside this bound. Then the second test finds a similar triangular equation for each triangle vertex in xyuvt space. Based on this equation, we cull the rest of samples outside. We present a simple method for the real-time stochastic rasterizer, and achieve a good sample test efficiency with low computation cost.
Chen, Han-wei, and 陳漢瑋. "A Memory-efficient 2D-graphics rasterization scheme." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/23187731082561890261.
Full text國立中山大學
資訊工程學系研究所
101
With the increasing demand of vector graphics applications, how to develop an efficient embedded rendering system becomes a hot issue in recent years. For embedded environment where the memory bandwidth is a very constrained resource, the optimization of buffer access is one of the most critical design issues. In order to achieve better memory access efficiency, this thesis first presents an efficient hierarchical scan-line buffer architecture for two-dimensional (2D) graphics rendering systems by extending a fast buffer-clear method used in three-dimensional (3D) graphics systems. The scan-line buffer is used to determine the interior regions of graphics objects. It will be accessed intensively and consume the major part of the overall memory bandwidth during the graphics rendering process. By using an additional level of auxiliary buffer to denote the status of blocks of scan-line buffer entries, the proposed method can not only be able to clear the scan-line buffer efficiently with much less cycles and data transfer amount, but it can also accelerate the winding count accumulation process significantly. Our experimental results show that the number of data accesses can be reduced by more than 65%, the best case can even be reduced to 76%. Since the size of the whole-frame scan-line buffer is not small, very often the buffer will be placed off-chip. Therefore, the thesis also considers the use of scan-line buffer cache to reduce the off-chip buffer accesses. By using only four cache blocks, the number of off-chip access cycles can be reduced by more than 50%. The other salient features of the proposed scan-line buffer design is that it can be integrated with the depth buffer used in 3D graphics in order to reduce the overall cost by sharing the same buffer circuits. In addition, the auxiliary buffer can be further expanded into more levels of hierarchy to achieve more saving of data accesses. In addition to the new scan-line buffer design, the paper also proposes an inverse-path-order-filling approach which can avoid the redundant access for those pixels encircled by more than one path. For some test objects, the saving of pixel update number can be up to 50%
Kuo, Chi-Lie, and 郭啓烈. "Hybrid Rendering Architecture for Photon Mapping and Rasterization." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/r59rdn.
Full text國立交通大學
資訊科學與工程研究所
106
In this thesis, we propose the hybrid rendering architecture for photon mapping and rasterization. The hybrid rendering mask for our hybrid rendering will be created by the object material, shadow area detection, and triangle photon density information. Then, the rendering method either uses rasterization or use photon mapping in this area will be determined by this mask. The hybrid rendering can provide about 61% lower rendering time than photon mapping, and better image quality than rasterization in Cornell-box. Furthermore, we implement the hardware units for traversal and intersection (T&I), and use the hardware unit to accelerate the operations. The hardware unit is implemented in TSMC 90nm process. The speedup with hardware unit operated at 166 MHz is about 90 times of the time executed on the software in Microsoft Visual Studio 2013 with Intel® Core™ i5-4570 CPU.
Wang, Hui-Shiun, and 王慧勳. "A Study on the Rasterization of Digital Contours." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/49918467933716734999.
Full text國立臺灣大學
地理學研究所
85
Grid DTM is the most popular structure in representing DTMs. Traditional topographic maps are informative and widely available thus make them an ideal source for creating grid DTMs. The data quality of resulted grid DTMs from contours is affected by factors including: interpolation method being used, quality of original contour map, and characteristics of terrain area. This paper investigates the effect of these factors by a series of tests using real terrain data. Two contour data sets are created from each of four 1/5000 topographic maps. These contours are interpolated using the four methods provided by ARC/INFO GRID modules: IDW, Kriging, Trend and Spline. The difference between these methods is significant. Result of tests shows that trend and spline are not suitable for interpolation terrain contours. The result of IDW and Kriging are close and better than that created from trend and spline methods. Accuracy of resulted DTMs decreases as resolution reduces, and the result is smothered. The maximum slope of the coverage with resolution of 40 meter is smaller than that of the coverage with a 10 meter resolution, and its standard deviation and mean are also smaller. The interval of contour is another factor influencing the accuracy of results. If more accurate results are needed, users should use contours with smaller interval. The characteristics of terrain is another critical factor. The accuracy of results will be higher for simple terrain area. Topogrid is another interpolation provided by ARC/INFO. In general, it performs better in area of complicated terrain.
Si-YuHuang and 黃斯榆. "Scalable and Reconfigurable Rasterization Architecture for Scanline-based Rendering." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/88244385695203455945.
Full textSvensson, Marcus. "Occlusion Culling on the GPU : Inner Conservative Occluder Rasterization." Thesis, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-12003.
Full textZeng, Cheng-Yuan, and 曾誠源. "An Efficient Hybrid Rendering Algorithm for Photon-Mapping and Rasterization." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/a886kn.
Full text國立交通大學
資訊科學與工程研究所
106
In this thesis, we will propose the hybrid rendering with photon mapping and rasterization. Using the stencil test supported by OpenGL to detect the shadow, mirror, and glass area in the scene. We also propose the tile-based photon density test (TiPDT) to find the caustic area in advanced. Then, the shadow, mirror, glass, and caustic area will be drawn by photon mapping, the other materials like diffuse will be rendered by rasterization. Compared with hybrid ray tracing and rasterization rendering, our proposed hybrid rendering method can draw all caustic areas in the scene, to get the more complete global illumination effects. Our simulation is executed by Visual Studio 2015 with Core™ i7-6700 CPU. The saving time can be achieved up to 65% than photon mapping for Cornell-box scene 2. Compared with rasterization rendering also retains the global illumination effects like caustic, soft shadow. As a result, our proposed hybrid rendering algorithm not only reduces the rendering time, but also gets the more complete global illumination effects.
Chen, Hong-Wei, and 陳浤偉. "Pre-rasterization blocked-Z test and its impact on system design." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/98299233143509447058.
Full text國立交通大學
資訊科學與工程研究所
97
We propose a blocked-Z test to effectively eliminate unnecessary data traffic between triangle setup and rasterization. This method works seamlessly with the existing rendering pipeline, with or without those existing fragment-based hierarchical Z/early Z/Z tests. And it performs much better than primitive-based Z test, in terms of data structuring and coverage. In this method, primitives are blocked into proper sizes and blocked-Z tested to filter out the most of hidden blocks, easing the storage and workloads of subsequent rendering tasks. Advantage of this method comes from two features: the blocked test, in which only one test may be sufficient to filter out a group (of the block size) of fragments; and the place of the test saving even unnecessary rasterization. Block sizes are determined statically without hardware nor runtime overhead, and an additional blocked-Z buffer, of the size of [Z buffer/(# fragments in block)], plus blocking and Z-test circuitry, are required. This design lengthens the rendering pipeline, but will not affect the throughput; in fact, it may even increase throughput, since a common wisdom is that the fragment-based pipeline stages are graphics rendering bottlenecks, and our proposal effectively relieves these bottlenecks. Experimental results using Doom3 and Quake4 with various screen sizes show that the rasterization and Z test workloads can be saved by 70%.
Chuang, Chin Chieh, and 莊沁傑. "Image Quality and Performance Comparison between GPU Ray Tracing and Rasterization." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/84373853428142458731.
Full text國立臺灣師範大學
資訊教育學系
102
With faster graphics processors and GPGPU languages, we have the ability to compute more complex data. However, we found few people want to simulate ray tracing on the graphics processor which can render high quality pictures. The developers think the cost of generating one frame is expensive by tracing rays. Besides, they are not willing to learn new GPGPU languages such as OpenCL and CUDA, because of the lack of powerful and convenient engines. In order to achieve that purpose, we offer two methods: One Pass Rendering Algorithm and Hybrid Rendering Algorithm to implement ray tracing on Shader and also implement the Phong lighting effect and the environment reflection effect. We compare the image quality and performance between rasterization and our Shader based ray tracing by different kinds of scenes and we also quantify the results of this comparison. We show the difference between GPU ray tracing and rasterization and we explain the pros and cons of them. The performance of rasterization is better than ray tracing, but we do not need to be worry about it. Because we do not get the larger performance gaps between GPU ray tracing and rasterization by increasing effects. On the contrary, we can gain higher image quality by using ray tracing technology. According to this experiment, we successfully prove the possibility of ray tracing simulation technology on GPU.
Liang, Bor-Sung, and 梁伯嵩. "The Hardware Design for Rasterization with Antialiasing in 3-D Graphics Processor." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/26917457636341695610.
Full text國立交通大學
電子研究所
84
3-D Computer graphics has played an important role in multimedia and virtual reality systems. Up to the beginning ofthe 1990s, applications of 3-D graphics emerge rapidly from technical areas to non-technical areas. Therefore the goal of state-of-the-art 3-D graphics hardware design not only focus on high performance and quality, but also low cost and system integration. In this thesis, a 3-D graphics processor is proposed to improvethe rendering performance, and the hardware of rasterizationunit with antialiasing capacity is designed. By making use ofthe parallelism in pixel data, the system block of 3-D graphics processor is analyzed to reduce the redundant internal bus routing and registers. The DDA (Digital Differential Analyzer) operation and antialiasing are both the time critical units in the hardware design for rasterization. To improve the time critical condition, we develop two architecture designs: The first is self carry routing adder (SCRA) for DDA operations. The DDA operations suffer the low hardware utilization caused by the various lengths of add operations. By segmentation, rearrangement and dynamic carry routing, The SCRA design can reduce the delay time (10.51ns in 0.03pf load) and raise the hardware utilization (92.93%). The second is the sub- scanline antialiasing algorithm for real-time antialiasing. The delay time is reduced (7.6ns in 0.03pf load) and only moderate area is necessary. All design for this 3-D graphics processor is based on the 0.5 um CMOS cell library of Philips.
Cho, Hsiao-Shuang, and 卓曉霜. "Texture-Compression and -Cache Driven Schemes for an Energy-Efficient Rasterization Engine." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/54731940288765924804.
Full text國立交通大學
資訊科學與工程研究所
100
In this thesis, an energy-efficient rasterization engine with cluster-based texture compression and multilevel heterogeneous texture cache schemes is presented to mitigate the bandwidth problem. The compression scheme is built on the S3TC and k-means clustering algorithms, and reduces five-sixth of data with acceptable compression quality. It outperforms standard S3TC in terms of PSNR with approximately 1.0 dB. Further, for hardware design consideration, the decompression is multiplier-free. The multilevel cache takes the texture compression into account, which not only allows small cache size but also decreases the frequency of fetching data from external memory. It has 128 bytes level-1 cache and 2KB level-2 cache, and the hit rate can achieve above 95% with lower image resolution. As a result, these two techniques effectively reduce the processing time of rasterization system to alleviate the memory bandwidth problem and enhance 75% energy efficiency. The proposed rasterization engine architecture is implemented in TSMC 90nm CMOS process and the energy efficiency achieves 3.47 Mpixels/mJ at 166 MHz.
Carvalho, Rúben André Campos de. "Combining the Ray Marching and Rasterization rendering models to provide real-time high-fidelity graphics." Dissertação, 2020. https://hdl.handle.net/10216/128348.
Full textCarvalho, Rúben André Campos de. "Combining the Ray Marching and Rasterization rendering models to provide real-time high-fidelity graphics." Master's thesis, 2020. https://hdl.handle.net/10216/128348.
Full textLiou, Jhe-Yu, and 劉哲宇. "Design, Analysis, and Implementation of a Rasterization Engine based on Tile-Based Rendering Architecture in 3D Graphics." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/69577498780347057023.
Full text國立成功大學
電腦與通信工程研究所
97
3D graphic rendering system for desktop has been developed for a long time and has the capability to show amazing 3D effect. However, this system is hard to be integrated with mobile electronic products because of its large-area requirement, high temperature, and high-power consumption. Due to the rapid development of embedded system and hardware technology, and increasing demand of 3D graphic applications for consumer electronic, how to design a low-cost 3D graphic accelerator has become an important issue. A typical 3D graphic accelerator can be divided into a geometry engine and a rasterization engine by the different processing stages. In this thesis, a highly efficient rasterization engine based on tile-based architecture is proposed. This engine has incorporated the following architecture techniques: tile-boundary skip traversal, barycentric coordinate, multi Z test, and 6D block texture cache. With these features, we reduce the area cost and improve the performance of the rasterization engine we design. The rasterization engine when synthesized with TSMC 0.18um technology can run up to 200MHz. We also verify the entire 3D graphic accelerator net-list with OpenGL ES application in Linux OS under a full system simulation platform constructed with CoWare and QEMU.
Inglis, Tiffany C. "Pixelating Vector Art." Thesis, 2014. http://hdl.handle.net/10012/8136.
Full textHsu, Rei Ting, and 徐叡霆. "An Experimental Study with ESL and HLS of Hardware Accelerators for 3D Graphics Rasterization on a Many-Core System." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/k679qs.
Full text國立清華大學
電機工程學系
105
ESL platforms have been built to overcome the design challenges posed by RTL including complex design entries and long verification process, especially for large many-core architectures. However, accuracy of ESL simulation may limit the application of raising to a higher abstraction level. In this thesis, we demonstrate that it's possible to create a fast and accurate ESL platform. First, we start from a parallel software for 3D graphics rasterization on a 44-mesh architecture (with an RTL definition). By profiling the software on an ESL platform based on instruction-level accuracy (hence no timing), we partition the part with a high-instruction count and implement it with a high-level synthesis flow. After verifying the HLS hardware on RTL, we try to augment the ESL platform for all components with correct timings (end-to-end software cycle errors are less than 5\% as compared with RTL). Finally, we are able to run a fast simulation (up to 10x10 mesh with hardware accelerators) to show the overall performance for different configuration of hardware on the ESL platform.