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Scott, Hazel Jean Carleton University Dissertation Engineering Electrical. "Automatic code generation for real time systems." Ottawa, 1991.
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Däumler, Martin. "Real-time Code Generation in Virtualizing Runtime Environments." Doctoral thesis, Universitätsbibliothek Chemnitz, 2015. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-162075.
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Modern general purpose programming languages like Java or C# provide a rich feature set and a higher degree of abstraction than conventional real-time programming languages like C/C++ or Ada. Applications developed with these modern languages are typically deployed via platform independent intermediate code. The intermediate code is typically executed by a virtualizing runtime environment. This allows for a high portability. Prominent examples are the Dalvik Virtual Machine of the Android operating system, the Java Virtual Machine as well as Microsoft .NET’s Common Language Runtime. The virtualizing runtime environment executes the instructions of the intermediate code. This introduces additional challenges to real-time software development. One issue is the transformation of the intermediate code instructions to native code instructions. If this transformation interferes with the execution of the real-time application, this might introduce jitter to its execution times. This can degrade the quality of soft real-time systems like augmented reality applications on mobile devices, but can lead to severe problems in hard real-time applications that have strict timing requirements. This thesis examines the possibility to overcome timing issues with intermediate code execution in virtualizing runtime environments. It addresses real-time suitable generation of native code from intermediate code in particular. In order to preserve the advantages of modern programming languages over conventional ones, the solution has to adhere to the following main requirements:
- Intermediate code transformation does not interfere with application execution
- Portability is not reduced and code transformation is still transparent to a programmer
- Comparable performance
Existing approaches are evaluated. A concept for real-time suitable code generation is developed. The concept bases on a pre-allocation of the native code and the elimination of indirect references, while considering and optimizing startup time of an application. This concept is implemented by the extension of an existing virtualizing runtime environment, which does not target real-time systems per se. It is evaluated qualitatively and quantitatively. A comparison of the new concept to existing approaches reveals high execution time determinism and good performance and while preserving the portability deployment of applications via intermediate code.
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Almohammad, Ali. "Rigorous code generation for distributed real-time embedded systems." Thesis, Northumbria University, 2013. http://nrl.northumbria.ac.uk/14825/.
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This thesis addresses the problem of generating executable code for distributed embedded systems in which computing nodes communicate using the Controller Area Network (CAN). CAN is the dominant network in automotive and factory control systems and is becoming increasingly popular in robotic, medical and avionics applications. The requirements for functional and temporal reliability in these domains are often stringent, and testing alone may not offer the required level of con dence that systems satisfy their specications. Consequently, there has been considerable research interest in additional techniques for reasoning about the behaviour of CAN-based systems. This thesis proposes a novel approach in which system behaviour is specifed in a high-level language that is syntactically similar to Esterel but which is given a formal semantics by translation to bCANDLE, an asynchronous process calculus. The work developed here shows that bCANDLE systems can be translated automatically, via a common intermediate net representation, not only into executable C code but also into timed automaton models that can be used in the formal verification of a wide range of functional and temporal properties. A rigorous argument is presented that, for any system expressed in the high-level language, its timed automaton model is a conservative approximation of the executable C code, given certain well-defined assumptions about system components. It is shownthat an off-the-shelf model-checker (UPPAAL) can be used to verify system properties with a high-level of confidence that those properties will be exhibited by the executable code. The approach is evaluated by applying it to four representative case studies. Our results show that, for small to medium-sized systems, the generated code is sufficiently efficient for execution on typical hardware and the generated timed automaton model is sufficiently small for analysis within reasonable time and memory constraints.
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Zhang, Da Qing. "Automatic code generation for real-time reactive systems in TROMLAB environment." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/MQ59345.pdf.
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Galparsoro, Miguel Angel Maiza. "Automatic scheduling and parallel code generation for high performance real-time systems." Thesis, University of York, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.288061.
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TAVARES, Eduardo Antônio Guimarães. "Software Synthesis for Energy-Constrained Hard Real-Time Embedded Systems." Universidade Federal de Pernambuco, 2009. https://repositorio.ufpe.br/handle/123456789/1403.
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Previous issue date: 2009A grande expansão do mercado de dispositivos digitais tem forçado empresas desenvolvedoras de sistemas embarcados em lidar com diversos desafios para prover sistemas complexos nesse nicho de mercado. Um dos desafios prominentes está relacionado ao consumo de energia, principalmente, devido aos seguintes fatores: (i) mobilidade; (ii) problemas ambientais; e (iii) o custo da energia. Como consequência, consideráveis esforços de pesquisa têm sido dedicados para a criação de técnicas voltadas para aumentar a economia de energia. Na última década, diversas técnicas foram desenvolvidas para reduzir o consumo de energia em sistemas embarcados. Muitos métodos lidam com gerenciamento dinâmico de energia (DPM), como, por exemplo, dynamic voltage scaling (DVS), cooperativamente com sistemas operacionais especializados, a fim de controlar o consumo de energia durante a execução do sistema. Entretanto, apesar da disponibilidade de muitos métodos de redução de consumo de energia, diversas questões estão em aberto, principalmente, no contexto de sistemas de tempo real crítico. Este trabalho propõe um método de síntese de software, o qual leva em consideração relação entre tarefas, overheads, restrições temporais e de energia. O método é composto por diversas atividades, as quais incluem: (i) medição; (ii) especificação; (iii) modelagem formal; (vi) escalonamento; e (v) geração de código. O método também é centrado no formalismo redes de Petri, o qual define uma base para geração precisa de escalas em tempo de projeto, adotando DVS para reduzir o consumo de energia. A partir de uma escala viável, um código customizado é gerado satisfazendo as restrições especificadas, e, dessa forma, garantindo previsibilidade em tempo de execução. Para lidar com a natureza estática das escalas geradas em tempo de projeto, um escalonador simples em tempo de execução é também proposto para melhorar o consumo de energia durante a execução do sistema. Diversos experimentos foram conduzidos, os quais demonstram a viabilidade da abordagem proposta para satisfazer restrições críticas de tempo e energia. Adicionalmente, um conjunto integrado de ferramentas foram desenvolvidas para automatizar algumas atividades do método de síntese de software proposto
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Däumler, Martin [Verfasser], Matthias [Akademischer Betreuer] Werner, Matthias [Gutachter] Werner, and Wolfram [Gutachter] Hardt. "Real-time Code Generation in Virtualizing Runtime Environments / Martin Däumler ; Gutachter: Matthias Werner, Wolfram Hardt ; Betreuer: Matthias Werner." Chemnitz : Universitätsbibliothek Chemnitz, 2015. http://d-nb.info/1214303579/34.
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Wehrmeister, Marco Aurélio. "An aspect-oriented model-driven engineering approach for distributed embedded real-time systems." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2009. http://hdl.handle.net/10183/17792.
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Atualmente, o projeto de sistemas tempo-real embarcados e distribuídos está crescendo em complexidade devido à sua natureza heterogênea e ao crescente número e diversidade de funções que um único sistema desempenha. Sistemas de automação industrial, sistemas eletrônicos em automóveis e veículos aéreos, equipamentos médicos, entre outros, são exemplos de tais sistemas. Tais sistemas são compostos por componentes distintos (blocos de hardware e software), os quais geralmente são projetados concorrentemente utilizando modelos, ferramentas e linguagens de especificação e implementação diferentes. Além disso, estes sistemas tem requisitos específicos e importantes, os quais não representam (por si só) as funcionalidades esperadas do sistema, mas podem afetar a forma como o sistema executa suas funcionalidades e são muito importantes para a realização do projeto com sucesso. Os chamados requisitos não-funcionais são difíceis de tratar durante todo o ciclo de projeto porque normalmente um único requisito não-funcional afeta vários componentes diferentes. A presente tese de doutorado propõe a integração automatizada das fases de projeto de sistemas tempo-real embarcados e distribuídos focando em aplicações na área da automação. A abordagem proposta usa técnicas de engenharia guiada por modelos (do inglês Model Driven Engineering ou MDE) e projeto orientado a aspectos (do inglês Aspect-Oriented Design ou AOD) juntamente com o uso de plataformas previamente desenvolvidas (ou desenvolvida por terceiros) para projetar os componentes de sistemas tempo-real embarcados e distribuídos. Adicionalmente, os conceitos de AOD permitem a separação no tratamento dos requisitos de naturezas diferentes (i.e. requisitos funcionais e não-funcionais), melhorando a modularização dos artefatos produzidos (e.g. modelos de especificação, código fonte, etc.). Além disso, esta tese propõe uma ferramenta de geração de código, que suporta a transição automática das fases iniciais de especificação para as fases seguintes de implementação. Esta ferramenta usa um conjunto de regras de mapeamento, que descrevem como elementos nos níveis mais altos de abstração são mapeados (ou transformados) em elementos dos níveis mais baixos de abstração. Em outras palavras, tais regras de mapeamento permitem a transformação automática da especificação inicial, as quais estão mais próximo do domínio da aplicação, em código fonte para os componentes de hardware e software, os quais podem ser compilados e sintetizados por outras ferramentas para se obter a realização/implementação do sistema tempo-real embarcado e distribuído.Currently, the design of distributed embedded real-time systems is growing in complexity due to the increasing amount of distinct functionalities that a single system must perform, and also to concerns related to designing different kinds of components. Industrial automation systems, embedded electronics systems in automobiles or aerial vehicles, medical equipments and others are examples of such systems, which includes distinct components (e.g. hardware and software ones) that are usually designed concurrently using distinct models, tools, specification, and implementation languages. Moreover, these systems have domain specific and important requirements, which do not represent by themselves the expected functionalities, but can affect both the way that the system performs its functionalities as well as the overall design success. The so-called nonfunctional requirements are difficult to deal with during the whole design because usually a single non-functional requirement affects several distinct components. This thesis proposes an automated integration of distributed embedded real-time systems design phases focusing on automation systems. The proposed approach uses Model- Driven Engineering (MDE) techniques together with Aspect-Oriented Design (AOD) and previously developed (or third party) hardware and software platforms to design the components of distributed embedded real-time systems. Additionally, AOD concepts allow a separate handling of requirement with distinct natures (i.e. functional and non-functional requirements), improving the produced artifacts modularization (e.g. specification model, source code, etc.). In addition, this thesis proposes a code generation tool, which supports an automatic transition from the initial specification phases to the following implementation phases. This tool uses a set of mapping rules, describing how elements at higher abstraction levels are mapped (or transformed) into lower abstraction level elements. In other words, suchmapping rules allow an automatic transformation of the initial specification, which is closer to the application domain, in source code for software and hardware components that can be compiled or synthesized by other tools, obtaining the realization/ implementation of the distributed embedded real-time system.
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Murali, madhavan rathai Karthik. "Synthesis and real-time implementation of parameterized NMPC schemes for automotive semi-active suspension systems." Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT052.
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Cette thèse traite de la synthèse et de la mise en œuvre en temps réel (RT) de schémas de contrôle prédictif non linéaire paramétré (pNMPC) pour les systèmes de suspension semi-active des automobiles. Le schéma pNMPC est basé sur une technique d'optimisation par simulation en boîte noire. Le point essentiel de la méthode est de paramétrer finement le profil d'entrée et de simuler le système pour chaque entrée paramétrée et d'obtenir la valeur approximative de l'objectif et de la violation des contraintes pour le problème pNMPC. Avec les résultats obtenus de la simulation, l'entrée admissible (si elle existe) ayant la valeur objective minimale ou, à défaut, la valeur de violation de contrainte la plus faible est sélectionnée et injectée dans le système et ceci est répété indéfiniment à chaque période de décision. La méthode a été validée expérimentalement sur dSPACE MicroAutoBoX II (MABXII) et les résultats montrent de bonnes performances de l'approche proposée. La méthode pNMPC a également été étendue à une méthode pNMPC parallélisée et la méthode proposée a été mise en œuvre pour le contrôle du système de suspension semi-active d'un demi-véhicule. Cette méthode a été mise en œuvre grâce à des unités de traitement graphique (GPU) qui servent de plate-forme modèle pour la mise en œuvre d'algorithmes parallèles par le biais de ses processeurs multi-cœurs. De plus, une version stochastique de la méthode pNMPC parallélisée est proposée sous le nom de schéma pNMPC à Scénario-Stochastique (SS-pNMPC). Cette méthode a été mise en œuvre et testée sur plusieurs cartes NVIDIA embarquées pour valider la faisabilité de la méthode proposée pour le contrôle du système de suspension semi-active d'un demi-véhicule. En général, les schémas pNMPC parallélisés offrent de bonnes performances et se prêtent bien à un large espace de paramétrage en entrée. Enfin, la thèse propose un outil logiciel appelé "pNMPC - A code generation software tool for implementation of derivative free pNMPC scheme for embedded control systems". L'outil logiciel de génération de code (S/W) a été programmé en C/C++ et propose également une interface avec MATLAB/Simulink. Le logiciel de génération de code a été testé pour divers exemples, tant en simulation que sur du matériel embarqué en temps réel (MABXII), et les résultats semblent prometteurs et viables pour la mise en œuvre de la RT pour des applications réelles. L'outil de génération de code S/W comprend également une fonction de génération de code GPU pour une mise en œuvre parallèle. Pour conclure, la thèse a été menée dans le cadre du projet EMPHYSIS et les objectifs du projet s'alignent sur cette thèse et les méthodes pNMPC proposées sont compatibles avec la norme eFMIThis thesis discusses the synthesis and real-time (RT) implementation of parameterized Nonlinear Model Predictive Control (pNMPC) schemes for automotive semi-active suspension systems. The pNMPC scheme uses a black-box simulation-based optimization method. The crux of the method is to finitely parameterize the input profile and simulate the system for each parameterized input and obtain the approximate objective and constraint violation value for the pNMPC problem. With the obtained results from the simulation, the input with minimum objective value or the least constraint violation value is selected and injected into the system and this is repeated in a receding horizon fashion. The method was experimentally validated on dSPACE MicroAutoBoX II (MABXII) and the results display good performance of the proposed approach. The pNMPC method was also augmented to parallelized pNMPC and the proposed method was implemented for control of semi-active suspension system for a half car vehicle. This method was implemented by virtue of Graphic Processing Units (GPUs) which serves as a paragon platform for implementation of parallel algorithms through its multi-core processors. Also, a stochastic version of the parallelized pNMPC method is proposed which is termed as Scenario-Stochastic pNMPC (SS-pNMPC) scheme and the method was implemented and tested on several NVIDIA embedded boards to verify and validate the RT feasibility of the proposed method for control of semi-active suspension system for a half car vehicle. In general, the parallelized pNMPC schemes provide good performance and also, fares well for large input parameterization space. Finally, the thesis proposes a software tool termed “pNMPC – A code generation software tool for implementation of derivative free pNMPC scheme for embedded control systems”. The code generation software (S/W) tool was programmed in C/C++ and also, provides interface to MATLAB/Simulink. The S/W tested for variety of examples both in simulation as well as on RT embedded hardware (MABXII) and the results looks promising and viable for RT implementation for real world applications. The code generation S/W tool also includes GPU code generation feature for parallel implementation. To conclude, the thesis was conducted under the purview of the EMPHYSIS project and the goals of the project align with this thesis and the proposed pNMPC methods are amenable with eFMI standard
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Husseini, Orabi Mahmoud. "Facilitating the Representation of Composite Structure, Active objects, Code Generation, and Software Component Descriptions in the Umple Model-Oriented Programming Language." Thesis, Université d'Ottawa / University of Ottawa, 2017. http://hdl.handle.net/10393/36452.
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For a long time, the development of component-based systems has been a crucial part of real-time software development required for embedded and automotive domains. However, most of the existing tools used in these fields are not only proprietary, but also expensive and not research-friendly. Open-source tools in this domain are so far quite limited in terms of the features supported, especially, code generation.
In this thesis, we demonstrate how we can improve the development of real-time and concurrent systems by the introduction of component-based modelling into Umple, an open-source modelling tool. Our work enables component-based modelling to be performed both textually and visually, as is the case with other Umple features.
We introduce a number of major features into Umple. First, we introduce support for real-time C++ code generation. This includes supporting all Umple features, such as class diagrams, associations, state machines, and attributes. In order to achieve this, we also introduce Umple Template Language (Umple-TL), which helps Umple developers to use Umple itself to emit text using easy-to-use constructs, such that the text emitted can be in different target languages such Java and C++. Umple-TL provides additional capabilities relying on Umple being a model-oriented and object-oriented language. Umple-TL has become the technology for all code generation in Umple, not just our real-time C++ generators. Umple-TL also plays a vital role easing writing component descriptions
Second, we support concurrency, which is crucial for the underlying architecture of composite structure. We have to avoid relying on any third-party libraries in order to make sure that the code generated will be deployable on embedded devices, which are limited and do not provide a lot of options. The concurrency pattern we follow extends the active object pattern aiming to enhance communication among active objects. Concurrency development in general, even if a programming language used is not real-time, is not easy. Hence, we simplify active object concepts, such as future, promise, and delay, using new Umple keywords.
We also add composite structure support to Umple, we believe that our syntax and language constructs are comprehensive, and do not require a wide knowledge of modelling and UML concepts. Additionally, we introduce a novel protocol-free approach that dynamically extracts communication protocols from ports, bindings, and active objects as a way to simplify development, and to lead to concise and optimized code generation.
We demonstrate the effectiveness of our work using cases studies, in which we implement Umple models using our new composite structure and concurrency constructs. We show that the amount of code required to specify complex concepts is reduced, and the generated systems are effective.
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Becker, Leandro Buss. "Ambiente de modelagem e implementação de sistemas tempo real usando o paradigma de orientação a objetos." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 1999. http://hdl.handle.net/10183/27108.
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Este trabalho descreve o desenvolvimento de um ambiente integrado para modelagem, simulação e implementação de sistemas de tempo real distribuídos (STRD), especialmente aqueles voltados para automação industrial. O ambiente proposto faz use do paradigma de orientação a objetos, sendo baseado no ambiente SIMOO, desenvolvido no Âmbito de uma tese de doutorado no CPGCC. A motivação para a realizado deste trabalho surgiu através de alguns estudos de caso, que constataram que as ferramentas CASE existentes não incorporavam todas as propriedades desejadas em termos de suporte para modelagem e implementação dos STRD. Dentre estas propriedades, destacam-se a capacidade para especificação de restrições temporais, o suporte a simulação do modelo desenvolvido e a capacidade de geração automática de código para a aplicação final. O ambiente proposto tem por objetivo suprir as carências observadas, adicionando ao ambiente SIMOO original facilidades para a descrição de restrições temporais e facilidades para descried° de comportamento do modelo desenvolvido. Além disso, é incorporada ao ambiente a capacidade de geração automática de código em uma linguagem que suporte as restrições temporais descritas no modelo. Este trabalho foi desenvolvido no contexto do projeto ADOORATA (A Distributed Object-Oriented Architecture for Real-Time Automation), como parte do Programa de Cooperação entre Brasil e Alemanha, financiado pelas agencias CNPq e DLR.This work describes the development of an integrated object-oriented environment for modeling, simulation and implementation of distributed real-time systems (DRTS), especially those conceived for industrial automation. This work extends the SIMOO environment, conceived as part of a Ph.D. thesis in the CPGCC at Federal University of Rio Grande do Sul. Its motivation began during some case studies, which concluded that existing CASE tools don't incorporate all the desired features for modeling and implementation of DRTS. Among these features, capacities to specify timing constraints, to simulate/animate the model and to automatically generate the final application code are highlighted. The proposed environment intends to overcome these lacks, adding to the original environment features for the specification of timing requirements and the application behavior, allowing the creation of an object-oriented simulation model. Additionally it automatically generates the application executable code, which makes use of the incorporated specifications to guarantee its correctness. This work has been developed within the context of the ADOORATA project (A Distributed Object-Oriented Architecture for Real-Time Automation), as part of the Brazilian-German Cooperation Program, sponsored by CNPq and DLR.
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Moreira, Tomás Garcia. "Geração automática de código VHDL a partir de modelos UML para sistemas embarcados de tempo-real." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2012. http://hdl.handle.net/10183/55444.
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A crescente demanda da indústria exige a produção de dispositivos embarcados em menos tempo e com mais funcionalidades diferentes. Isso implica diretamente no processo de desenvolvimento destes produtos requerendo novas técnicas para absorver a complexidade crescente dos projetos e para acelerar suas etapas de desenvolvimento. A linguagem UML vem sendo utilizada para absorver a complexidade do projeto de sistemas embarcados através de sua representação gráfica que torna o processo mais simples e intuitivo. Para acelerar o desenvolvimento surgiram processos que permitem, diretamente a partir modelos UML, a geração de código para linguagens de descrição de software embarcado (C, C++, Java) e para linguagens tradicionais de descrição de hardware (VHDL, Verilog). Diversos trabalhos e ferramentas comerciais foram desenvolvidos para automatizar o processo de geração de código convencional a partir de modelos UML (software). No entanto, pela complexidade da transformação existem apenas poucos trabalhos e nenhuma ferramenta comercial direcionado à geração de HDL a partir de UML, tornando este processo ainda pouco difundido. Nossa proposta é focada na geração de descrições de hardware na linguagem VHDL a partir de modelos UML de sistemas tempo-real embarcados (STRE), surgindo como alternativa ao processo de desenvolvimento de hardware. Apresenta uma metodologia completa para geração automática de código VHDL, permitindo que o comportamento descrito para o sistema modelado seja testado e validado antes de ser desenvolvido, acelerando o processo de produção de hardware e diminuindo as chances de erros de projeto. É proposto como um processo de engenharia dirigido por modelos (MDE) que cobre desde as fases de análise de requisitos e modelagem UML, até a geração de código fonte na linguagem VHDL, onde o foco é gerar na forma de descrições de hardware, todas aquelas funções lógicas de um sistema embarcado que normalmente são desenvolvidas em software. Para atingir este objetivo, foi desenvolvido neste trabalho um conjunto de regras de mapeamento que estende a funcionalidade da ferramenta GenERTiCA, utilizada como suporte ao processo. Adicionalmente, foram pesquisados e desenvolvidos conceitos que serviram como base para o desenvolvimento de regras utilizadas pela ferramenta suporte para guiar o processo de mapeamento entre as linguagens. Os conceitos e as regras propostas foram validados por meio de um estudo de caso, cujos resultados obtidos estão demonstrados nesta dissertação.The growing market demand requires the production of embedded devices in less time and with more different features. This directly implies on the development process of these products requiring new techniques to absorb the growing complexity of projects and to accelerate their development stages. UML has been used to handle the embedded systems design complexity through its graphical representation that makes the process simpler and more intuitive. To speed up the development cycle, it has emerged some processes that permit code generating directly from UML models to embedded software description languages (C, C++, Java), and traditional hardware description languages (VHDL, Verilog). Several researches and commercial tools have been developed to automate the code generation process from UML models to conventional languages (software). However, due to the transformation complexity there are only few studies and no commercial tool addressed to HDL generation from UML models, making this process almost unknown. Our proposal is focused on generating hardware descriptions as VHDL code from UML models of real-time embedded systems (RTES), emerging as an alternative to the hardware development. It presents a complete methodology to the VHDL code generation, allowing the behavior described to the modeled system to be tested and validated before being implemented, accelerating the hardware production and decreasing the chances of design errors. It is proposed as a model-driven engineering (MDE) process that covers the phases of requirements analysis, UML modeling, models transformations, and the source code generating process to the VHDL language, where the focus is to generate as hardware descriptions all the logic functions of an embedded system which are usually developed as software. To achieve this goal, this work was developed a set of mapping rules which extends the functionality of the tool GenERTiCA, used to support the process. Additionally, it was researched and developed concepts that were the basis for the development of rules used by the tool support to guide the mapping process between languages. The concepts and proposed rules have been validated through a case study, whose results are shown in this dissertation.
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Lu, Yujie Irene. "Real-time digital simulation of the generator model." Thesis, Virginia Tech, 1990. http://hdl.handle.net/10919/42061.
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This thesis is in an attempt to realistically model a real-time digital generator which interfaces to an analog system simulator and which consists of the synchronous machine and its peripheral controllers such as the exciter and the governor-turbine subsystems. In this work, the exciter, the synchronous machine, the machine dynamics and the governor are modeled in detail while a simplified model of the turbine is used.
The synchronous machine, the main component of this simulation, solves the discretized Park's machine equations which include flux derivative tenns and tenns pertaining to the two amortisseur windings. Treatment of saturation effects in the mutual inductances is also discussed. The Park's model is arranged to obtain a field voltage and machine armature cutTent input - machine tenninal voltage output structure, where the armature current and terminal voltage are rotor based quantities (i.e. in d-q domain). In order to interface the Park's machine model to the analog system model, the Park's and inverse Park's transfonnation are implemented by software modules.
The implementation of a prototype model generator using a Motorola 68020 microprocessor and fast computer peripherals is discussed. The results of the digital computer simulation in real-time for the generator model under various operating conditions are presented.
Master of Science
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Zarif, Mansour Sepehr. "A real time and time optimal trajectory generator for Cartesian machine tools." Thesis, University of British Columbia, 2015. http://hdl.handle.net/2429/53939.
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This work focuses on control and trajectory optimization strategies for high speed contouring of machine tools. In the first part, control strategies are studied. Studied strategies are divided into three major categories. Axial error controllers, contour error controllers, and feed forward controllers. The control strategies are benchmarked on a biaxial XY table. The least contouring error was recorded for the control structure consisting of Cartesian Servo Control (CSC) with a Proportional Derivative Integral (PID) regulator + Torque Feed Forward (TFF). As for the trajectory optimization, a new real time algorithm to select time-optimal feedrates has been proposed. The algorithm is independent of the spline representation of the nominal path, and incorporates both velocity and acceleration constraints. The fact that the proposed algorithm is independent from the spline representation (since it simply adjusts sampling times for position increments), makes it more flexible than conventional algorithms in the literature that require particular spline representations of the reference trajectory. Also the proposed algorithm is computationally efficient because: 1) an analytical solution to the optimization is applied at every time step rather than a global numerical optimization procedure, and 2) other analytical solutions in the literature require a forward and a backward pass over the compete trajectory. The new algorithm only backtracks over a short window before decelerations. Finally, this study also introduces two new reference path generation techniques that use part tolerance values to reduce machining time.Applied Science, Faculty of
Engineering, School of (Okanagan)
Graduate
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Wang, Fukang. "Real time instruction generator for the Bolton urban drainage control system." Thesis, University of Salford, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.245021.
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De, Wulf Martin. "From timed models to timed implementations." Doctoral thesis, Universite Libre de Bruxelles, 2006. http://hdl.handle.net/2013/ULB-DIPOT:oai:dipot.ulb.ac.be:2013/210797.
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Computer Science is currently facing a grand challenge :finding good design practices for embedded systems. Embedded systems are essentially computers interacting with some physical process. You could find one in a braking systems or in a nuclear power plant for example. They present several design difficulties :first they are reactive systems, interacting indefinitely with their environment. Second,they must satisfy real-time constraints specifying when they should respond, and not only how. Finally, their environment is often deeply continuous, presenting complex dynamics. The formal models of choice for specifying such systems are timed and hybrid automata for which model checking is pretty well studied.
In a first part of this thesis, we study a complete design approach, including verification and code generation, for timed automata. We have to define a new semantics for timed automata, the AASAP semantics, that preserves the decidability properties for model checking and at the same time is implementable. Our notion of implementability is completely novel, and relies on the simulation of a semantics that is obviously implementable on a real platform. We wrote tools for the analysis and code generation and exemplify them on a case study about the well known Philips Audio Control Protocol.
In a second part of this thesis, we study the problem of controller synthesis for an environment specified as a hybrid automaton. We give a new solution for discrete controllers having only an imperfect information about the state of the system. In the process, we defined a new algorithm, based on the monotonicity of the controllable predecessors operator, for efficiently finding a controller and we show some promising applications on a classical problem :the universality test for finite automata.
Doctorat en sciences, Spécialisation Informatique
info:eu-repo/semantics/nonPublished
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Dubasi, Mohana Asha Latha. "Timed Refinement for Verification of Real-Time Object Code Programs." Diss., North Dakota State University, 2018. https://hdl.handle.net/10365/31372.
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Real-time systems such as medical devices, surgical robots, and microprocessors are safety-critical
applications that have hard timing constraint. The correctness of real-time systems is
important as the failure may result in severe consequences such as loss of money, time and human
life. These real-time systems have software to control their behavior. Typically, this software
has source code which is converted to object code and then executed in safety-critical embedded
devices. Therefore, it is important to ensure that both source code and object code are error-free.
When dealing with safety-critical systems, formal verification techniques have laid the foundation
for ensuring software correctness.
Refinement based technique in formal verification can be used for the verification of real-time
interrupt-driven object code. This dissertation presents an automated tool that verifies the
functional and timing correctness of real-time interrupt-driven object code programs. The tool has
been developed in three stages. In the first stage, a novel timed refinement procedure that checks
for timing properties has been developed and applied on six case studies. The required model
and an abstraction technique were generated manually. The results indicate that the proposed
abstraction technique reduces the size of the implementation model by at least four orders of
magnitude. In the second stage, the proposed abstraction technique has been automated. This
technique has been applied to thirty different case studies. The results indicate that the automated
abstraction technique can easily reduce the model size, which would in turn significantly reduce
the verification time. In the final stage, two new automated algorithms are proposed which would
check the functional properties through safety and liveness. These algorithms were applied to the
same thirty case studies. The results indicate that the functional verification can be performed in
less than a second for the reduced model.
The benefits of automating the verification process for real-time interrupt-driven object code
include: 1) the overall size of the implementation model has reduced significantly; 2) the verification
is within a reasonable time; 3) can be applied multiple times in the system development process.Several parts of this dissertation were funded by a grant from the United States Government and the generous support of the American people through the United States Department of State and the United States Agency for International Development (USAID) under the Pakistan – U.S. Science & Technology Cooperation Program. The contents do not necessarily reflect the views of the United States Government.
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Ng, Sunny, Mei Y. Wei, Austin Somes, Mich Aoyagi, and Joe Leung. "REAL-TIME DATA SERVER-CLIENT SYSTEM FOR THE NEAR REAL-TIME RESEARCH ANALYSIS OF ENSEMBLE DATA." International Foundation for Telemetering, 1998. http://hdl.handle.net/10150/609671.
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International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, CaliforniaThis paper describes a distributed network client-server system developed for researchers to perform real-time or near-real-time analyses on ensembles of telemetry data previously done in post-flight. The client-server software approach provides extensible computing and real-time access to data at multiple remote client sites. Researchers at remote sites can share similar information as those at the test site. The system has been used successfully in numerous commercial, academic and NASA wide aircraft flight testing.
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Srinivasa, Murthy Dilip. "REAL-TIME HILBERT TRANSFORM AND AUTOCORRELATION FOR DIGITAL WIDEBAND COMMUNICATION APPLICATIONS." Wright State University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=wright1227202325.
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Schäfer, Pierre-Alain. "Dynamic loading and linking native code on a real-time operating system." Instituto Tecnológico de Aeronáutica, 2007. http://www.bd.bibl.ita.br/tde_busca/arquivo.php?codArquivo=473.
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This thesis presents a very efficient and simple approach to native code generation and dynamic code loading for the RTOS RTEMS on the Blackfin architecture. The whole solution is intended for PLCs implementing the IEC 61131-3 standard. The second part of the solution, native code loading on RTEMS, is also usable for code updates in satellite applications. For the code generation modern parser generator tools have been used to implement a language translator from Instruction List to C language. The generated C language is then feed to the freely distributable GCC compiler which generates efficient native code. This native code is later on loaded and executed on a Blackfin CPU. The execution environment RTEMS has been ported to the Blackfin architecture. RTEMS is a hard real-time operating system which has been widely used in space applications. For the dynamic loading and linking of the native code 2 different loaders have been evaluated and compared. Those loaders are of special interest for satellite applications because they allow for much faster software update over slow communication links. The final systems achieves a speedup of approximately 4 compared to a traditional interpreted IEC 61131-3 system.
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Luppold, Arno [Verfasser]. "Schedulability-oriented code optimization of hard real-time multitasking systems / Arno Luppold." Hamburg : Universitätsbibliothek der Technischen Universität Hamburg-Harburg, 2020. http://d-nb.info/1213804000/34.
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Munukuntla, Sowmya. "Sensitivity Analysis of Synchronous Generators for Real-Time Simulation." ScholarWorks@UNO, 2016. http://scholarworks.uno.edu/td/2172.
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The purpose of this thesis is to validate generator models for dynamic studies of power systems using PSS/E (Power System Simulator for Engineering), EMTP (ElectroMagnetic Transient Program), and Hypersim. To thoroughly evaluate the behavior of a power system in the three specified software packages, it is necessary to have an accurate model for the power system, especially the generator which is of interest. The effect of generator modeling on system response under normal conditions and under faulted conditions is investigated in this work. A methodology based on sensitivity analysis of generator model parameters is proposed aiming to homogenize the behavior of the same power system that is modeled in three software packages. Standard IEEE 14-Bus system is used as a test case for this investigation. Necessary changes in the exciter parameters are made using the proposed methodology so that the system behaves identical across all three software platforms.
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Treadwell, Steven B. (Steven Brett). "Estimating task execution delay in a real-time system via static source code analysis." Thesis, Massachusetts Institute of Technology, 1993. http://hdl.handle.net/1721.1/46427.
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Lowe, Darryn W. "Real-time FPGA realization of an UWB transceiver physical layer." Access electronically, 2005. http://www.library.uow.edu.au/adt-NWU/public/adt-NWU20060726.161825/index.html.
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Lundström, Adam. "Finding strategies for executing Ada-code in real-time on Linux using an embedded computer." Thesis, KTH, Maskinkonstruktion (Inst.), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-187735.
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A combination of Ada, real-time Linux and an embedded computer is a costeective solution that accommodates most of the demands of embedded systemsdevelopment or prototyping. Linux in its standard conguration is not suitablefor real-time applications, but there exists solutions that modies it to be morereal-time capable. The question is, what modication is the optimal one froman Ada perspective? To answer this, a literature study has been conducted toidentify solutions, followed by an analysis that gures out the most promisingone. The selected solution has then been further evaluated and veried by benchmarksand tests running on a BeagleBone Black.The evaluation results shows that the PREEMPT_RT real-time patches for Linuxis the optimal solution for enabling real-time execution of Ada code. Two otherpromising solutions were Xenomai and RTAI, they provide better performancein terms of lower latencies but does not have full Ada support and requires codeto be specically targeted to their solutions compared to PREEMPT_RT that istransparent to the user.The worst case latencies for PREEMPT_RT were measured with Cyclictest whilethe system was stressed by using Sysbench, Hackbench and ping ooding. Thetests stressed dierent part of the system, e.g CPU, memory and le IO, making itpossible to determine howsensitive the latencies are to dierent types of applications.Two of the tests stood out from the others, the ping ood and the SysbenchThread-test. When pinging the system the worst case latencies were 364 µs, inthe order of three times higher than the other loads. The other deviating resultwas observed when the system was loaded using the Sysbench Thread-test, thelatencies were actually lower compared to the unloaded system, 62 µs versus 90µs. The reason for this is dicult to determine due to the size and complexity ofLinux, it would require a deeper analysis of the kernel code.PREEMPT_RT allows existing applications for Linux to run without modicationto the source code which makes it attractive for developing mixed type systemsthat require real-time predictability, general purpose exibility and highthroughput. It is a cost-eective solution that could be used for teaching Adaand making prototypes that don’t require the highest levels of safety certication.The latencies are not low enough to accommodate the demands of all systems,but many systems require latencies only to be in the order of milliseconds,which this solution would be suitable for.En kombination av Ada, realtids-Linux och en enkortsdator är en kostnadseektivlösning som möter de esta av behoven för utveckling och prototypframtagninginom inbyggda system. Linux är i sin standardkonguration inte lämpligför realtidsapplikationer, men det nns lösningar som gör Linux mer realtids anpassat.Frågan är, vilken lösning är den optimala från ett Ada perspektiv? För attsvara på detta har en litteraturstudie utförts för att identiera olika lösningar,följt av en analys som tar fram den mest lovande. Den utvalda lösningen har sedanutvärderats och verierats genom tester som körts på en BeagleBone Black.Utvärderingen visar att lösningen PREEMPT_RT för Linux är den optimala förrealtids-exekvering av kod skriven i Ada. Två andra lovande lösningar är Xenomaioch RTAI, de uppvisar bättre prestanda genom kortare fördröjningar. Mende har inte fullt stöd för Ada och kräver att kod anpassas för deras lösning tillskillnad från PREEMPT_RT som är transparent för användaren.Fördröjningarna för PREEMP_RT mättes upp med Cyclictest samtidigt som systemetbelastades av Sysbench, Hackbench och ’ping ooding’. Testerna belastadeolika delar av systemet, till exempel CPUn, minnet och l-IO, vilket gör detmöjligt att bestämma hur känsligt systemet är för olika typer av applikationer.Två test särskilde sig från de andra, ’ping ooding’ och Sysbench Thread-test.När systemet pingades mättes fördröjningarna upp till 364 µs, i storleksordningentre gånger högre jämfört med de andra testerna. Det andra utmärkande testetvar när Sysbench Thread-testet kördes, fördröjningarna var oväntat nog mindrejämfört med det obelastade systemet, 62 µs respektive 90 µs. Anledningen till detär svårt att avgöra på grund av storleken och komplexiteten av Linux, det skullekräva en djupare analys av Linux-kärnan.PREEMPT_RT tillåter att bentliga applikation för Linux att köras utan förändringarav källkoden vilket gör lösning attraktiv för utveckling av system somkräver realtidsegenskaper, exibilitet och hög prestanda. Det är en kostnadseffektivlösning som kan användas för utbilding i Ada och utveckling av prototypersom inte kräver högsta nivån av säkerhetscertiering. Fördröjningarna är intetillräckligt låga för att kunna möta kraven för alla system, men ofta är kraven istorleksordningen av millisekunder, vilket den här lösningen skulle vara lämpligför.
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Tomasi, Daniele. "Function Point e Real Time Software: caso di studio reale." Bachelor's thesis, Alma Mater Studiorum - Università di Bologna, 2014. http://amslaurea.unibo.it/7816/.
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La tesi si pone come obiettivo quello di analizzare dal punto di vista funzionale il software embedded real - time installato su di una applicazione industriale, utilizzando la prima release per calibrare il sistema in modo da poter stimare il numero di linee di codice necessarie per lo sviluppo delle versioni successive.
Durante questo studio sono stati applicati i metodi indicati dall'ingegneria del software per contare le linee di codice sorgente dell'applicativo e stimarne i function point, analizzando ed individuando le problematiche relative all'utilizzo di tali strumenti su software di tipo real - time.
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Ashglaf, Mohmed Omran. "Development of Hybridization concept for horizontal axis wind / tidal systems using functional similarities and advanced real-time emulation methods." Thesis, Normandie, 2019. http://www.theses.fr/2019NORMLH07/document.
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La capacité des systèmes conventionnels de production d'énergie éolienne et marémotrice à fournir au réseau une énergie fiable et stable à tout moment est un nouveau défi en raison des fluctuations météorologiques, qui ont un impact significatif et direct sur la production d'énergie. C'est pourquoi l'hybridation des systèmes de production d'énergie éolienne et hydrolienne ont été étudiées pour améliorer l'intégration des énergies éolienne et marémotrice sur le réseau électrique.Cette étude nous a amené à développer des contributions liées à deux axes principaux :Le premier axe est focalisé sur un nouveau concept d'hybridation de deux sources énergétiques différentes en termes de propriétés physiques, l’éolien et l’hydrolienne à axe horizontal, basé sur un couplage électromécanique de ces deux systèmes. Les deux ressources sont l’énergie éolienne et l’énergie des courants marins. Le concept est développé en utilisant les similitudes fonctionnelles des turbines et les similarités en conversion d’énergie de leurs chaînes énergétiques. Pour appliquer ce concept en premier lieu, les paramètres de la génératrice asynchrone à double alimentation installée dans l’émulateur du GREAH sont identifiés. Ensuite, la chaîne de conversion de puissance est modélisée mathématiquement et simulée dans un environnement MATLAB / SIMULINK. Nous avons développé deux stratégies de commande.Une stratégie à vitesse fixe appelé "Contrôle direct de la vitesse", et une stratégie à vitesse variable basée sur la recherche de puissance maximale, dénommée "Contrôle indirecte de vitesse". Enfin, ce concept a été implémenté pratiquement sur l’émulateur en temps réel du laboratoire. Les résultats obtenus ont été analysés et discutés suite à ces travaux.Le deuxième axe est consacré à un concept que l’on appelle «temps accélérée» de simulation ou « temps virtuel ». Par la suite, ce concept a été mis en œuvre sur l’émulateur multi physique disponible au laboratoire GREAH. Ce concept (temps accélérée) est basé sur la réduction des échantillons de profil de vent afin de diminuer le temps de simulation et faciliter la commande en temps réel.Les résultats principaux sont obtenus d’abord dans MATLAB / SIMULINK, puis ont été vérifiés sur l’émulateur en temps réel. L’objectif principal de cette thèse est d’étudier le concept d’hybridation éolienne offshore / éolienne basée sur la flexibilité d’un émulateur multifonctions permettant diverses architectures d’émulation : éoliennes, éoliennes, et systèmes hybrides éoliennes - éoliennes. Nous analysons son impact sur la puissance de sortie du système. Les résultats obtenus sont corrélés aux profils de vitesse du vent et des marées, dans lesquels les propriétés statistiques ayant un impact sur les chaînes énergétiques mondiales pourraient être complémentaires et en particulier en fonction des sites donnés.Contributions principales et perspectives- Développement du concept de couplage électromécanique. Lorsque deux sources d’énergie renouvelables sont « intégrées », on stabilise la fluctuation rapide de la puissance générée, mais sous certaines conditions telles que la présence d’unités de stockage ou d’un système d’embrayage automatique.- Le concept temps accéléréeCette méthode est utilisée pour réduire la taille des données enregistrées du vent ou des courant marins, afin d’accélérer le temps de simulation des unités de production d'énergie avec des résultats raisonnables qui se rapprochent pertinemment des situations réelles.- Etudier et développer le concept de régime d’arbre électrique :Si le couplage électromécanique est difficile à réaliser du point de vue mécanique et que les découplages à arbre unique sont trop fréquents et que les contraintes mécaniques sont élevées, on peut étudier le régime de l'arbre électrique avec deux machines à induction DFIG. Le système peut fonctionner en mode synchrone avec des structures et configurations spécifiquesThe ability of conventional wind and tidal generation systems to provide the grid with reliable and stable power at all times is a new challenge due to weather fluctuations, which have a significant and direct impact on energy production. This is why the hybridization of wind and tidal power generation systems has been studied to improve the integration of wind and tidal power into the electricity grid.This study led us to develop contributions related to two main axes:The first axis is focused on a new concept of hybridization of two different energy sources in terms of physical properties, wind and horizontal axis turbines, based on an electromechanical coupling of these two systems. The two resources are wind energy and marine energy. The concept is developed using the functional similarities of turbines and similarities in energy conversion of their energy chains. To apply this concept first, the parameters of the double fed asynchronous generator installed in the GREAH emulator are identified. Then, the power conversion chain is modeled mathematically and simulated in a MATLAB / SIMULINK environment. We have developed two control strategies.A fixed speed strategy called "Direct Speed Control", and a variable speed strategy based on the search for maximum power, called "Indirect Speed Control". Finally, this concept has been implemented practically on the real-time emulator of the laboratory. The results obtained were analyzed and discussed following this work.The second axis is devoted to a concept called "accelerated time" simulation or "virtual time". Subsequently, this concept was implemented on the multi-physics emulator available at the GREAH laboratory. This concept (accelerated time) is based on reducing wind profile samples in order to decrease simulation time and facilitate real-time control.The main results are obtained first in MATLAB / SIMULINK, then verified on the emulator in real time.The main objective of this thesis is to study the concept of offshore wind / tidal turbine hybridization based on the flexibility of a multi-function emulator that allows various emulation architectures: wind turbines, tidal turbines, and hybrid wind - tidal turbines systems. We analyze its impact on the output power of the system; the obtained results are correlated with wind and tidal speed profiles, in which statistical properties impacting global power chains could be complementary and in particular in function of the given sites. Main contributions and perspectives- Development of the concept of electromechanical coupling.When two renewable energy sources are "integrated", the rapid fluctuation of the power generated is stabilized, but under certain conditions such as the presence of storage units or an automatic clutch system.- The accelerated time conceptThis method is used to reduce the size of the recorded wind or sea current data, to speed up the simulation time of the power generation units with reasonable results that are close to actual situations.- Study and develop the concept of electric shaft regime: If the electromechanical coupling is difficult to achieve from the mechanical point of view and the single shaft decouples are too frequent so high mechanical stress, one can study the electric shaft regime with two DFIG induction machines.There is a regime in which the ratios between the speeds of the different machines are rigorously constant. The system can operate in synchronous mode with specific structures and configurations
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Berdugo, Albert, and William G. Ricker. "A NEW 1553 ALL-BUS INSTRUMENTATION MONITOR." International Foundation for Telemetering, 1990. http://hdl.handle.net/10150/613782.
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International Telemetering Conference Proceedings / October 29-November 02, 1990 / Riviera Hotel and Convention Center, Las Vegas, NevadaIncreased data throughput demands in military and avionics systems has led to the development of an advanced, All-Bus MIL-STD-1553 Instrumentation Monitor. This paper discusses an airborne unit which acquires the information from up to 8 dual-redundant buses, and formats the data for telemetry, recording or real-time analysis according to the requirements of IRIG-106-86, Chapter 8. The ALBUS-1553 acquires all or selected 1553 messages which are formatted into IRIG-compatible serial data stream outputs. Data is time tagged to microsecond resolution. The unit selectively transmits entire or partial 1553 messages under program control. This results in reduced transmission bandwidth if prior knowledge of 1553 traffic is known. The ALBUS also encodes analog voice inputs, discrete userword inputs and multiplexed analog (overhead) inputs. The unit is provided in a ruggedized airborne housing utilizing standard ATR packaging,
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Billings, Don, Mei Wei, Joseph Leung, Michio Aoyagi, Fred Shigemoto, and Rob Honeyman. "REAL-TIME INTEGRATION OF RADAR INFORMATION, AND GROUND AND RADIOSONDE METEOROLOGY WITH FLIGHT RESEARCH DATA." International Foundation for Telemetering, 1998. http://hdl.handle.net/10150/607368.
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International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, CaliforniaAlthough PCM/TDM framed data is one of the most prevalent formats handled by flight test ranges, it is often required to acquire and process other types. Examples of such non-standard data types are radar position information and meteorological data from both ground based and radiosonde systems. To facilitate the process and management of such non-standard data types, a micro-processor based system was developed to acquire and transform them into a standard PCM/TDM data frame. This obviated the expense of developing additional special software and hardware to handle such non-standard data types.
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Wang, Ge. "Doubly fed induction generator (DFIG)-based wind power generation system simulation using real-time digital simulator (RTDS) a thesis presented to the faculty of the Graduate School, Tennessee Technological University /." Click to access online, 2009. http://proquest.umi.com/pqdweb?index=0&did=2000377761&SrchMode=1&sid=4&Fmt=6&VInst=PROD&VType=PQD&RQT=309&VName=PQD&TS=1277818196&clientId=28564.
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Björnhager, Jens. "CRL2ALF : En översättare från PowerPC till ALF." Thesis, Mälardalens högskola, Akademin för innovation, design och teknik, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-13373.
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Realtidssystem ställer hårda krav på dess ingående mjukvaras temporala beteende. Programmen måste bete sig deterministiskt och ge svar inom satta tidsgränser. Med hårda krav följer större behov av verktyg att testa koden med. WCET (Worst Case Execution Time)-analys har som mål att finna en övre gräns för ett programs exekveringstid. SWEET (SWEdish Execution Time) är ett verktyg för WCET-analys utvecklat av en forskargrupp vid Mälardalens Högskola. PowerPC är en klassisk processorarkitektur som utvecklades av Apple, Motorola och IBM och släpptes 1991. Den har bland annat använts av Apple i äldre versioner av deras Macintosh-datorer och i TV-spelskonsoler såsom Nintendo GameCube och är stor inom inbyggda system. Tidigare har endast analys av källkod, C, varit möjlig i SWEET. Målet för detta examensarbete var att möjliggöra analys av körbara program för vilka källkoden ej är tillgänglig, Detta gjordes genom att konstruera en översättare från PowerPC-binärer till det programformat som SWEET använder för sina statiska analyser, ALF, med hjälp av tredjepartsverktyget aiT från AbsInt GmbH. Resultatet blev en med undantag för flyttalsinstruktioner komplett översättare av PowerPC-program till ALF-kod. De flesta genererade programfiler som har testats i SWEET har gett lyckat resultat.Real-time systems put tough timing requirements on the software running on them. The programs must behave deterministically and respond within set time limits. With these demands comes a higher demand on verification tools. The goal of a WCET (Worst Case Execution Time) analysis is to derive the upper bound of a program's execution time. SWEET (SWEdish Execution Time) is a tool for WCET analysis developed by a research group at Mälardalen University. PowerPC is a classic processor architecture that was developed by Apple, Motorola and IBM and was released in 1991. It has been used in older versions of Apple's Macintosh computers and in video game consoles such as the GameCube from Nintendo, and is a popular choice for embedded solutions. Previously you could only do analyses on code generated from C in SWEET. The goal of this MSC thesis was to construct a converter from PowerPC binaries to the program format that SWEET uses for its analyses, ALF, with the help of the third-party tool aiT from AbsInt GmbH. The result is a - with the exception of floating-point instructions - complete converter from PowerPC programs to ALF. Most of the generated program files have been tested within SWEET with successful results.
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Elloumi, Yaroub. "Parallélisme des nids de boucles pour l’optimisation du temps d’exécution et de la taille du code." Thesis, Paris Est, 2013. http://www.theses.fr/2013PEST1199/document.
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Les algorithmes des systèmes temps réels incluent de plus en plus de nids de boucles, qui sont caractérisés par un temps d’exécution important. De ce fait, plusieurs démarches de parallélisme des boucles imbriquées ont été proposées dans l’objectif de réduire leurs temps d’exécution. Ces démarches peuvent être classifiées selon deux niveaux de granularité : le parallélisme au niveau des itérations et le parallélisme au niveau des instructions. Dans le cas du deuxième niveau de granularité, les techniques visent à atteindre un parallélisme total des instructions appartenant à une même itération. Cependant, le parallélisme est contraint par les dépendances des données inter-itérations ce qui implique le décalage des instructions à travers les boucles imbriquées, provocant ainsi une augmentation du code proportionnelle au niveau du parallélisme. Par conséquent, le parallélisme total au niveau des instructions des nids de boucles engendre des implémentations avec des temps d’exécution non-optimaux et des tailles du code importantes. Les travaux de cette thèse s’intéressent à l’amélioration des stratégies de parallélisme des nids de boucles. Une première contribution consiste à proposer une nouvelle technique de parallélisme au niveau des instructions baptisée « retiming multidimensionnel décalé ». Elle vise à ordonnancer les nids de boucles avec une période de cycle minimale, sans atteindre un parallélisme total. Une deuxième contribution consiste à mettre en pratique notre technique dans le contexte de l’implémentation temps réel embarquée des nids de boucles. L’objectif est de respecter la contrainte du temps d’exécution tout en utilisant un code de taille minimale. Dans ce contexte, nous avons proposé une première démarche d’optimisation qui consiste à utiliser notre technique pour déterminer le niveau parallélisme minimal. Par la suite, nous avons décrit une deuxième démarche permettant de combiner les parallélismes au niveau des instructions et au niveau des itérations, en utilisant notre technique et le « loop striping »The real time implementation algorithms always include nested loops which require important execution times. Thus, several nested loop parallelism techniques have been proposed with the aim of decreasing their execution times. These techniques can be classified in terms of granularity, which are the iteration level parallelism and the instruction level parallelism. In the case of the instruction level parallelism, the techniques aim to achieve a full parallelism. However, the loop carried dependencies implies shifting instructions in both side of nested loops. Consequently, these techniques provide implementations with non-optimal execution times and important code sizes, which represent limiting factors when implemented on embedded real-time systems. In this work, we are interested on enhancing the parallelism strategies of nested loops. The first contribution consists of purposing a novel instruction level parallelism technique, called “delayed multidimensional retiming”. It aims to scheduling the nested loops with the minimal cycle period, without achieving a full parallelism. The second contribution consists of employing the “delayed multidimensional retiming” when providing nested loop implementations on real time embedded systems. The aim is to respect an execution time constraint while using minimal code size. In this context, we proposed a first approach that selects the minimal instruction parallelism level allowing the execution time constraint respect. The second approach employs both instruction level parallelism and iteration level parallelism, by using the “delayed multidimensional retiming” and the “loop striping”
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Eccles, Lee, Michael O’Brien, and William Anderson. "DATA ACQUISITION SYSTEM FOR AIRCRAFT QUALIFICATION." International Foundation for Telemetering, 1986. http://hdl.handle.net/10150/615566.
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International Telemetering Conference Proceedings / October 13-16, 1986 / Riviera Hotel, Las Vegas, NevadaThe Boeing Commercial Airplane Company presently uses an Airborne Data Analysis and Monitor System (ADAMS) to support extensive qualification testing on new and modified commercial aircraft. The ADAMS system consists of subsystems controlled by independent processors which preprocess serial PCM data, perform application-specific processing, provide graphic display of data, and manage mass storage resources. Setup and control information is passed between processors using the Ethernet protocol on a fiber optic network. Tagged data is passed between processors using a data bus with networking characteristics. During qualification tests, data are dynamically selected, analyses performed, and results recorded. Decisions to proceed or repeat tests are made in real time on the aircraft. Instrumentation in present aircraft includes up to 3700 sensors, with projections for 5750 sensors in the next generation. Concurrently, data throughput rates are increasing, and data preprocessing requirements are becoming more complex. Fairchild Weston Systems, Inc., under contract to Boeing, has developed an Acquisition Interface Assembly (AIA) which accepts multiple streams of PCM data, controls recording and playback on analog tape, performs high speed data preprocessing, and distributes the data to the other ADAMS subsystems. The AIA processes one to three streams in any of the standard IRIG PCM formats using programmable bit, frame and subframe synchronizers. Data from ARINC buses with embedded measurement labels, bus ID’s, and time tags may also be processed by the AIA. Preprocessing is accomplished by two high-performance Distributed Processing Units (DPU) operating in either pipeline or parallel environments. The DPU’s perform concatenation functions, number system conversions, engineering unit conversions, and data tagging for distribution to the ADAMS system. Time information, from either a time code generator or tape playback, may be merged with data with a 0.1 msec resolution. Control and status functions are coordinated by an embedded processor, and are accessible to other ADAMS processors via both the Ethernet interface and a local operator’s terminal. Because the AIA assembly is used in aircraft, the entire functional capability has been packaged in a 14-inch high, rack-mountable chassis with EMI shielding. The unit has been designed for high temperature, high altitude, vibrating environments. The AIA will be a key element in aircraft qualification testing at Boeing well into the next generation of airframes, and specification, design, development, and implementation of the AIA has been carried out with the significance of that fact in mind.
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Huang, Renke. "Seamless design of energy management systems." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/53518.
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The contributions of the research are (a) an infrastructure of data acquisition systems that provides the necessary information for an automated EMS system enabling autonomous distributed state estimation, model validation, simplified protection, and seamless integration of other EMS applications, (b) an object-oriented, interoperable, and unified component model that can be seamlessly integrated with a variety of applications of the EMS, (c) a distributed dynamic state estimator (DDSE) based on the proposed data acquisition system and the object-oriented, interoperable, and unified component model, (d) a physically-based synchronous machine model, which is expressed in terms of the actual self and mutual inductances of the synchronous machine windings as a function of rotor position, for the purpose of synchronous machine parameters identification, and (e) a robust and highly efficient algorithm for the optimal power flow (OPF) problem, one of the most important applications of the EMS, based on the validated states and models of the power system provided by the proposed DDSE.
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Bun, Long. "Détection et localisation de défauts pour un système PV." Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00647189.
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Comme tout processus industriel, un système photovoltaïque peut être soumis, au cours de son fonctionnement, à différents défauts et anomalies conduisant à une baisse de la performance du système et voire à son indisponibilité. Permettre de diagnostiquer finement et de faire de la détection et de localisation de défauts dans une installation PV réduit les coûts de maintenance et surtout augmente la productivité. Dans ce travail de thèse, nous nous intéressons spécifiquement à la détection et la localisation de défauts côté DC du système PV, c'est-à-dire du côté générateur PV. L'objectif de cette thèse est de proposer, en prenant le moins de mesures possibles pour respecter les contraintes économiques, un algorithme pour détecter et localiser des défauts conduisant à une baisse de production. Pour cela, le choix s'est porté sur l'analyse de la caractéristique I-V du générateur PV pour les différents modes de fonctionnement considérés. Cette analyse a conduit à utiliser la méthode d'inférence pour effectuer le diagnostic de l'installation. Cette démarche a été validée par des expérimentations sur site, des simulations temps-réel et hors temps-réel.
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Meléndez, i. Catalán Adrià. "Development of a New Parallel Code for 3-D Joint Refraction and Reflection Travel-Time Tomography of Wide-Angle Seismic Data. Synthetic and Real Data Applications to the Study of Subduction Zones." Doctoral thesis, Universitat de Barcelona, 2014. http://hdl.handle.net/10803/289786.
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This dissertation is devoted to seismic tomography. I have implemented a new modelling tool for 3-D joint refraction and reflection travel-time tomography of wide-angle seismic data (TOMO3D). The reason behind this central objective is the evidence that the information based on 2-D seismic data does not allow to capture the structural complexity of many 3-D targets, and in particular that of the seismogenic zone in subduction margins. The scientific rationale for this statement, which justifies the central part of my thesis work, is based on the analysis of 2-D models obtained in the convergent margin of Nicaragua, a seismically active area where a textbook example of tsunami earthquake took place in 1992. In this application I modelled two perpendicular wide-angle seismic profiles for the characterisation of the overriding plate and the interplate fault. To do this, I applied TOMO2D, a state-of-the-art joint refraction and reflection 2-D travel-time tomography code. The inversion outcomes are two 2-D velocity models along both profiles, together with the 1-D geometry of the interplate boundary. In combination with other geophysical data measurements, namely coincident multichannel seismic profiles and gravity data, these models provide new constraints on the nature and structure of the margin, and in particular add new insights on the nucleation and propagation of the said earthquake and its tsunamigenic behaviour. Ultimately, this case study evidences the aforementioned limitations of 2-D modelling in the investigation of 3-D geological structures and phenomena. Following from this first application and with the idea of increasing the amount of data used in travel-time tomography, I focused on an a priori paradoxical phenomenon related to water-layer multiple phases, that under certain circumstances, is observed on wide-angle record sections. The interest of this study lies in the fact that this phenomenon can provide additional constraints on travel-time tomography models. First, I propose and corroborate the hypothesis explaining the apparent paradox, and then derive the most favourable geological conditions for the phenomenon to occur. Subsequently, the possibility to model this multiple-like phases is introduced in TOMO3D.
The development of TOMO3D, which constitutes the core of my work, is founded on TOMO2D, from which it inherits the numerical methods for solving the forward and inverse problems. Source files have been rewritten, redefining and introducing the necessary variables and functions to handle 3-D data inversion. The tests made with the sequential version of the code emphasise the need of parallelisation for practicality reasons. Indeed, the increasing size of data sets along with the modelling of the additional spatial dimension results in computationally demanding inversions. Hence, I parallelised the forward modelling part of the code, which takes up to 90% of the computing time, with a combination of multiprocessing and message-passing interface extensions. Subsequently, the parallel version of TOMO3D is applied to a complex synthetic case simulating a subduction zone. This first 3-D application serves to evaluate the correctness of the code's programming, and as step-by-step description of the modelling procedure, with particular attention on the layer-stripping strategy used to successively model several reflectors. The outcomes demonstrate the ability of the code and the chosen inversion strategy to accurately recover the velocity distribution and the geometry of the two reflectors. Finally, TOMO3D is applied to a real 3-D wide-angle seismic data set acquired at the Pacific margin of Ecuador and Colombia to extract a 3-D velocity model of the overriding and incoming plates, which is then compared to previous results obtained with an extensively tested and used 3-D refraction travel-time tomography code (FAST). The comparison indicates that TOMO3D is more accurate than FAST but at the same time it is computationally more demanding. However, the parallelisation of TOMO3D allows using high-performance computing facilities, which is not the case of FAST or most of the existing codes.Aquesta tesi està dedicada a la tomografia sísmica. Concretament, he implementat una eina de modelització 3D per a la tomografia conjunta de temps de trajecte de refraccions i reflexions (TOMO3D). La raó darrere d'aquest objectiu és l'evidència de que la informació basada en dades sísmiques 2D no permet copsar la complexitat de gran part dels cossos geològics, i en particular de la zona sismogènica en marges de subducció. El desenvolupament del TOMO3D es basa en el TOMO2D, un codi d'avantguarda per a la tomografia conjunta de refraccions i reflexions en 2D. Els arxius de codi han estat reescrits, redefinint i introduint les funcions necessàries per dur a terme la inversió 3D. Els testos fets amb la versió seqüencial del codi posen de manifest la necessitat de paral·lelització ja que l'increment de la mida dels conjunts de dades així com la modelització de la dimensió espacial afegida fan que les inversions siguin computacionalment exigents. La versió paral·lelitzada del TOMO3D ha sigut aplicada a un cas sintètic complex que simula una zona de subducció. Aquesta primera aplicació 3D serveix per avaluar la correcció de la programació del codi, i com a descripció pas a pas del procediment de modelització. Els resultats demostren la capacitat del codi per recuperar acuradament la distribució de velocitat i la geometria dels dos reflectors. Finalment, el TOMO3D és aplicat a un conjunt 3D de dades de sísmica de gran angle adquirit al marge pacífic d'Equador i Colòmbia per extreure'n un model 3D de la velocitat de les plaques cavalcant i subduïda, que és comparat amb el resultat obtingut amb un codi 3D de tomografia de temps de trajecte de refraccions (FAST). La comparació indica que el TOMO3D és més acurat que el FAST però al mateix temps és computacionalment més exigent. Tot i així, la paral·lelització del TOMO3D permet utilitzar plataformes de supercomputació, a diferència del que passa amb el FAST i la majoria de codis existents.
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Chatterton, Jacqueline Ruth. "An evaluation of the predictions of near bottom interaction forces and moments on unmanned undersea vehicles : validation, reduction, and implementation of the results of a computer code into a real-time simulation." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/37523.
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Kraft, Johan. "Enabling Timing Analysis of Complex Embedded Software Systems." Doctoral thesis, Mälardalens högskola, Akademin för innovation, design och teknik, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-9532.
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Cars, trains, trucks, telecom networks and industrial robots are examples of products relying on complex embedded software systems, running on embedded computers. Such systems may consist of millions of lines of program code developed by hundreds of engineers over many years, often decades. Over the long life-cycle of such systems, the main part of the product development costs is typically not the initial development, but the software maintenance, i.e., improvements and corrections of defects, over the years. Of the maintenance costs, a major cost is the verification of the system after changes has been applied, which often requires a huge amount of testing. However, today's techniques are not sufficient, as defects often are found post-release, by the customers. This area is therefore of high relevance for industry. Complex embedded systems often control machinery where timing is crucial for accuracy and safety. Such systems therefore have important requirements on timing, such as maximum response times. However, when maintaining complex embedded software systems, it is difficult to predict how changes may impact the system's run-time behavior and timing, e.g., response times.Analytical and formal methods for timing analysis exist, but are often hard to apply in practice on complex embedded systems, for several reasons. As a result, the industrial practice in deciding the suitability of a proposed change, with respect to its run-time impact, is to rely on the subjective judgment of experienced developers and architects. This is a risky and inefficient, trial-and-error approach, which may waste large amounts of person-hours on implementing unsuitable software designs, with potential timing- or performance problems. This can generally not be detected at all until late stages of testing, when the updated software system can be tested on system level, under realistic conditions. Even then, it is easy to miss such problems. If products are released containing software with latent timing errors, it may cause huge costs, such as car recalls, or even accidents. Even when such problems are found using testing, they necessitate design changes late in the development project, which cause delays and increases the costs. This thesis presents an approach for impact analysis with respect to run-time behavior such as timing and performance for complex embedded systems. The impact analysis is performed through optimizing simulation, where the simulation models are automatically generated from the system implementation. This approach allows for predicting the consequences of proposed designs, for new or modified features, by prototyping the change in the simulation model on a high level of abstraction, e.g., by increasing the execution time for a particular task. Thereby, designs leading to timing-, performance-, or resource usage problems can be identified early, before implementation, and a late redesigns are thereby avoided, which improves development efficiency and predictability, as well as software quality. The contributions presented in this thesis is within four areas related to simulation-based analysis of complex embedded systems: (1) simulation and simulation optimization techniques, (2) automated model extraction of simulation models from source code, (3) methods for validation of such simulation models and (4) run-time recording techniques for model extraction, impact analysis and model validation purposes. Several tools has been developed during this work, of which two are in commercialization in the spin-off company Percepio AB. Note that the Katana approach, in area (2), is subject for a recent patent application - patent pending.PROGRESS
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Tan, Mustafa Tumer. "Seismic Strengthening Of A Mid-rise Reinforced Concrete Frame Using Cfrps: An Application From Real Life." Master's thesis, METU, 2009. http://etd.lib.metu.edu.tr/upload/12610562/index.pdf.
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SEISMIC STRENGTHENING OF A
MID-RISE REINFORCED CONCRETE FRAME
USING CFRPs: AN APPLICATION FROM REAL LIFE
Tan, Mustafa Tümer M.S., Department Of Civil Engineering Supervisor: Prof. Dr. Gü
ney Ö
zcebe Co-Supervisor: Assoc. Prof. Dr. BariS Binici May 2009, 162 pages FRP retrofitting allows the utilization of brick infill walls as lateral load resisting elements. This practical retrofit scheme is a strong alternative to strengthen low to mid-rise deficient reinforced concrete (RC) structures in Turkey. The advantages of the FRP applications, to name a few, are the speed of construction and elimination of the need for building evacuation during construction. In this retrofit scheme, infill walls are adopted to the existing frame system by using FRP tension ties anchored the boundary frame using FRP dowels. Results of experiments have previously shown that FRP strengthened infill walls can enhance lateral load carrying capacity and reduce damage by limiting interstory drift deformations. In previous, analytical studies, a detailed mathematical model and a simplified version of the model for compression struts and tension ties was proposed and verified by comparing model estimations with test results. In this study, an existing 9-storey deficient RC building located in Antakya was chosen to design and apply a hybrid strengthening scheme with FRPs and reduced number of shear walls. Linear elastic analysis procedure was utilized (force based assessment technique) along with the rules of Mode Superposition Method for the reftrofit design. FRP retrofit scheme was employed using the simplified model and design was conducted such that life safety performance criterion is satisfied employing elastic spectrum with 10% probability of exceedance in 50 years according to the Turkish Earthquake Code 2007. Further analytical studies are performed by using Modal Pushover and Nonlinear Time-History Analyses. At the end of these nonlinear analyses, performance check is performed according to Turkish Earthquake Code 2007, using the strains resulting from the sum of yield and plastic rotations at demand in the critical sections. CFRP retrofitting works started at October 2008 and finished at December 2008 for the building mentioned in this study. Eccentric reinforced concrete shearwall installation is still being undertaken. All construction business is carried out without evacuation of the building occupants. This project is one of the first examples of its kind in Turkey. Keywords: CFRP, Carbon Fiber Reinforced Polymers, Masonry Infill Walls, Reinforced Concrete Infill Walls, Mid-Rise Deficient Structures, Turkish Earthquake Code 2007, Modal Pushover Analysis, Nonlinear Time History Analysis, Linear Elastic Building Assessment
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Velásquez, Omar Chayña Chayña. "Ajuste e ensaio de sistemas de proteção de geradores síncronos." Universidade de São Paulo, 2015. http://www.teses.usp.br/teses/disponiveis/3/3143/tde-13062016-090911/.
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Os sistemas de proteção dos elementos da rede elétrica desempenham um papel de fundamental importância na segurança e confiabilidade dos sistemas de potência. A não atuação ou a atuação incorreta dos relés de proteção durante uma falta localizada em um componente da rede pode transformar-se em um evento sistêmico de grandes proporções (blecaute). Esses eventos trazem riscos e elevados prejuízos econômicos à sociedade. A proteção dos geradores síncronos, apesar do alto custo e complexidade deste tipo de equipamento, não recebe a mesma atenção na literatura que a dedicada à proteção de outros elementos da rede, como, por exemplo, a das linhas de transmissão. Isso decorre do menor número de geradores existentes na rede e também da ideia que as faltas neste tipo de equipamento são menos frequentes. Este trabalho aborda os principais aspectos envolvidos com o projeto de um sistema de proteção para geradores síncronos de grande porte. Incialmente, discutese os principais conceitos associados com os geradores, de interesse para a tarefa de proteção. Particular atenção é dedicada às formas de aterramento e aos critérios adotados para projeto do resistor de aterramento utilizado nesse equipamento. Em seguida, apresentam-se as principais funções de proteção aplicáveis aos geradores, particularmente aquelas voltadas para a detecção de faltas nos enrolamentos do estator. Discute-se também os critérios de ajustes dos parâmetros dessas funções. Descreve-se o uso de uma plataforma laboratorial, baseada em simulador de tempo real (RTDS), para ensaio e análise do sistema de proteção visando validar seu correto desempenho frente às possíveis condições operativas que podem ser encontradas em campo. Finalmente, utilizando os conceitos desenvolvidos ao longo do trabalho, desenvolve-se um estudo de caso, onde é realizado o projeto e implementação do sistema de proteção dos geradores de uma usina hidrelétrica hipotética. Para avaliar e analisar o desempenho do sistema de proteção dessa rede exemplo, parametrizou-se o IED G60 (GE) e realizou-se inúmeras simulações na plataforma de testes proposta.Protection systems play a critical role in the safety and reliability of electric power systems. The non-operation or wrong operation of protective relays during a fault in a network element can evolve to a systemic event in large scale (blackout). These events bring risks and high economic losses to society. Despite the high cost and complexity, the protection of synchronous generators has not received much attention in the literature devoted to protection of other network elements, such as transmission lines. This stems from the smaller number of generators in the network and also the idea that the faults in this type of equipment are less frequent. This research discusses the main aspects involved in the design of a protection system for large synchronous generators. Initially, it discusses the key concepts of interest to the generation protection. Particular attention is given to grounding techniques and the criteria adopted for the design of grounding resistors used in those equipment. Then the main protection functions applicable to generators are presented, particularly those related to fault detection in the stator windings. The criteria for setting the parameters of these functions are also discussed. After that, the use of a laboratory shelf, based on Real-Time Digital Simulator (RTDS) for testing and analysis of the protection system, is described in order to validate the correct performance in face of possible operating conditions in the field. Finally, a study case is developed using the concepts developed throughout the research. Then, the design and implementation of the protection system of generators of a hypothetical hydroelectric plant are carried out. To evaluate and analyze the performance of this example network protection system, parameterized up IED G60 (GE) and held numerous simulations in the proposed test platform.
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Smith, Guillaume. "Concevoir des applications temps-réel respectant la vie privée en exploitant les liens entre codes à effacements et les mécanismes de partages de secrets." Thesis, Toulouse, ISAE, 2014. http://www.theses.fr/2014ESAE0045/document.
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Une large quantité de données personnelles sont partagées en temps réel par des utilisateurs en ligne, utilisant de plus en plus des terminaux mobiles avec connexion sans-fil. L'industrie s'efforce d'accumuler et d'analyser ces données pour fournir de nouveaux services ou des améliorations. La recherche fournit un effort équivalent pour permettre de traiter ces données de façon sécurisée et protectrice de la vie privée. Les problèmes de performance des communications temps réels sur terminaux mobiles sur un canal sans-fil sont aussi étudiés. Les codes à effacement sont un moyen courant d'améliorer ces performances. Le secret sharing est un mécanisme permettant de partager des données privées, ne les révélant qu'à un groupe d'utilisateur choisi. Dans cette thèse, nous lions théoriquement les secret sharing schemes et les codes à effacement, pour fournir une source plus riche de solutions aux deux problèmes. Notre objectif est de fournir des solutions ayant le niveau de sécurité souhaité, tout en restant efficace et implémentable. Les contributions de cette thèse sont les suivantes. Nous évaluons l'applicabilité d'une nouvelle classe de codes à effacements à Maximum Distance Séparable (MDS) pour transférer du contenu temps réel à des terminaux mobiles, et nous démontrons que le code systématique réduit grandement la complexité d'exécution et la taille nécessaire des tampons en comparaison du code non systématique, faisant de lui un bon candidat pour une application mobile. Nous proposons un nouveau Layered secret sharing scheme pour le partage en temps réel de données sur des réseaux sociaux (OSNs pour Online Social Network). Le procédé permet de partager automatiquement un profile dans un groupe défini dans un OSN, en utilisant un multi-secret sharing scheme formé de multiples couches. Le procédé ne dépend nullement d'un tiers de confiance. Comparé à un partage simple de chaque attributs (pouvant être un texte, une image ou une vidéo), le procédé ne divulgue aucune information à propos de ce qui est partagé, pas même le nombre de ceux-ci, et il induit une augmentation relativement faible du temps de calcul et des données à envoyer. Finalement, nous étudions les liens entre les codes MDS et les secret sharing schemes, ayant pour motivation l'inefficacité du très populaire Shamir secret sharing scheme. Nous établissons les liens théoriques entre les deux domaines et nous proposons une nouvelle construction de strong ramp schemes à partir de codes MDS. Ceci permet d'utiliser les codes MDS existants et efficaces pour des applications de partage de secret et de calculs distribués et sécurisés. Nous évaluons et montrons une réduction significative de temps de calcul et du coût de communication en utilisant un strong ramp scheme, en comparaison avec le procédé de ShamirData from both individuals and companies is increasingly aggregated and analysed to provide new and improved services. There is a corresponding research effort to enable processing of such data in a secure and privacy preserving way, in line with the increasing public concerns and more stringent regulatory requirements for the protection of such data. Secure Multi-Party Computation (MPC) and secret sharing are mechanisms that can enable both secure distribution and computations on private data. In this thesis, we address the inefficiencies of these mechanisms by utilising results from a theoretically related rich area, erasure codes. We derive links between erasure codes and secret sharing, and use Maximum Distance Separable (MDS) codes as a basis to provide real-time applications relying on private user's data, revealing this data only to the selected group (which can be empty). The thesis has three contributions. A new class of erasure code called on-the-fly coding, have been introduced for their improvements in terms of recovery delay and achievable capacity. However little is known about the complexity of the systematic and non-systematic variants of this code, notably for live multicast transmission of multimedia content which is their ideal use case. The evaluation of both variants demonstrate that the systematic code outperforms the non-systematic one in regard to both the buffer sizes and the computation complexity. Then, we propose a new Layered secret sharing scheme and its application to Online Social Network (OSN). In current OSN, access to the user's profile information is managed by the service provider based on a limited set of rules. The proposed scheme enables automated profile sharing in OSN's groups with fine grained privacy control, via a multi-secret sharing scheme comprising of layered shares, without relying on a trusted third party. We evaluate the security of the scheme and the resulting profile's level of protection in an OSN scenario. Finally, after showing that erasure codes are efficient for real-time applications and that the security offered by secret sharing schemes can be applied to real-case applications, we derive the theoretical links between MDS codes and secret sharing to enable the implementation of efficient secret sharing scheme built from MDS codes. To illustrate this efficiency, we implement two of these schemes and evaluate their benefits in regard to computation and communication costs in an MPC application
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Barnett, William Halbert. "Duty Cycle Maintenance in an Artificial Neuron." Digital Archive @ GSU, 2009. http://digitalarchive.gsu.edu/phy_astr_theses/7.
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Neuroprosthetics is at the intersection of neuroscience, biomedical engineering, and physics. A biocompatible neuroprosthesis contains artificial neurons exhibiting biophysically plausible dynamics. Hybrid systems analysis could be used to prototype such artificial neurons. Biohybrid systems are composed of artificial and living neurons coupled via real-time computing and dynamic clamp. Model neurons must be thoroughly tested before coupled with a living cell. We use bifurcation theory to identify hazardous regimes of activity that may compromise biocompatibility and to identify control strategies for regimes of activity desirable for functional behavior. We construct real-time artificial neurons for the analysis of hybrid systems and demonstrate a mechanism through which an artificial neuron could maintain duty cycle independent of variations in period.
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Bataglioli, Rodrigo Pavanello. "Proteção digital de geradores eólicos com conversores de potência de escala completa no contexto das smart grids." Universidade de São Paulo, 2018. http://www.teses.usp.br/teses/disponiveis/18/18154/tde-25092018-155933/.
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Considerando condições anormais que o Sistema Elétrico de Potência (SEP) está sujeito, a proteção de seus elementos é um tópico importante. Dentre os equipamentos a serem protegidos, destacam-se os geradores devido a representarem elevado custo de investimento e estarem sujeitos a multas por paradas não programadas. Desta forma, com base em pesquisa bibliográfica, observa-se que não existem estudos abrangentes para a proteção individual de máquinas síncronas aplicadas à geração eólica. Além disso, considerando o contexto das smart grids, a presença de baterias e a possibilidade da operação ilhada podem alterar a dinâmica das situações de falta. Portanto, faz-se necessário um estudo do comportamento dos aerogeradores em situações de falha, sabendo que o esquema de proteção depende do tipo de gerador e da maneira como este está conectado ao SEP. Neste sentido, esta pesquisa propôs incluir uma bateria para operar com um gerador eólico de velocidade variável de forma complementar, suavizando a potência de saída e tornando o sistema de conversão de energia eólica forte o suficiente para operar no modo ilhado. A metodologia estabelece vários tipos de falhas para investigar o comportamento da turbina eólica em tais condições. Para realizar as simulações de falta, foi utilizado um simulador digital de tempo real (RTDS®). Com base nisso, um esquema composto por funções de proteção convencionais foi especificado e testado usando o software MATLAB®. Além disso, simulações em laço fechado foram realizadas com relés comercial e universal. Os resultados obtidos com o esquema proposto são bastante promissores.Considering abnormal conditions to which the Electric Power System (EPS) may be subjected, the protection of its elements is an important topic. Among the equipments to be protected, the generators are highlighted, because they represent a high investment cost and are subjected to penalties for unscheduled stoppages. Hence, based on literature, it is observed that there are no comprehensive studies and standards for individual protection of Synchronous Generators (SGs) applied to Wind Energy Conversion System (WECS). Furthermore, considering the smart grids context, the presence of batteries and the possibility of island operation may change the dynamic of fault situations. Therefore, it is necessary to study and analyse the behavior of wind turbines in fault situations, knowing that the protection scheme is dependent on the generator type and the way it is connected to the EPS. In order to study these issues, this research proposed to include a battery to operate with a full-variable speed wind generator in a complementary way, smoothing the output power and making the WECS strong enough to operate in the island mode. The methodology establishes several fault types to investigate the wind turbine behavior in such conditions. In order to conduct the fault simulations, a real time digital simulator (RTDS®) was used. Based on this, a scheme composed by conventional protection functions were specified and tested using the MATLAB® software. Furthermore, hardware-in-the-loop simulations were performed with commercial and universal relays. Very good results in favor of the proposed scheme are presented.
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Avramović, Nikola. "Testovací modul pro vybranou část standardu IEEE 802.1Q." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2019. http://www.nusl.cz/ntk/nusl-402127.
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Tato práce se zabývá analyzováním IEEE 802.1Q standardu TSN skupiny a návrhem testovacího modulu. Testovací modul je napsán v jazyku VHDL a je možné jej implementovat do Intel Stratix® V GX FPGA (5SGXEA7N2F45C2) vývojové desky. Standard IEEE 802.1Q (TSN) definuje deterministickou komunikace přes Ethernet sít, v reálném čase, požíváním globálního času a správným rozvrhem vysíláním a příjmem zpráv. Hlavní funkce tohoto standardu jsou: časová synchronizace, plánování provozu a konfigurace sítě. Každá z těchto funkcí je definovaná pomocí více různých podskupin tohoto standardu. Podle definice IEEE 802.1Q standardu je možno tyto podskupiny vzájemně libovolně kombinovat. Některé podskupiny standardu nemohou fungovat nezávisle, musí využívat funkce jiných podskupin standardu. Realizace funkce podskupin standardu je možná softwarově, hardwarově, nebo jejich kombinací. Na základě výše uvedených fakt, implementace podskupin standardu, které jsou softwarově související, byly vyloučené. Taky byly vyloučené podskupiny standardů, které jsou závislé na jiných podskupinách. IEEE 802.1Qbu byl vybrán jako vhodná část pro realizaci hardwarového testu. Různé způsoby testování byly vysvětleny jako DFT, BIST, ATPG a další jiné techniky. Pro hardwarové testování byla vybrána „Protocol Aware (PA)“technika, protože tato technika zrychluje testování, dovoluje opakovanou použitelnost a taky zkracuje dobu uvedení na trh. Testovací modul se skládá ze dvou objektů (generátor a monitor), které mají implementovanou IEEE 802.1Qbu podskupinu standardu. Funkce generátoru je vygenerovat náhodné nebo nenáhodné impulzy a potom je poslat do testovaného zařízeni ve správném definovaném protokolu. Funkce monitoru je přijat ethernet rámce a ověřit jejich správnost. Objekty jsou navrhnuty stejným způsobem na „TOP“úrovni a skládají se ze čtyř modulů: Avalon MM rozhraní, dvou šablon a jednoho portu. Avalon MM rozhraní bylo vytvořeno pro komunikaci softwaru s hardwarem. Tento modul přijme pakety ze softwaru a potom je dekóduje podle definovaného protokolu a „pod-protokolu “. „Pod-protokol“se skládá z příkazu a hodnoty daného příkazu. Podle dekódovaného příkazu a hodnot daných příkazem je kontrolovaný celý objekt. Šablona se používá na generování nebo ověřování náhodných nebo nenáhodných dat. Dvě šablony byly implementovány pro expresní ověřování nebo preempční transakce, definované IEEE 802.1Qbu. Porty byly vytvořené pro komunikaci mezi testovaným zařízením a šablonou podle daného standardu. Port „generátor“má za úkol vybrat a vyslat rámce podle priority a času vysílaní. Port „monitor“přijme rámce do „content-addressable memory”, která ověřuje priority rámce a podle toho je posílá do správné šablony. Výsledky prokázaly, že tato testovací technika dosahuje vysoké rychlosti a rychlé implementace.
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Kuchařová, Hana. "Technologie RFID v ekonomických sektorech." Master's thesis, Vysoká škola ekonomická v Praze, 2011. http://www.nusl.cz/ntk/nusl-85237.
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This thesis is focused on explanation of RFID technology. The first part analyses its historical development, describes the basic elements needed for its operation and standards enabling its spread into the supplier-customer chains. Furthermore are summarized its common applications such as systems for real-time location, traceability and identification of persons. Finally is summarized its usage in particular economic sectors. The end of the thesis is focused on suitable procedures for implementation of RFID technology into the enterprise, with respect to a feasibility of the project, which is determined in the initial study based on the methodology MMDIS.
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Alsmadi, Yazan M. "Modeling, Advance Control, and Grid Integration of Large-Scale DFIG-Based Wind Turbines during Normal and Fault Ride-Through Conditions." The Ohio State University, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=osu1437140573.
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Giovanardi, Samuele. "Study and development of an autonomous layout entering algorithm for an industrial AGV." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2021.
Find full textAbstract:
The main topic of this thesis is the trajectory generation for the autonomous layout entering of an automated guided vehicle in an indoor environment. I specifically studied a control model for a quadricycle vehicle.
The thesis is structured in four chapters.
The first chapter illustrates the Shark vehicles produced by System Logistics S.p.a.. In particular, the chapter is centred on the explanation of kinematic model of quadricycle vehicle, introducing also a brief explanation of what is a layout and an introduction of what is the operating system that control the process (QNX). The second chapter explain in a detailed way what is the problem of autonomous layout entering, also called auto-nsertion, and the control methodology to manage it, showing in a detailed way all the steps starting from the consideration of the pose of the vehicle and the final pose to reach, considering also all the mechanical limitations. The third chapter shows all the simulative work carried out by means the Matlab and Simulink tools. It shows also all the results both with an ideal model and a real one and considering some disturbances and measurement errors. In the fourth chapter the real test are explicated by the use of a real test area and a real AGV (Automated Guided Vehicle) with the Shark.
The conclusions highlight some considerations about the use of this method and some comparison with other possible methods.
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Tigori, Kabland Toussaint Gautier. "Méthode de génération d’exécutif temps-réel." Thesis, Ecole centrale de Nantes, 2016. http://www.theses.fr/2016ECDN0019.
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Dans les systèmes embarqués, la spécialisation ou la configuration des systèmes d’exploitation temps réel en fonction des besoins de l’application consiste en la suppression des services inutiles du système d’exploitation. Cela a non seulement pour but d’optimiser l’empreinte mémoire occupée par le système d’exploitation temps réel, afin de satisfaire les contraintes de mémoire auxquelles les systèmes embarqués font face, mais aussi de réduire la quantité de code mort au sein du système d’exploitation temps réel afin d’améliorer la sureté de fonctionnement. Dans nos travaux de thèse, nous nous intéressons à l’utilisation des méthodes formelles dans le processus de spécialisation des systèmes d’exploitation temps réel. Une difficulté majeure dans l’utilisation de modèles formels est la distance entre le modèle et le système modélisé. Nous proposons donc de modéliser le système d’exploitation de telle sorte que le modèle embarque son code source et les structures de données manipulées. Nous utilisons à cet effet un modèle à états finis (éventuellement temporisé) augmenté par des variables discrètes et des séquences d’instructions, considérées comme atomiques, manipulant ces variables. À partir du modèle du système d’exploitation et d’un modèle de l’application visée, l’ensemble des états accessibles du modèle du système d’exploitation traduisant le code effectivement utilisé lors de l’exécution de l’application est calculé. Le code source du système d’exploitation spécialisé est extrait de ce modèle élagué. L’ensemble de la démarche exposée est mise en oeuvre avec Trampoline, un système d’exploitation temps réel basée sur les standards OSEK/VDX et AUTOSAR. Cette technique de spécialisation garantit l’absence de code mort, minimise l’empreinte mémoire et fournit un modèle formel du système d’exploitation utilisable dans une étape ultérieure de modelchecking. Dans ce cadre, nous proposons une technique automatique de vérification formelle de la conformité aux standards OSEK/VDX et AUTOSAR à l’aide d’observateurs génériquesIn embedded systems, specialization or configuration of real-time operating systems according to the application requirements consists to remove the operating system services that are not needed by the application. This operation allows both to optimize the memory footprint occupied by the real-time operating system in order to meet the memory constraints in embedded systems and to reduce the amount of dead code inside the real-time operating system in order to improve its reliability. In this thesis, we focus on the use of formal methods to specialize real-time operating systems according applications. One major difficulty using formal models is the gap between the system model and its implementation. Thus, we propose to model the operating system so that the model embeds its source code and manipulated data structures. For this purpose, we use finite state model (possibly timed model) with discrete variables and sequences of instructions which are considered as atomic manipulating these variables. From the operating system model and an application model, the set of reachable states of the operating system model describing the code needed during application execution is computed. Thus, the source code of the specialized operating system is extracted from the pruned model. The overall approach is implemented with Trampoline, a real-time operating system based on OSEK/VDX and AUTOSAR standards. This specialization technique ensures the absence of dead code, minimizes the memory footprint and provides a formal model of the operating system used in a last step to check its behavior by using model checking. In this context, we propose an automatic formal verification technique that allows to check the operating systems according OSEK/VDX and AUTOSAR standards using generic observers
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Geitner, Gert-Helge. "Simulink Erweiterungsblockbibliothek, Funktionsplan." Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2013. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-119809.
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Das Softwarewerkzeug FUP Blockbibliothek wurde für Entwurf, Simulation, Echtzeitkodegenerierung und Dokumentation von ereignisgesteuerten Systemen, speziell in Maschinenbau, Mechatronik und Elektrotechnik entwickelt. Es stellt eine Erweiterung zu MATLAB /Simulink dar und bietet eine umfangreiche Entwurfsunterstützung einschließlich Werkzeugen zur Erkennung von Eingabe- und Strukturfehlern. Die graphische Darstellung (Blockikonen) lehnt sich an die VDI / VDE - Richtlinie 3684 "Beschreibung ereignisgesteuerter Bewegungsabläufe mit Funktionsplänen" an.
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Braun, Robert. "Hardware-in-the-Loop Simulation of Aircraft Actuator." Thesis, Linköping University, Linköping University, Department of Management and Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-20466.
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Advanced computer simulations will play a more and more important role in future aircraft development and aeronautic research. Hardware-in-the-loop simulations enable examination of single components without the need of a full-scale model of the system. This project investigates the possibility of conducting hardware-in-the-loop simulations using a hydraulic test rig utilizing modern computer equipment. Controllers and models have been built in Simulink and Hopsan. Most hydraulic and mechanical components used in Hopsan have also been translated from Fortran to C and compiled into shared libraries (.dll). This provides an easy way of importing Hopsan models in LabVIEW, which is used to control the test rig. The results have been compared between Hopsan and LabVIEW, and no major differences in the results could be found. Importing Hopsan components to LabVIEW can potentially enable powerful features not available in Hopsan, such as hardware-in-the-loop simulations, multi-core processing and advanced plotting tools. It does however require fast computer systems to achieve real-time speed. The results of this project can provide interesting starting points in the development of the next generation of Hopsan.