Relevant bibliographies by topics / Reconfigurable caches

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  1. Journal articles
  2. Dissertations / Theses
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  4. Conference papers

Academic literature on the topic 'Reconfigurable caches'

Author: Grafiati
Published: 4 June 2021
Last updated: 7 February 2022

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Journal articles on the topic "Reconfigurable caches"

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Begum, B. Shameedha, and N. Ramasubramanian. "Design of an Intelligent Data Cache with Replacement Policy." International Journal of Embedded and Real-Time Communication Systems 10, no. 2 (April 2019): 87–107. http://dx.doi.org/10.4018/ijertcs.2019040106.

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Embedded systems are designed for a variety of applications ranging from Hard Real Time applications to mobile computing, which demands various types of cache designs for better performance. Since real-time applications place stringent requirements on performance, the role of the cache subsystem assumes significance. Reconfigurable caches meet performance requirements under this context. Existing reconfigurable caches tend to use associativity and size for maximizing cache performance. This article proposes a novel approach of a reconfigurable and intelligent data cache (L1) based on replacement algorithms. An intelligent embedded data cache and a dynamic reconfigurable intelligent embedded data cache have been implemented using Verilog 2001 and tested for cache performance. Data collected by enabling the cache with two different replacement strategies have shown that the hit rate improves by 40% when compared to LRU and 21% when compared to MRU for sequential applications which will significantly improve performance of embedded real time application.
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Zhu, Wei, and Xiaoyang Zeng. "Decision Tree-Based Adaptive Reconfigurable Cache Scheme." Algorithms 14, no. 6 (June 1, 2021): 176. http://dx.doi.org/10.3390/a14060176.

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Applications have different preferences for caches, sometimes even within the different running phases. Caches with fixed parameters may compromise the performance of a system. To solve this problem, we propose a real-time adaptive reconfigurable cache based on the decision tree algorithm, which can optimize the average memory access time of cache without modifying the cache coherent protocol. By monitoring the application running state, the cache associativity is periodically tuned to the optimal cache associativity, which is determined by the decision tree model. This paper implements the proposed decision tree-based adaptive reconfigurable cache in the GEM5 simulator and designs the key modules using Verilog HDL. The simulation results show that the proposed decision tree-based adaptive reconfigurable cache reduces the average memory access time compared with other adaptive algorithms.
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Ho, Nam, Paul Kaufmann, and Marco Platzner. "Evolution of application-specific cache mappings." International Journal of Hybrid Intelligent Systems 16, no. 3 (September 28, 2020): 149–61. http://dx.doi.org/10.3233/his-200281.

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Reconfigurable caches offer an intriguing opportunity to tailor cache behavior to applications for better run-times and energy consumptions. While one may adapt structural cache parameters such as cache and block sizes, we adapt the memory-address-to-cache-index mapping function to the needs of an application. Using a LEON3 embedded multi-core processor with reconfigurable cache mappings, a metaheuristic search procedure, and MiBench applications, we show in this work how to accurately compare non-deterministic performances of applications and how to use this information to implement an optimization procedure that evolves application-specific cache mappings for the LEON3 multi-core processor.
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Yang, Xue-Jun, Jun-Jie Wu, Kun Zeng, and Yu-Hua Tang. "Managing Data-Objects in Dynamically Reconfigurable Caches." Journal of Computer Science and Technology 25, no. 2 (March 2010): 232–45. http://dx.doi.org/10.1007/s11390-010-9320-6.

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Ranganathan, Parthasarathy, Sarita Adve, and Norman P. Jouppi. "Reconfigurable caches and their application to media processing." ACM SIGARCH Computer Architecture News 28, no. 2 (May 2000): 214–24. http://dx.doi.org/10.1145/342001.339685.

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Huang, Yuanwen, and Prabhat Mishra. "Vulnerability-Aware Energy Optimization for Reconfigurable Caches in Multitasking Systems." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38, no. 5 (May 2019): 809–21. http://dx.doi.org/10.1109/tcad.2018.2834410.

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Bengueddach, A., B. Senouci, S. Niar, and B. Beldjilali. "Two-level caches tuning technique for energy consumption in reconfigurable embedded MPSoC." Journal of Systems Architecture 59, no. 8 (September 2013): 656–66. http://dx.doi.org/10.1016/j.sysarc.2013.05.018.

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Coole, James, and Greg Stitt. "Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures." International Journal of Reconfigurable Computing 2010 (2010): 1–16. http://dx.doi.org/10.1155/2010/652620.

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Field-programmable gate arrays (FPGAs) and other reconfigurable computing (RC) devices have been widely shown to have numerous advantages including order of magnitude performance and power improvements compared to microprocessors for some applications. Unfortunately, FPGA usage has largely been limited to applications exhibiting sequential memory access patterns, thereby prohibiting acceleration of important applications with irregular patterns (e.g., pointer-based data structures). In this paper, we present a design pattern for RC application development that serializes irregular data structure traversals online into a traversal cache, which allows the corresponding data to be efficiently streamed to the FPGA. The paper presents a generalized framework that benefits applications with repeated traversals, which we show can achieve between 7x and 29x speedup over pointer-based software. For applications without strictly repeated traversals, we present application-specialized extensions that benefit applications with highly similar traversals by exploiting similarity to improve memory bandwidth and execute multiple traversals in parallel. We show that these extensions can achieve a speedup between 11x and 70x on a Virtex4 LX100 for Barnes-Hut n-body simulation.
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Azad, Zahra, Hamed Farbeh, Amir Mahdi Hosseini Monazzah, and Seyed Ghassem Miremadi. "AWARE: Adaptive Way Allocation for Reconfigurable ECCs to Protect Write Errors in STT-RAM Caches." IEEE Transactions on Emerging Topics in Computing 7, no. 3 (July 1, 2019): 481–92. http://dx.doi.org/10.1109/tetc.2017.2701880.

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KIM, YOONJIN. "POWER-EFFICIENT CONFIGURATION CACHE STRUCTURE FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURE." Journal of Circuits, Systems and Computers 22, no. 03 (March 2013): 1350001. http://dx.doi.org/10.1142/s0218126613500011.

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Coarse-grained reconfigurable architectures (CGRA) require many processing elements (PEs) and a configuration memory unit (configuration cache) for reconfiguration of its PE array. Although this structure is meant for high performance and flexibility, it consumes significant power. Specially, power consumption by configuration cache is explicit overhead compared to other types of IP cores. Reducing power in configuration cache is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. In this paper, I propose a power-efficient configuration cache structure based on two design schemes — one is a reusable context pipelining (RCP) architecture to reduce power-overhead caused by reconfiguration and another is a dynamic context management strategy for power saving in configuration cache. This power-efficient approach works without degrading the performance and flexibility of CGRA. Experimental results show that the proposed approach saves 56.50%/86.84% of the average power in write/read-operation of configuration cache compared to the previous design.
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Dissertations / Theses on the topic "Reconfigurable caches"

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Ramaswamy, Subramanian. "Active management of Cache resources." Diss., Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24663.

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This dissertation addresses two sets of challenges facing processor design as the industry enters the deep sub-micron region of semiconductor design. The first set of challenges relates to the memory bottleneck. As the focus shifts from scaling processor frequency to scaling the number of cores, performance growth demands increasing die area. Scaling the number of cores also places a concurrent area demand in the form of larger caches. While on-chip caches occupy 50-60% of area and consume 20-30% of energy expended on-chip, their performance and energy efficiencies are less than 15% and 1% respectively for a range of benchmarks! The second set of challenges is posed by transistor leakage and process variation (inter-die and intra-die) at future technology nodes. Leakage power is anticipated to increase exponentially and sharply lower defect-free yield with successive technology generations. For performance scaling to continue, cache efficiencies have to improve significantly. This thesis proposes and evaluates a broad family of such improvements. This dissertation first contributes a model for cache efficiencies and finds them to be extremely low - performance efficiencies less than 15% and energy efficiencies in the order of 1%. Studying the sources of inefficiency leads to a framework for efficiency improvement based on two interrelated strategies. The approach for improving energy efficiency primarily relies on sizing the cache to match the application memory footprint during a program phase while powering down all remaining cache sets. Importantly, the sized is fully functional with no references to inactive sets. Improving performance efficiency primarily relies on cache shaping, i.e., changing the placement function and thereby the manner in which memory shares the cache. Sizing and shaping are applied at different phase of the design cycle: i) post-manufacturing & offline, ii) at compile-time, and at iii) run-time. This thesis proposes and explores techniques at each phase collectively realizing a repertoire of techniques for future memory system designers. The techniques use a combination of HW-SW techniques and are demonstrated to provide substantive improvements with modest overheads.
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Brewer, Jeffery R. "Reconfigurable cache memory /." Available to subscribers only, 2009. http://proquest.umi.com/pqdweb?did=1885437651&sid=8&Fmt=2&clientId=1509&RQT=309&VName=PQD.

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Brewer, Jeffery Ramon. "Reconfigurable Cache Memory." OpenSIUC, 2009. https://opensiuc.lib.siu.edu/theses/48.

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AN ABSTRACT OF THE THESIS OF Jeffery R. Brewer, for the Master degree in Electrical Computer Engineer, presented on May 22, 2009 at Southern Illinois University Carbondale. TITLE: Reconfigurable Cache Memory MAJOR PROFESSOR: Dr. Nazeih Botros As chip designers continue to push the performance of microprocessors to higher levels the energy demand grows. The increase need for integrated chips that provide energy savings without degrading performance is paramount. The cache memory is typically over fifty percent of the size of today's microprocessor chip, and consumes a significant percentage of the total power. Therefore, by designing a reconfigurable cache that's able to dynamically adjust to a smaller cache size without encountering a significant degrade in performance, we are able to realize power conservation. Tournament caching is a reconfigurable method that tracks the current performance of the cache and compares it to possible smaller or larger cache size [1] . The results in this thesis shows that reconfigurable cache memory implemented with a configuration mechanism like Tournament caching would take advantage of associativity and cache size while providing energy conservation. i
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JUPALLY, RAGHAVENDRA PRASADA RAO. "IMPLEMENTATION OF RECONFIGURABLE COMPUTING CACHE ARCHITECTURE." OpenSIUC, 2010. https://opensiuc.lib.siu.edu/theses/336.

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In a modern microprocessor, a considerable portion of the chip is dedicated to cache memories. However some applications do not utilize all the cache capacity all the time, on the other side these applications may require more computing power than the actual computing capability. To efficiently utilize the on-chip resources, in this project we have designed and implemented the reconfigurable computing cache architecture, this design is implemented as a schematic in Xilinx. In this architecture a part of an L1 data cache is designed as a reconfigurable functional cache which can act as a conventional cache memory module in memory mode and also work as specialized computing that can perform a selective core function whenever such computing capability is required. Using this reconfigurable cache architecture the execution of the core functions of compute intensive applications are accelerated, due to which the execution time and the number of instructions are significantly reduced, which results in the increased performance of the processor.
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Bond, Paul Joseph. "Design and analysis of reconfigurable and adaptive cache structures." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/14983.

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Ho, Nam [Verfasser]. "FPGA-based reconfigurable cache mapping schemes: design and optimization / Nam Ho." Paderborn : Universitätsbibliothek, 2018. http://d-nb.info/1167856481/34.

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Bani, Ruchi Rastogi Mohanty Saraju. "A new N-way reconfigurable data cache architecture for embedded systems." [Denton, Tex.] : University of North Texas, 2009. http://digital.library.unt.edu/ark:/67531/metadc12079.

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Bani, Ruchi Rastogi. "A New N-way Reconfigurable Data Cache Architecture for Embedded Systems." Thesis, University of North Texas, 2009. https://digital.library.unt.edu/ark:/67531/metadc12079/.

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Performance and power consumption are most important issues while designing embedded systems. Several studies have shown that cache memory consumes about 50% of the total power in these systems. Thus, the architecture of the cache governs both performance and power usage of embedded systems. A new N-way reconfigurable data cache is proposed especially for embedded systems. This thesis explores the issues and design considerations involved in designing a reconfigurable cache. The proposed reconfigurable data cache architecture can be configured as direct-mapped, two-way, or four-way set associative using a mode selector. The module has been designed and simulated in Xilinx ISE 9.1i and ModelSim SE 6.3e using the Verilog hardware description language.
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Junior, Roberto Borges Kerr. "Proposta e desenvolvimento de um algoritmo de associatividade reconfigurável em memórias cache." Universidade de São Paulo, 2008. http://www.teses.usp.br/teses/disponiveis/3/3141/tde-01102008-135441/.

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A evolução constante dos processadores está aumentando cada vez o overhead dos acessos à memória. Tentando evitar este problema, os desenvolvedores de processadores utilizam diversas técnicas, entre elas, o emprego de memórias cache na hierarquia de memórias dos computadores. As memórias cache, por outro lado, não conseguem suprir totalmente as suas necessidades, sendo interessante alguma técnica que tornasse possível aproveitar melhor a memória cache. Para resolver este problema, autores propõem a utilização de técnicas de computação reconfigurável. Este trabalho analisa um trabalho na área de reconfiguração na associatividade de memórias cache, e propõe melhorias nele para uma melhor utilização de seus recursos, apresentando resultados práticos de simulações realizadas com diversas organizações de cache.
With the constant evolution of processors architecture, its getting even bigger the overhead generated with memory access. Trying to avoid this problem, some processors developers are using several techniques to improve the performance, as the use of cache memories. By the otherside, cache memories cannot supply all their needs, thats why its important some new technique that could use better the cache memory. Working on this problem, some authors are using reconfigurable computing to improve the cache memorys performance. This work analyses the reconfiguration of the cache memory associativity algorithm, and propose some improvements on this algorithm to better use its resources, showing some practical results from simulations with several cache organizations.
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Avakian, Annie. "Reducing Cache Access Time in Multicore Architectures Using Hardware and Software Techniques." University of Cincinnati / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1335461322.

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Book chapters on the topic "Reconfigurable caches"

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Ofori-Attah, Emmanuel, Xiaohang Wang, and Michael Opoku Agyeman. "A Survey of Low Power Design Techniques for Last Level Caches." In Applied Reconfigurable Computing. Architectures, Tools, and Applications, 217–28. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-78890-6_18.

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Benitez, D., J. C. Moure, D. I. Rexachs, and E. Luque. "A Reconfigurable Data Cache for Adaptive Processors." In Reconfigurable Computing: Architectures and Applications, 230–42. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11802839_31.

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Navarro, Osvaldo, and Michael Huebner. "Runtime Adaptive Cache for the LEON3 Processor." In Applied Reconfigurable Computing. Architectures, Tools, and Applications, 343–54. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-78890-6_28.

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Han, Xing, Jiang Jiang, Yuzhuo Fu, and Chang Wang. "Reconfigurable Many-Core Processor with Cache Coherence." In Communications in Computer and Information Science, 198–207. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-41635-4_21.

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Hu, Sensen, Anthony Brandon, Qi Guo, and Yizhuo Wang. "Improving the Performance of Adaptive Cache in Reconfigurable VLIW Processor." In Lecture Notes in Computer Science, 3–15. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-56258-2_1.

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Vergos, Haridimos T., Dimitris Nikolos, Petros Mitsiadis, and Chrisovalantis Kavousianos. "Reconfigurable CPU Cache Memory Design: Fault Tolerance and Performance Evaluation." In VLSI: Integrated Systems on Silicon, 103–14. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-0-387-35311-1_9.

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"Defect Rate Analysis & Reduction of MPSOC Through Run Time Reconfigurable Computing with Multiple Caches." In International Conference on Computer Technology and Development, 3rd (ICCTD 2011), 413–18. ASME Press, 2011. http://dx.doi.org/10.1115/1.859919.paper71.

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Véstias, Mário Pereira. "Field-Programmable Gate Array." In Encyclopedia of Information Science and Technology, Fifth Edition, 257–70. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-3479-3.ch020.

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Field-programmable gate arrays (FPGAs) are integrated circuits whose logic and their interconnections are configurable. These devices are field-programmable, that is, they can be configured by the hardware designer without any intervention of the manufacturer. Most FPGAs can be reprogrammed as many times as we want with a vast variety of digital circuits. Some recent FPGA families are system-on-chips (SoC) with one or more microprocessor cores, memory, cache, and reconfigurable logic allowing the implementation of complex hardware/software systems in a single programmable device. This article focuses on the architecture of FPGAs, including the so called SoC FPGA. It explains the main blocks of the FPGA, how they have evolved along the last decades and the perspectives of next generation FPGAs. It also describes some applicability areas and how its architecture have evolved to adapt to some of these target markets.
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Conference papers on the topic "Reconfigurable caches"

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Naz, Afrin, Krishna Kavi, JungHwan Oh, and Pierfrancesco Foglia. "Reconfigurable split data caches." In the 2007 ACM symposium. New York, New York, USA: ACM Press, 2007. http://dx.doi.org/10.1145/1244002.1244160.

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Dahlgren, Fredrik, and Per Stenström. "On reconfigurable on-chip data caches." In the 24th annual international symposium. New York, New York, USA: ACM Press, 1991. http://dx.doi.org/10.1145/123465.123504.

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Ranganathan, Parthasarathy, Sarita Adve, and Norman P. Jouppi. "Reconfigurable caches and their application to media processing." In the 27th annual international symposium. New York, New York, USA: ACM Press, 2000. http://dx.doi.org/10.1145/339647.339685.

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Donvanavard, Brvan, Amir Mahdi Hosseini Monazzah, Nikil Dutt, and Tiago Muck. "Exploring Hybrid Memory Caches in Chip Multiprocessors." In 2018 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC). IEEE, 2018. http://dx.doi.org/10.1109/recosoc.2018.8449386.

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Tada, Jubee, Masayuki Sato, and Ryusuke Egawa. "An Adaptive Demotion Policy for High-Associativity Caches." In HEART2017: The 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. New York, NY, USA: ACM, 2017. http://dx.doi.org/10.1145/3120895.3120906.

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Ho, Nam, Paul Kaufmann, and Marco Platzner. "Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor." In 2017 International Conference on Field Programmable Technology (ICFPT). IEEE, 2017. http://dx.doi.org/10.1109/fpt.2017.8280144.

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Huang, Yuanwen, and Prabhat Mishra. "Vulnerability-Aware Energy Optimization Using Reconfigurable Caches in Multicore Systems." In 2017 IEEE 35th International Conference on Computer Design (ICCD). IEEE, 2017. http://dx.doi.org/10.1109/iccd.2017.44.

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Ho, Nam, Paul Kaufmann, and Marco Platzner. "Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure." In 2014 IEEE International Conference on Evolvable Systems (ICES). IEEE, 2014. http://dx.doi.org/10.1109/ices.2014.7008719.

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Bengueddach, A., B. Senouci, S. Niar, and B. Beldjilali. "Energy consumption in reconfigurable mpsoc architecture: Two-level caches optimization oriented approach." In 2013 Design and Test Symposium (IDT). IEEE, 2013. http://dx.doi.org/10.1109/idt.2013.6727118.

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Navarro, Osvaldo, Tim Leiding, and Michael Hubner. "Configurable cache tuning with a victim cache." In 2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC). IEEE, 2015. http://dx.doi.org/10.1109/recosoc.2015.7238080.

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