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Dissertations / Theses on the topic 'Reconfigurable caches'
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1
Ramaswamy, Subramanian. "Active management of Cache resources." Diss., Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24663.
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This dissertation addresses two sets of challenges facing processor design as the industry enters the deep sub-micron region of semiconductor design. The first set of challenges relates to the memory bottleneck. As the focus shifts from scaling processor frequency to scaling the number of cores, performance growth demands increasing die area. Scaling the number of cores also places a concurrent area demand in the form of larger caches. While on-chip caches occupy 50-60% of area and consume 20-30% of energy expended on-chip, their performance and energy efficiencies are less than 15% and 1% respectively for a range of benchmarks! The second set of challenges is posed by transistor leakage and process variation (inter-die and intra-die) at future technology nodes. Leakage power is anticipated to increase exponentially and sharply lower defect-free yield with successive technology generations. For performance scaling to continue, cache efficiencies have to improve significantly. This thesis proposes and evaluates a broad family of such improvements.
This dissertation first contributes a model for cache efficiencies and finds them to be extremely low - performance efficiencies less than 15% and energy efficiencies in the order of 1%. Studying the sources of inefficiency leads to a framework for efficiency improvement based on two interrelated strategies. The approach for improving energy efficiency primarily relies on sizing the cache to match the application memory footprint during a program phase while powering down all remaining cache sets. Importantly, the sized is fully functional with no references to inactive sets. Improving performance efficiency primarily relies on cache shaping, i.e., changing the placement function and thereby the manner in which memory shares the cache.
Sizing and shaping are applied at different phase of the design cycle: i) post-manufacturing & offline, ii) at compile-time, and at iii) run-time. This thesis proposes and explores techniques at each phase collectively realizing a repertoire of techniques for future memory system designers. The techniques use a combination of HW-SW techniques and are demonstrated to provide substantive improvements with modest overheads.
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Brewer, Jeffery R. "Reconfigurable cache memory /." Available to subscribers only, 2009. http://proquest.umi.com/pqdweb?did=1885437651&sid=8&Fmt=2&clientId=1509&RQT=309&VName=PQD.
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Brewer, Jeffery Ramon. "Reconfigurable Cache Memory." OpenSIUC, 2009. https://opensiuc.lib.siu.edu/theses/48.
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AN ABSTRACT OF THE THESIS OF Jeffery R. Brewer, for the Master degree in Electrical Computer Engineer, presented on May 22, 2009 at Southern Illinois University Carbondale. TITLE: Reconfigurable Cache Memory MAJOR PROFESSOR: Dr. Nazeih Botros As chip designers continue to push the performance of microprocessors to higher levels the energy demand grows. The increase need for integrated chips that provide energy savings without degrading performance is paramount. The cache memory is typically over fifty percent of the size of today's microprocessor chip, and consumes a significant percentage of the total power. Therefore, by designing a reconfigurable cache that's able to dynamically adjust to a smaller cache size without encountering a significant degrade in performance, we are able to realize power conservation. Tournament caching is a reconfigurable method that tracks the current performance of the cache and compares it to possible smaller or larger cache size [1] . The results in this thesis shows that reconfigurable cache memory implemented with a configuration mechanism like Tournament caching would take advantage of associativity and cache size while providing energy conservation. i
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JUPALLY, RAGHAVENDRA PRASADA RAO. "IMPLEMENTATION OF RECONFIGURABLE COMPUTING CACHE ARCHITECTURE." OpenSIUC, 2010. https://opensiuc.lib.siu.edu/theses/336.
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In a modern microprocessor, a considerable portion of the chip is dedicated to cache memories. However some applications do not utilize all the cache capacity all the time, on the other side these applications may require more computing power than the actual computing capability. To efficiently utilize the on-chip resources, in this project we have designed and implemented the reconfigurable computing cache architecture, this design is implemented as a schematic in Xilinx. In this architecture a part of an L1 data cache is designed as a reconfigurable functional cache which can act as a conventional cache memory module in memory mode and also work as specialized computing that can perform a selective core function whenever such computing capability is required. Using this reconfigurable cache architecture the execution of the core functions of compute intensive applications are accelerated, due to which the execution time and the number of instructions are significantly reduced, which results in the increased performance of the processor.
5
Bond, Paul Joseph. "Design and analysis of reconfigurable and adaptive cache structures." Diss., Georgia Institute of Technology, 1995. http://hdl.handle.net/1853/14983.
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Ho, Nam [Verfasser]. "FPGA-based reconfigurable cache mapping schemes: design and optimization / Nam Ho." Paderborn : Universitätsbibliothek, 2018. http://d-nb.info/1167856481/34.
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Bani, Ruchi Rastogi Mohanty Saraju. "A new N-way reconfigurable data cache architecture for embedded systems." [Denton, Tex.] : University of North Texas, 2009. http://digital.library.unt.edu/ark:/67531/metadc12079.
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Bani, Ruchi Rastogi. "A New N-way Reconfigurable Data Cache Architecture for Embedded Systems." Thesis, University of North Texas, 2009. https://digital.library.unt.edu/ark:/67531/metadc12079/.
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Performance and power consumption are most important issues while designing embedded systems. Several studies have shown that cache memory consumes about 50% of the total power in these systems. Thus, the architecture of the cache governs both performance and power usage of embedded systems. A new N-way reconfigurable data cache is proposed especially for embedded systems. This thesis explores the issues and design considerations involved in designing a reconfigurable cache. The proposed reconfigurable data cache architecture can be configured as direct-mapped, two-way, or four-way set associative using a mode selector. The module has been designed and simulated in Xilinx ISE 9.1i and ModelSim SE 6.3e using the Verilog hardware description language.
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Junior, Roberto Borges Kerr. "Proposta e desenvolvimento de um algoritmo de associatividade reconfigurável em memórias cache." Universidade de São Paulo, 2008. http://www.teses.usp.br/teses/disponiveis/3/3141/tde-01102008-135441/.
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A evolução constante dos processadores está aumentando cada vez o overhead dos acessos à memória. Tentando evitar este problema, os desenvolvedores de processadores utilizam diversas técnicas, entre elas, o emprego de memórias cache na hierarquia de memórias dos computadores. As memórias cache, por outro lado, não conseguem suprir totalmente as suas necessidades, sendo interessante alguma técnica que tornasse possível aproveitar melhor a memória cache. Para resolver este problema, autores propõem a utilização de técnicas de computação reconfigurável. Este trabalho analisa um trabalho na área de reconfiguração na associatividade de memórias cache, e propõe melhorias nele para uma melhor utilização de seus recursos, apresentando resultados práticos de simulações realizadas com diversas organizações de cache.With the constant evolution of processors architecture, its getting even bigger the overhead generated with memory access. Trying to avoid this problem, some processors developers are using several techniques to improve the performance, as the use of cache memories. By the otherside, cache memories cannot supply all their needs, thats why its important some new technique that could use better the cache memory. Working on this problem, some authors are using reconfigurable computing to improve the cache memorys performance. This work analyses the reconfiguration of the cache memory associativity algorithm, and propose some improvements on this algorithm to better use its resources, showing some practical results from simulations with several cache organizations.
10
Avakian, Annie. "Reducing Cache Access Time in Multicore Architectures Using Hardware and Software Techniques." University of Cincinnati / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1335461322.
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Mesquita, Daniel Gomes. "Architectures Reconfigurables et Cryptographie : une analyse de robustesse face aux attaques par canaux cachés." Montpellier 2, 2006. http://www.theses.fr/2006MON20097.
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Ce travail constitue une étude sur la conception d’une architecture reconfigurable pour la cryptographie. Divers aspects sont étudiés, tels que les principes de base de la cryptographie, l’arithmétique modulaire, les attaques matériaux et les architectures reconfigurables. Des méthodes originales pour contrecarrer les attaques par canaux cachés, notamment la DPA, sont proposés. L’architecture proposée est efficace du point de vue de la performance et surtout est robuste contre la DPAThis work addresses the reconfigurable architectures for cryptographic applications theme, emphasizing the robustness issue. Some mathematical background is reviewed, as well the state of art of reconfigurable architectures. Side channel attacks, specially the DPA and SPA attacks, are studied. As consequence, algorithmic, hardware and architectural countermeasures are proposed. A new parallel reconfigurable architecture is proposed to implement the Leak Resistant Arithmetic. This new architecture outperforms most of state of art circuits for modular exponentiation, but the main feature of this architecture is the robustness against DPA attacks
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Gomes, Mesquita Daniel. "Architectures Reconfigurables et Cryptographie: Une Analyse de Robustesse et Contremesures Face aux Attaques par Canaux Cachés." Phd thesis, Université Montpellier II - Sciences et Techniques du Languedoc, 2006. http://tel.archives-ouvertes.fr/tel-00115736.
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Ce travail constitue une étude sur la conception d'une architecture reconfigurable pour lacryptographie. Divers aspects sont étudiés, tels que les principes de base de la cryptographie,
l'arithmétique modulaire, les attaques matériaux et les architectures reconfigurables. Des méthodes
originales pour contrecarrer les attaques par canaux cachés, notamment la DPA, sont proposés.
L'architecture proposée est efficace du point de vue de la performance et surtout est robuste contre
la DPA.
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Cuminato, Lucas Albers. "Otimização de memória cache em tempo de execução para o processador embarcado LEON3." Universidade de São Paulo, 2014. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-22092014-161846/.
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O consumo de energia é uma das questões mais importantes em sistemas embarcados. Estudos demonstram que neste tipo de sistema a cache é responsável por consumir a maior parte da energia fornecida ao processador. Na maioria dos processadores embarcados, os parâmetros de configuração da cache são fixos e não permitem mudanças após sua fabricação/síntese. Entretanto, este não é o cenário ideal, pois a configuração da cache pode não ser adequada para uma determinada aplicação, tendo como consequência menor desempenho na execução e consumo excessivo de energia. Neste contexto, este trabalho apresenta uma implementação em hardware, utilizando computação reconfigurável, capaz de reconfigurar automática, dinâmica e transparentemente a quantidade de ways e por consequência o tamanho da cache de dados do processador embarcado LEON3, de forma que a cache se adeque à aplicação em tempo de execução. Com esta técnica, espera-se melhorar o desempenho das aplicações e reduzir o consumo de energia do sistema. Os resultados dos experimentos demonstram que é possível reduzir em até 5% o consumo de energia das aplicações com degradação de apenas 0.1% de desempenhoEnergy consumption is one of the most important issues in embedded systems. Studies have shown that in this type of system the cache consumes most of the power supplied to the processor. In most embedded processors, the cache configuration parameters are fixed and do not allow changes after manufacture/synthesis. However, this is not the ideal scenario, since the configuration of the cache may not be suitable for a particular application, resulting in lower performance and excessive energy consumption. In this context, this project proposes a hardware implementation, using reconfigurable computing, able to reconfigure the parameters of the LEON3 processor\'s cache in run-time improving applications performance and reducing the power consumption of the system. The result of the experiment shows it is possible to reduce the processor\'s power consumption up to 5% with only 0.1% degradation in performance
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Brogioli, Michael C. "Dynamically reconfigurable data caches in low-power computing." Thesis, 2003. http://hdl.handle.net/1911/17647.
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In order to curb microprocessor power consumption, we propose an L1 data cache which can be reconfigured dynamically at runtime according to the cache requirements of a given application. A two phase approach is used involving both compile time information, and the runtime monitoring of program performance. The compiler predicts L1 data cache requirements of loop nests in the input program, and instructs the hardware on how much L1 data cache to enable during a loop nest's execution. For regions of the program not analyzable at compile time, the hardware itself monitors program performance and reconfigures the L1 data cache so as to maintain cache performance while minimizing cache power consumption. In addition to this, we provide a study of data reuses inside loop nests of the SPEC CPU2000 and Mediabench benchmarks. The sensitivity of data reuses to L1 data cache associativity is analyzed to illustrated the potential power savings a reconfigurable L1 data cache can achieve.
15
Bandara, Sahan Lakshitha. "Investigating the viability of adaptive caches as a defense mechanism against cache side-channel attacks." Thesis, 2019. https://hdl.handle.net/2144/36079.
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The ongoing miniaturization of semiconductor manufacturing technologies has enabled the integration of tens to hundreds of processing cores on a single chip. Unlike frequency-scaling where performance is increased equally across the board, core-scaling and hardware thread-scaling harness the additional processing power through the concurrent execution of multiple processes or programs. This approach of mingling or interleaving process executions has engendered a new set of security challenges that risks to undermine nearly three decades’ worth of computer architecture design efforts.
The complexity of the runtime interactions and aggressive resource sharing among processes, e.g., caches or interconnect network paths, have created a fertile ground to mount attacks of ever-increasing acuteness against these computer systems. One such class of attacks is cache side-channel attacks.
While caches are vital to the performance of current processors, they have also been the target of numerous side-channel attacks. As a result, a few cache architectures have been proposed to defend against these attacks. However, these designs tend to provide security at the expense of performance, area and power. Therefore, the design of secure, high-performance cache architectures is still a pressing research challenge.
In this thesis, we examine the viability of self-aware adaptive caches as a defense mechanism against cache side-channel attacks. We define an adaptive cache as a caching structure with (i) run-time reconfiguration capability, and (ii) intelligent built-in logic to monitor itself and determine its parameter settings. Since the success of most cache side-channel attacks depend on the attacker’s knowledge of the key cache parameters such as associativity, set count, replacement policy, among others, an adaptive cache can provide a moving target defense approach against many of these cache side-channel attacks.
Therefore, we hypothesize that the runtime changes in certain cache parameters should render some of the side-channel attacks less effective due to their dependence on knowing the exact configuration of the caches.2020-06-03T00:00:00Z
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Barzegar, Ali. "Dynamically Reconfigurable Active Cache Modeling." Thesis, 2014. http://spectrum.library.concordia.ca/978188/1/Barzegar_MASc_S2014.pdf.
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This thesis presents a novel dynamically reconfigurable active L1 instruction and data cache model, called DRAC. Employing cache, particularly L1, can speed up memory accesses, reduce the effects of memory bottleneck and consequently improve the system performance; however, efficient design of a cache for embedded systems requires fast and early performance modeling. Our proposed model is cycle accurate instruction and data cache emulator that is designed as an on-chip hardware peripheral on FPGA. The model can also be integrated into multicore emulation system and emulate multiple caches of the cores. DRAC model is implemented on Xilinx Virtex 5 FPGA and validated using several benchmarks. Our experimental results show the model can accurately estimate the execution time of a program both as a standalone and multicore cache emulator. We have observed 2.78% average error and 5.06% worst case error when DRAC is used as a standalone cache model in a single core design. We also observed 100% relative accuracy in design space exploration and less than 13% absolute worst case timing estimation error when DRAC is used as multicore cache emulator.
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Lin, Chia Hao, and 林嘉豪. "On-Line Reconfigurable Cache for Embedded Systems." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/49976132696808727162.
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碩士國立暨南國際大學
資訊工程學系
94
To reduce energy consumption, this work investigates an on-line reconfigurable cache architecture for embedded systems. First, some front-end instructions of the application are preloaded into the instruction cache before running to reduce the power consumption due to off-chip memory. Second, the way-prediction is adopted to reduce the power consumption due to the n-way set associative cache. Third, we propose a most-case optimal configuration searching algorithm that can operate faster and increase precision significantly. Even with the same application, different inputs would lead to different configurations. Based on this point, an on-line reconfigurable cache algorithm for different inputs is finally derived for searching an optimal configuration of the cache for each application for saving power near-real-time. Experimental results show that our non-on-line reconfigurable cache structure saves 12.86% of the total memory access energy over Zhang's. Furthermore, the proposed on-line reconfigurable cache can save 14.57% of memory access energy compared with the non-on-line one.
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Jheng, Geng-Cyuan, and 鄭耕全. "Real-time Reconfigurable Cache for Low-Power Embedded Systems." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/39182178624040456726.
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碩士國立暨南國際大學
資訊工程學系
96
Modern embedded systems execute a small set of applications or even a single one repeatedly. Specializing cache configurations to a particular application is well-known to have great benefits on performance and power. To reduce the searching for optimal cache configuration, a most-case optimal cache configuration searching algorithm for the entire execution of an application was proposed by Lin et al. in 2006 which greatly reduces the time and power in searching. However, the fact that the behavior of an application varies from phase to phase has been shown in recent years. Tuning cache configuration to fit a target application in different phases gives a further improvement in power consumption. This work presents a mechanism which determines the optimal configurations in different phases during an execution process. By dividing an execution process into small time intervals and applying corresponding local optimal cache configuration for each interval on L1 instruction cache, this work shows that on average 91.6% energy saving is obtained by comparing with average energy consumption of all four-way set-associative caches in search space. On average 5.29% power reduction is achieved by comparing with energy consumption of benchmarks with their respective global optimal cache configurations.
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Jheng, Geng-Cyuan. "Real-time Reconfigurable Cache for Low-Power Embedded Systems." 2008. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0020-3107200814582400.
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Peng, Cheng-Hao, and 彭政豪. "Design of a Reconfigurable Cache for Low-Power Embedded Systems." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/74241048008722334994.
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碩士國立暨南國際大學
資訊工程學系
98
Modern embedded systems execute a small set of application or a single one repeatedly. Specializing cache configurations to a particular application is well-known to have great advantages on performance and energy saving. To reduce the searching for optimal cache configuration, a most-case optimal cache configuration searching algorithm was proposed which greatly reduces the times and power in searching. However, the fact that the behavior of an application varies from phase to phase has been shown in recent years. Tuning cache configuration to fit a specialized application in different phases gives a further improvement in power consumption. This work presents a mechanism which choices the optimal configurations in different phases during an execution process. By dividing an execution process into flexible time interval and applying corresponding local optimal cache configuration for each interval on L1 instruction cache. The experimental result shows that over 4.374% energy saving which compared with whole application divided into 64 intervals. On average 6.653% power reduction by dividing the whole application into flexible phases instead of slicing the entire application 1M instructions per phase.
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Hsu, Po-Hao, and 許博豪. "Reconfigurable Cache Memory Mechanism for Integral Image andIntegral Histogram Applications." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/58964530730016983247.
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碩士國立臺灣大學
電子工程學研究所
100
With the development of semiconductor technology, the capability of micro-processor doubles almost every 18 months, by the Moore''s Law. However, the speed of off-chip DRAM grows only 7% every year. There is a huge gap between the speed of CPU and DRAM. Cache memory is a high speed memory which can reduce the memory access latency between the processor and off-chip DRAM, and it usually occupies a large area of the whole system.However, for some operation with integral images and integral integral histograms, which are famous for getting an arbitrary-sized block summation and histogram in a constant speed and widely implemented in many applications, the read and write mechanisms of cache are not suitable for such algorithms with stream processing characteristic. With larger cache size, the cycle count can be further reduced. However, the analysis results show that there is a bottleneck of cache hit rate and the cycle count reduction meets a limitation. For the above reasons, in this thesis, a reconfigurable cache memory mechanism is proposed to support both general data access and stream processing. This proposed memory has two modes: normal cache mode and Row-Based Stream Processing (RBSP) mode, which is a specific mechanism for data accessing of integral images and integral histograms. The RBSP mode can reduce the cycle count because all the subsequent necessary data has been precisely prefetched with the basic accessing unit of an image row. Two integral image and integral histogram applications, SURF algorithm and center-surround histogram of salience map, are implemented to verify the proposed mechanism. Moreover, the data reuse scheme intra-filter-size sharing and inter-filter-size sharing between different filter sizes and diffierent filtering stripes are taken into consideration to further reduce the data access to the off-chip DRAM. A mapping algorithm is proposed to help the RBSP memory read and write the data, which is implemented in hardware and software versions. In addition, a method called Memory Dividing Technique (MDT) is also proposed to further reduce the word-length. The whole system is built in the Coware Platform Architect to verify our design. Our target image size is VGA 640 x 480 and the experimental results show that the proposed Reconfigurable RBSP memory can save 38.31% and 48.29% memory cycle count for these two applications compared to the traditional data cache in the same level of size. The hardware is implemented with Verilog-HDL and synthesized with Synopsys Design Compiler in TSMC 180nm technology. The total gate count of RBSP memory is 557.0K. The overhead of our proposed RBSP memory is very small, just 7.61% or 5.28% with hardware or software based implementation compared to the set associative cache.
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Yang, Yun-Chung, and 楊允中. "A Reconfigurable Cache for Efficient Usage of the Tag RAM Space." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/7ctc27.
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碩士國立中山大學
資訊工程學系研究所
102
In almost every typical SoCs (System-on-Chip) in modern days, the size of cache grows larger as new SoC fabrics enhanced to satisfy the variety of workloads. Cache occupies the whole chip area more than 60% in SoC. Most of the time, application does not use the entire cache space. Consequently, the underutilized cache space consume a certain power constantly without any contribution. Thus, some of the industry company in present day, starting to develop mechanisms to make the cache size reconfigurable. In recent work, an idea of scratchpad memory extends the turned-off part of cache space as local memory, also called SPM (scratchpad memory), which can benefit other activities to further increase the performance or enhance instruction delivery. However, SPM only uses the part of data RAMs, the tag RAMs part is still remaining un-used. In this work, we proposed an architecture that can exploit the SPM space by reusing tag RAMs in either instruction or data cache. Implementing the proposed architecture on an ARM compatible CPU data cache for case study. The experiment results show that we can reclaim 12.5% of memory space with 0.08% hardware overhead in the configuration of 4KB, 4 way-associative cache with 32 byte line size which is equivalent to ARM Cortex-A5.
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Kim, Yoonjin. "DESIGNING COST-EFFECTIVE COARSE-GRAINED RECONFIGURABLE ARCHITECTURE." 2009. http://hdl.handle.net/1969.1/ETD-TAMU-2009-05-649.
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Application-specific optimization of embedded systems becomes inevitable to satisfy the
market demand for designers to meet tighter constraints on cost, performance and power.
On the other hand, the flexibility of a system is also important to accommodate the short
time-to-market requirements for embedded systems. To compromise these incompatible
demands, coarse-grained reconfigurable architecture (CGRA) has emerged as a suitable
solution. A typical CGRA requires many processing elements (PEs) and a configuration
cache for reconfiguration of its PE array. However, such a structure consumes significant
area and power. Therefore, designing cost-effective CGRA has been a serious concern
for reliability of CGRA-based embedded systems.
As an effort to provide such cost-effective design, the first half of this work
focuses on reducing power in the configuration cache. For power saving in the configuration
cache, a low power reconfiguration technique is presented based on reusable context
pipelining achieved by merging the concept of context reuse into context pipelining.
In addition, we propose dynamic context compression capable of supporting only required
bits of the context words set to enable and the redundant bits set to disable. Finally, we provide dynamic context management capable of reducing reduce power consumption
in configuration cache by controlling a read/write operation of the redundant
context words
In the second part of this dissertation, we focus on designing a cost-effective PE array
to reduce area and power. For area and power saving in a PE array, we devise a costeffective
array fabric addresses novel rearrangement of processing elements and their
interconnection designs to reduce area and power consumption. In addition, hierarchical
reconfigurable computing arrays are proposed consisting of two reconfigurable computing
blocks with two types of communication structure together. The two computing
blocks have shared critical resources and such a sharing structure provides efficient
communication interface between them with reducing overall area.
Based on the proposed design approaches, a CGRA combining the multiple design
schemes is shown to verify the synergy effect of the integrated approach. Experimental
results show that the integrated approach reduces area by 23.07% and power by up to
72% when compared with the conventional CGRA.