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Journal articles on the topic 'Reconfigurable caches'

Author: Grafiati

Published: 4 June 2021

Last updated: 7 February 2022

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1

Begum, B. Shameedha, and N. Ramasubramanian. "Design of an Intelligent Data Cache with Replacement Policy." International Journal of Embedded and Real-Time Communication Systems 10, no. 2 (April 2019): 87–107. http://dx.doi.org/10.4018/ijertcs.2019040106.

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Embedded systems are designed for a variety of applications ranging from Hard Real Time applications to mobile computing, which demands various types of cache designs for better performance. Since real-time applications place stringent requirements on performance, the role of the cache subsystem assumes significance. Reconfigurable caches meet performance requirements under this context. Existing reconfigurable caches tend to use associativity and size for maximizing cache performance. This article proposes a novel approach of a reconfigurable and intelligent data cache (L1) based on replacement algorithms. An intelligent embedded data cache and a dynamic reconfigurable intelligent embedded data cache have been implemented using Verilog 2001 and tested for cache performance. Data collected by enabling the cache with two different replacement strategies have shown that the hit rate improves by 40% when compared to LRU and 21% when compared to MRU for sequential applications which will significantly improve performance of embedded real time application.

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2

Zhu, Wei, and Xiaoyang Zeng. "Decision Tree-Based Adaptive Reconfigurable Cache Scheme." Algorithms 14, no. 6 (June 1, 2021): 176. http://dx.doi.org/10.3390/a14060176.

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Applications have different preferences for caches, sometimes even within the different running phases. Caches with fixed parameters may compromise the performance of a system. To solve this problem, we propose a real-time adaptive reconfigurable cache based on the decision tree algorithm, which can optimize the average memory access time of cache without modifying the cache coherent protocol. By monitoring the application running state, the cache associativity is periodically tuned to the optimal cache associativity, which is determined by the decision tree model. This paper implements the proposed decision tree-based adaptive reconfigurable cache in the GEM5 simulator and designs the key modules using Verilog HDL. The simulation results show that the proposed decision tree-based adaptive reconfigurable cache reduces the average memory access time compared with other adaptive algorithms.

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Ho, Nam, Paul Kaufmann, and Marco Platzner. "Evolution of application-specific cache mappings." International Journal of Hybrid Intelligent Systems 16, no. 3 (September 28, 2020): 149–61. http://dx.doi.org/10.3233/his-200281.

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Reconfigurable caches offer an intriguing opportunity to tailor cache behavior to applications for better run-times and energy consumptions. While one may adapt structural cache parameters such as cache and block sizes, we adapt the memory-address-to-cache-index mapping function to the needs of an application. Using a LEON3 embedded multi-core processor with reconfigurable cache mappings, a metaheuristic search procedure, and MiBench applications, we show in this work how to accurately compare non-deterministic performances of applications and how to use this information to implement an optimization procedure that evolves application-specific cache mappings for the LEON3 multi-core processor.

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4

Yang, Xue-Jun, Jun-Jie Wu, Kun Zeng, and Yu-Hua Tang. "Managing Data-Objects in Dynamically Reconfigurable Caches." Journal of Computer Science and Technology 25, no. 2 (March 2010): 232–45. http://dx.doi.org/10.1007/s11390-010-9320-6.

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5

Ranganathan, Parthasarathy, Sarita Adve, and Norman P. Jouppi. "Reconfigurable caches and their application to media processing." ACM SIGARCH Computer Architecture News 28, no. 2 (May 2000): 214–24. http://dx.doi.org/10.1145/342001.339685.

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6

Huang, Yuanwen, and Prabhat Mishra. "Vulnerability-Aware Energy Optimization for Reconfigurable Caches in Multitasking Systems." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38, no. 5 (May 2019): 809–21. http://dx.doi.org/10.1109/tcad.2018.2834410.

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7

Bengueddach, A., B. Senouci, S. Niar, and B. Beldjilali. "Two-level caches tuning technique for energy consumption in reconfigurable embedded MPSoC." Journal of Systems Architecture 59, no. 8 (September 2013): 656–66. http://dx.doi.org/10.1016/j.sysarc.2013.05.018.

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8

Coole, James, and Greg Stitt. "Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures." International Journal of Reconfigurable Computing 2010 (2010): 1–16. http://dx.doi.org/10.1155/2010/652620.

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Field-programmable gate arrays (FPGAs) and other reconfigurable computing (RC) devices have been widely shown to have numerous advantages including order of magnitude performance and power improvements compared to microprocessors for some applications. Unfortunately, FPGA usage has largely been limited to applications exhibiting sequential memory access patterns, thereby prohibiting acceleration of important applications with irregular patterns (e.g., pointer-based data structures). In this paper, we present a design pattern for RC application development that serializes irregular data structure traversals online into a traversal cache, which allows the corresponding data to be efficiently streamed to the FPGA. The paper presents a generalized framework that benefits applications with repeated traversals, which we show can achieve between 7x and 29x speedup over pointer-based software. For applications without strictly repeated traversals, we present application-specialized extensions that benefit applications with highly similar traversals by exploiting similarity to improve memory bandwidth and execute multiple traversals in parallel. We show that these extensions can achieve a speedup between 11x and 70x on a Virtex4 LX100 for Barnes-Hut n-body simulation.

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9

Azad, Zahra, Hamed Farbeh, Amir Mahdi Hosseini Monazzah, and Seyed Ghassem Miremadi. "AWARE: Adaptive Way Allocation for Reconfigurable ECCs to Protect Write Errors in STT-RAM Caches." IEEE Transactions on Emerging Topics in Computing 7, no. 3 (July 1, 2019): 481–92. http://dx.doi.org/10.1109/tetc.2017.2701880.

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10

KIM, YOONJIN. "POWER-EFFICIENT CONFIGURATION CACHE STRUCTURE FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURE." Journal of Circuits, Systems and Computers 22, no. 03 (March 2013): 1350001. http://dx.doi.org/10.1142/s0218126613500011.

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Coarse-grained reconfigurable architectures (CGRA) require many processing elements (PEs) and a configuration memory unit (configuration cache) for reconfiguration of its PE array. Although this structure is meant for high performance and flexibility, it consumes significant power. Specially, power consumption by configuration cache is explicit overhead compared to other types of IP cores. Reducing power in configuration cache is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. In this paper, I propose a power-efficient configuration cache structure based on two design schemes — one is a reusable context pipelining (RCP) architecture to reduce power-overhead caused by reconfiguration and another is a dynamic context management strategy for power saving in configuration cache. This power-efficient approach works without degrading the performance and flexibility of CGRA. Experimental results show that the proposed approach saves 56.50%/86.84% of the average power in write/read-operation of configuration cache compared to the previous design.

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11

Omran, Safaa S., and Ibrahim A. Amory. "Comparative Study of Reconfigurable Cache Memory." Cihan University-Erbil Scientific Journal 2017, Special-1 (2017): 25–40. http://dx.doi.org/10.24086/cuesj.si.2017.n1a3.

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12

Huesung Kim, A. K. Somani, and A. Tyagi. "A reconfigurable multifunction computing cache architecture." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9, no. 4 (August 2001): 509–23. http://dx.doi.org/10.1109/92.931228.

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13

Son, Dong-Oh, Hong-Jun Choi, Jong-Myon Kim, and Cheol-Hong Kim. "Core-aware Cache Replacement Policy for Reconfigurable Last Level Cache." Journal of the Korea Society of Computer and Information 18, no. 11 (November 29, 2013): 1–12. http://dx.doi.org/10.9708/jksci.2013.18.11.001.

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14

Miyamoto, Naoto, Koji Kotani, and Tadahiro Ohmi. "A 3.7×3.7mm² 310.9mW 105.2msec 512×512-Pixel Phase-Only Correlation Processor." Journal of Robotics and Mechatronics 17, no. 4 (August 20, 2005): 395–400. http://dx.doi.org/10.20965/jrm.2005.p0395.

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The image recognition processor we propose implements the phase-only correlation (POC) algorithm. Its arithmetic-logic unit (ALU) is dynamically reconfigurable to any necessary circuitry for POC by itself. 2-stage cached-memory architecture (CMA) is developed so that high-radix batch processing is possible. By transforming the original POC algorithm into the optimum form for the dynamically reconfigurable ALU and 2-stage CMA, the proposed processor executes two-dimensional 512×512 pixel image recognition within 105.2msec and 310.9mW at 80MHz in an area 3.7×3.7mm². Its power consumption is over 11.3 times lower than that of previously reported work.

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15

ZHAO, Huan, Xiao-kun SU, and Ren-fa LI. "Dynamically reconfigurable cache scheme with lower-power." Journal of Computer Applications 29, no. 5 (July 27, 2009): 1446–48. http://dx.doi.org/10.3724/sp.j.1087.2009.01446.

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16

Sahoo, Debiprasanna, Swaraj Sha, Manoranjan Satpathy, and Madhu Mutyam. "ReDRAM: A Reconfigurable DRAM Cache for GPGPUs." IEEE Computer Architecture Letters 17, no. 2 (July 1, 2018): 213–16. http://dx.doi.org/10.1109/lca.2018.2865552.

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17

Hu, Sensen, and Jing Haung. "Exploring Adaptive Cache for Reconfigurable VLIW Processor." IEEE Access 7 (2019): 72634–46. http://dx.doi.org/10.1109/access.2019.2919589.

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18

Bossuet, Lilian, and El Mehdi Benhani. "Performing Cache Timing Attacks from the Reconfigurable Part of a Heterogeneous SoC—An Experimental Study." Applied Sciences 11, no. 14 (July 20, 2021): 6662. http://dx.doi.org/10.3390/app11146662.

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Cache attacks are widespread on microprocessors and multi-processor system-on-chips but have not yet spread to heterogeneous systems-on-chip such as SoC-FPGA that are found in increasing numbers of applications on servers or in the cloud. This type of SoC has two parts: a processing system that includes hard components and ARM processor cores and a programmable logic part that includes logic gates to be used to implement custom designs. The two parts communicate via memory-mapped interfaces. One of these interfaces is the accelerator coherency port that provides optional cache coherency between the two parts. In this paper, we discuss the practicability and potential threat of inside-SoC cache attacks using the cache coherency mechanism of a complex heterogeneous SoC-FPGA. We provide proof of two cache timing attacks Flush+Reload and Evict+Time when SoC-FPGA is targeted, and proof of hidden communication using a cache-based covert channel. The heterogeneous SoC-FPGA Xilinx Zynq-7010 is used as an experimental target.

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19

Hu, Sensen, Weixing Ji, and Yizhuo Wang. "Feedback cache mechanism for dynamically reconfigurable VLIW processors." Tsinghua Science and Technology 22, no. 3 (June 2017): 303–16. http://dx.doi.org/10.23919/tst.2017.7914202.

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20

Rama Sangireddy, H. Kim, and A. K. Somani. "Low-power high-performance reconfigurable computing cache architectures." IEEE Transactions on Computers 53, no. 10 (October 2004): 1274–90. http://dx.doi.org/10.1109/tc.2004.80.

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21

Putnam, Andrew, Susan Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, and Ralph Wittig. "Performance and power of cache-based reconfigurable computing." ACM SIGARCH Computer Architecture News 37, no. 3 (June 15, 2009): 395–405. http://dx.doi.org/10.1145/1555815.1555804.

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22

GUPTA, VIPUL, and EUGEN SCHENFELD. "TASK GRAPH PARTITIONING AND MAPPING IN A RECONFIGURABLE PARALLEL ARCHITECTURE." Parallel Processing Letters 05, no. 04 (December 1995): 563–74. http://dx.doi.org/10.1142/s0129626495000503.

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The goal of a task graph partitioning and mapping strategy is to reduce the communication overhead in a parallel application. Much of the past work in this area has been in the context of a static network topology. Here we show that the flexibility provided by a reconfigurable network can help lower the overhead and provide additional performance gains. However, since a reconfigurable network can be set to many different topologies, a new approach for the mapping problem must be formulated. Our research is based on the Interconnection Cached Network (ICN) a prototype of which is currently under development. The ICN is a reconfigurable network suited for exploiting switching locality in applications. "Switching locality" refers to the phenomenon in parallel applications of having each task mostly communicating (switching) between a small set of other tasks. As evidenced by the sparse nature of most task graphs, this phenomenon is common to many parallel applications. We describe the ICN architecture, the problem of mapping task graphs in the ICN, and the performance advantages of complementing clever partitioning strategies with topology reconfiguration.

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23

Kim, Yongjoo. "A Cache-based Reconfigurable Accelerator in Die-stacked DRAM." KIPS Transactions on Computer and Communication Systems 4, no. 2 (February 28, 2015): 41–46. http://dx.doi.org/10.3745/ktccs.2015.4.2.41.

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24

Chen, Gang, Biao Hu, Kai Huang, Alois Knoll, Kai Huang, Di Liu, Todor Stefanov, and Feng Li. "Reconfigurable cache for real-time MPSoCs: Scheduling and implementation." Microprocessors and Microsystems 42 (May 2016): 200–214. http://dx.doi.org/10.1016/j.micpro.2015.11.020.

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25

Jheng, Geng Cyuan, Dyi Rong Duh, and Cheng Nan Lai. "Real-time reconfigurable cache for low-power embedded systems." International Journal of Embedded Systems 4, no. 3/4 (2010): 235. http://dx.doi.org/10.1504/ijes.2010.039027.

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26

Quislant, Ricardo, Ezequiel Herruzo, Oscar Plata, JosÉ Ignacio Benavides, and Emilio L. Zapata. "Teaching the Cache Memory System Using a Reconfigurable Approach." IEEE Transactions on Education 51, no. 3 (August 2008): 336–41. http://dx.doi.org/10.1109/te.2008.916767.

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27

Se-Jeong Park, Jeong-Su Kim, Ramchan Woo, Se-Joong Lee, Kang-Min Lee, Tae-Hum Yang, Jin-Yong Jung, and Hoi-Jun Yoo. "A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth." IEEE Journal of Solid-State Circuits 37, no. 5 (May 2002): 612–23. http://dx.doi.org/10.1109/4.997855.

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28

Zhang, Qinchuan, Min Li, and Jun Jiang. "Study on data acquisition system based on reconfigurable cache technology." Review of Scientific Instruments 89, no. 3 (March 2018): 035110. http://dx.doi.org/10.1063/1.5016905.

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29

Tao, Jie, Marcel Kunze, Fabian Nowak, Rainer Buchty, and Wolfgang Karl. "Performance Advantage of Reconfigurable Cache Design on Multicore Processor Systems." International Journal of Parallel Programming 36, no. 3 (April 24, 2008): 347–60. http://dx.doi.org/10.1007/s10766-008-0075-4.

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30

Munaf, S., Dr A. Bharathi, and Dr A. N. Jayanthi. "Double Pumping Low Power Technique for Coarse - Grained Reconfigurable Architecture." International Journal of Electrical and Electronics Research 4, no. 1 (March 31, 2016): 10–15. http://dx.doi.org/10.37391/ijeer.040103.

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Coarse-grained reconfigurable architectures (CGRAs) require many processing elements (PEs) and a con- figuration memory unit (configuration cache) for reconfiguration of its PE array. Though this architecture is meant for high performance and flexibility. Power reduction is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. We propose a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) architecture to reduce power-overhead caused by reconfiguration. The power reduction can be achieved by using the characteristics like double pumping the data bus and an I/O buffer between the memory and the data bus of DDR SDRAM. All modules have been designed at behavioral level with VHDL coding and to Simulate in Xilinx ISE navigator.

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31

Shahid, Arsalan, Muhammad Yasir Qadri, Martin Fleury, Hira Waris, Ayaz Ahmad, and Nadia N. Qadri. "AC-DSE: Approximate Computing for the Design Space Exploration of Reconfigurable MPSoCs." Journal of Circuits, Systems and Computers 27, no. 09 (April 26, 2018): 1850145. http://dx.doi.org/10.1142/s0218126618501451.

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This paper concerns the design space exploration (DSE) of Reconfigurable Multi- Processor System-on- Chip (MPSoC) architectures. Reconfiguration allows users to allocate optimum system resources for a specific application in such a way to improve the energy and throughput balance. To achieve the best balance between power consumption and throughput performance for a particular application domain, typical design space parameters for a multi-processor architecture comprise the cache size, the number of processor cores and the operating frequency. The exploration of the design space has always been an offline technique, consuming a large amount of time. Hence, the exploration has been unsuitable for reconfigurable architectures, which require an early runtime decision. This paper presents Approximate Computing DSE (AC-DSE), an online technique for the DSE of MPSoCs by means of approximate computing. In AC-DSE, design space solutions are first obtained from a set of optimization algorithms, which in turn are used to train a neural network (NN). From then on, the NN can be used to rapidly return its own solutions in the form of design space parameters for a desired energy and throughput performance, without any further training.

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32

Wang, Chao, Peng Cao, Bo Liu, and Jun Yang. "Coarse-grained reconfigurable architecture with hierarchical context cache structure and management approach." IEICE Electronics Express 14, no. 6 (2017): 20170090. http://dx.doi.org/10.1587/elex.14.20170090.

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33

Balasubramani, S., and S. Ram Kumar. "A Comprehensive Survey of Reconfigurable Cache Memories for Energy Efficient Embedded Systems." Asian Journal of Research in Social Sciences and Humanities 7, no. 2 (2017): 393. http://dx.doi.org/10.5958/2249-7315.2017.00098.3.

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34

Jiang, Lin, Yang Liu, Rui Shan, Yani Feng, Yuan Zhang, and Xiaoyan Xie. "RDMM: Runtime dynamic migration mechanism of distributed cache for reconfigurable array processor." Integration 72 (May 2020): 82–91. http://dx.doi.org/10.1016/j.vlsi.2020.01.003.

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35

Chakraborty, Prasenjit, Preeti Ranjan Panda, and Sandeep Sen. "Partitioning and Data Mapping in Reconfigurable Cache and Scratchpad Memory--Based Architectures." ACM Transactions on Design Automation of Electronic Systems 22, no. 1 (December 28, 2016): 1–25. http://dx.doi.org/10.1145/2934680.

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36

Huang, Xiaoying, Zhichuan Guo, Mangu Song, and Yunfei Guo. "AccelSDP: A Reconfigurable Accelerator for Software Data Plane Based on FPGA SmartNIC." Electronics 10, no. 16 (August 11, 2021): 1927. http://dx.doi.org/10.3390/electronics10161927.

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Software-defined networking (SDN) has attracted much attention since it was proposed. The architecture of the SDN data plane is also evolving. To support the flexibility of the data plane, the software implementation approach is adopted. The software data plane of SDN is commonly implemented on a commercial off-the-shelf (COTS) server, executing an entire processing logic on a commodity CPU. With sharp increases in network capacity, CPU-based packet processing is overwhelmed. However, completely implementing the data plane on hardware weakens the flexibility. Therefore, hybrid implementation where a hardware device is adopted as the accelerator is proposed to balance the performance and flexibility. We propose an FPGA SmartNIC-based reconfigurable accelerator to offload some of the operation-intensive packet processing functions from the software data plane to reconfigurable hardware, thus improving the overall data plane performance while retaining flexibility. The accelerated software data plane has a powerful line-rate packet processing capability and flexible programmability at 100 Gbps and higher throughput. We offloaded a cached-rule table to the proposed accelerator and tested its performance with 100 GbE traffic. Compared with the software implementation, the evaluation result shows that the throughput can achieve a 600% improvement when processing small packets and a 100% increase in large packet processing, and the latency can be reduced by about 20× and 100×, respectively, when processing small packets and large packets.

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37

Salkhordeh, Reza, Shahriar Ebrahimi, and Hossein Asadi. "ReCA: An Efficient Reconfigurable Cache Architecture for Storage Systems with Online Workload Characterization." IEEE Transactions on Parallel and Distributed Systems 29, no. 7 (July 1, 2018): 1605–20. http://dx.doi.org/10.1109/tpds.2018.2796100.

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38

Huang, Ing-Jer, Chun-Hung Lai, Yun-Chung Yang, Hsu-Kang Dow, and Hung-Lun Chen. "A Reconfigurable Cache for Efficient Use of Tag RAM as Scratch-Pad Memory." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26, no. 4 (April 2018): 663–70. http://dx.doi.org/10.1109/tvlsi.2017.2785222.

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39

Jang, Jin-Ho, Sang-Won Ko, and Jung-Sun Kim. "A Reconfigurable, General-purpose DSM-CC Architecture and User Preference-based Cache Management Strategy." KIPS Transactions:PartC 17C, no. 1 (February 28, 2010): 89–98. http://dx.doi.org/10.3745/kipstc.2010.17c.1.089.

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40

Kim, Youngsik. "Reconfigurable Parallel Multi-way Associative Cache with Miss-fetch Merge for Anisotropic Texture Filtering." International Journal of Multimedia and Ubiquitous Engineering 10, no. 8 (October 31, 2015): 401–12. http://dx.doi.org/10.14257/ijmue.2015.10.8.39.

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41

Ramesh, Tirumale, and Khalid Abed. "Cost-efficient reconfigurable geometrical bus interconnection system for many-core platforms." International Journal of Reconfigurable and Embedded Systems (IJRES) 10, no. 2 (July 1, 2021): 77. http://dx.doi.org/10.11591/ijres.v10.i2.pp77-89.

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System-on-chip (SoC) embedded computing platforms can support a wide range of next generation embedded artificial intelligence and other computationally intensive applications. These platforms require cost effective interconnection network. Network-on-chip has been widely used today for on-chip interconnection. However, it is still considered expensive for large system sizes. As full bus-based interconnection has high number of bus connections, reduced bus connections might offer considerable implementation economies with relatively small design cost for field programmable gate arrays (FPGAs) based embedded platforms. In this paper, we propose a cost efficient generalized reconfigurable bus-based interconnection for many-core system with reduced number of bus connections. We generalize the system with b =min {n,m}/k number of interconnect buses in which where n is the number of processor cores, m is the number of memory-modules and k is the general bus reduction factor. We present four geometrical interconnect configurations and provide their characterization in terms of memory bandwidth, cost per bandwidth and bus fault tolerance for various system sizes. Our results show that these configurations provide reduced cost per bandwidth and can achieve higher system throughput with bus cache.

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42

Liu, Bing, Danyin Zou, Lei Feng, Shou Feng, Ping Fu, and Junbao Li. "An FPGA-Based CNN Accelerator Integrating Depthwise Separable Convolution." Electronics 8, no. 3 (March 3, 2019): 281. http://dx.doi.org/10.3390/electronics8030281.

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The Convolutional Neural Network (CNN) has been used in many fields and has achieved remarkable results, such as image classification, face detection, and speech recognition. Compared to GPU (graphics processing unit) and ASIC, a FPGA (field programmable gate array)-based CNN accelerator has great advantages due to its low power consumption and reconfigurable property. However, FPGA’s extremely limited resources and CNN’s huge amount of parameters and computational complexity pose great challenges to the design. Based on the ZYNQ heterogeneous platform and the coordination of resource and bandwidth issues with the roofline model, the CNN accelerator we designed can accelerate both standard convolution and depthwise separable convolution with a high hardware resource rate. The accelerator can handle network layers of different scales through parameter configuration and maximizes bandwidth and achieves full pipelined by using a data stream interface and ping-pong on-chip cache. The experimental results show that the accelerator designed in this paper can achieve 17.11GOPS for 32bit floating point when it can also accelerate depthwise separable convolution, which has obvious advantages compared with other designs.

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43

Yang, Chen, Leibo Liu, Kai Luo, Shouyi Yin, and Shaojun Wei. "CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays." IEEE Transactions on Parallel and Distributed Systems 28, no. 1 (January 1, 2017): 29–43. http://dx.doi.org/10.1109/tpds.2016.2554278.

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"An Enhanced Low Power Dual Data Injection Technique for Coarse - Grained Reconfigurable Architecture." International Journal of Innovative Technology and Exploring Engineering 9, no. 2 (December 10, 2019): 4421–24. http://dx.doi.org/10.35940/ijitee.b7299.129219.

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oarse-gr ained reconfigurable architectures (CGRA) having a well-organized, more efficient configurable array of processing unit and high speed cache unit. The processing unit performs required arithmetic and logic operations. Now a day’s video processing applications power consumption plays an important role. We propose Double Data Rate Synchronous Memory architecture can address and reduce the power consumption caused by reconfiguration. An input data bits are injecting on the data bus in the interval of low to high and high low clock period. All modules have been designed and implemented in vertex using behavioral level with VHDL coding and to Simulate in Xilinx ISE navigator.

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45

Ebrahimi, Shahriar, Reza Salkhordeh, Seyed Ali Osia, Ali Taheri, Hamid R. Rabiee, and Hossein Asadi. "RC-RNN: Reconfigurable Cache Architecture for Storage Systems Using Recurrent Neural Networks." IEEE Transactions on Emerging Topics in Computing, 2021, 1. http://dx.doi.org/10.1109/tetc.2021.3102041.

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