Journal articles on the topic 'Reconfigurable caches'
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Begum, B. Shameedha, and N. Ramasubramanian. "Design of an Intelligent Data Cache with Replacement Policy." International Journal of Embedded and Real-Time Communication Systems 10, no. 2 (April 2019): 87–107. http://dx.doi.org/10.4018/ijertcs.2019040106.
Full textZhu, Wei, and Xiaoyang Zeng. "Decision Tree-Based Adaptive Reconfigurable Cache Scheme." Algorithms 14, no. 6 (June 1, 2021): 176. http://dx.doi.org/10.3390/a14060176.
Full textHo, Nam, Paul Kaufmann, and Marco Platzner. "Evolution of application-specific cache mappings." International Journal of Hybrid Intelligent Systems 16, no. 3 (September 28, 2020): 149–61. http://dx.doi.org/10.3233/his-200281.
Full textYang, Xue-Jun, Jun-Jie Wu, Kun Zeng, and Yu-Hua Tang. "Managing Data-Objects in Dynamically Reconfigurable Caches." Journal of Computer Science and Technology 25, no. 2 (March 2010): 232–45. http://dx.doi.org/10.1007/s11390-010-9320-6.
Full textRanganathan, Parthasarathy, Sarita Adve, and Norman P. Jouppi. "Reconfigurable caches and their application to media processing." ACM SIGARCH Computer Architecture News 28, no. 2 (May 2000): 214–24. http://dx.doi.org/10.1145/342001.339685.
Full textHuang, Yuanwen, and Prabhat Mishra. "Vulnerability-Aware Energy Optimization for Reconfigurable Caches in Multitasking Systems." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38, no. 5 (May 2019): 809–21. http://dx.doi.org/10.1109/tcad.2018.2834410.
Full textBengueddach, A., B. Senouci, S. Niar, and B. Beldjilali. "Two-level caches tuning technique for energy consumption in reconfigurable embedded MPSoC." Journal of Systems Architecture 59, no. 8 (September 2013): 656–66. http://dx.doi.org/10.1016/j.sysarc.2013.05.018.
Full textCoole, James, and Greg Stitt. "Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures." International Journal of Reconfigurable Computing 2010 (2010): 1–16. http://dx.doi.org/10.1155/2010/652620.
Full textAzad, Zahra, Hamed Farbeh, Amir Mahdi Hosseini Monazzah, and Seyed Ghassem Miremadi. "AWARE: Adaptive Way Allocation for Reconfigurable ECCs to Protect Write Errors in STT-RAM Caches." IEEE Transactions on Emerging Topics in Computing 7, no. 3 (July 1, 2019): 481–92. http://dx.doi.org/10.1109/tetc.2017.2701880.
Full textKIM, YOONJIN. "POWER-EFFICIENT CONFIGURATION CACHE STRUCTURE FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURE." Journal of Circuits, Systems and Computers 22, no. 03 (March 2013): 1350001. http://dx.doi.org/10.1142/s0218126613500011.
Full textOmran, Safaa S., and Ibrahim A. Amory. "Comparative Study of Reconfigurable Cache Memory." Cihan University-Erbil Scientific Journal 2017, Special-1 (2017): 25–40. http://dx.doi.org/10.24086/cuesj.si.2017.n1a3.
Full textHuesung Kim, A. K. Somani, and A. Tyagi. "A reconfigurable multifunction computing cache architecture." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9, no. 4 (August 2001): 509–23. http://dx.doi.org/10.1109/92.931228.
Full textSon, Dong-Oh, Hong-Jun Choi, Jong-Myon Kim, and Cheol-Hong Kim. "Core-aware Cache Replacement Policy for Reconfigurable Last Level Cache." Journal of the Korea Society of Computer and Information 18, no. 11 (November 29, 2013): 1–12. http://dx.doi.org/10.9708/jksci.2013.18.11.001.
Full textMiyamoto, Naoto, Koji Kotani, and Tadahiro Ohmi. "A 3.7×3.7mm² 310.9mW 105.2msec 512×512-Pixel Phase-Only Correlation Processor." Journal of Robotics and Mechatronics 17, no. 4 (August 20, 2005): 395–400. http://dx.doi.org/10.20965/jrm.2005.p0395.
Full textZHAO, Huan, Xiao-kun SU, and Ren-fa LI. "Dynamically reconfigurable cache scheme with lower-power." Journal of Computer Applications 29, no. 5 (July 27, 2009): 1446–48. http://dx.doi.org/10.3724/sp.j.1087.2009.01446.
Full textSahoo, Debiprasanna, Swaraj Sha, Manoranjan Satpathy, and Madhu Mutyam. "ReDRAM: A Reconfigurable DRAM Cache for GPGPUs." IEEE Computer Architecture Letters 17, no. 2 (July 1, 2018): 213–16. http://dx.doi.org/10.1109/lca.2018.2865552.
Full textHu, Sensen, and Jing Haung. "Exploring Adaptive Cache for Reconfigurable VLIW Processor." IEEE Access 7 (2019): 72634–46. http://dx.doi.org/10.1109/access.2019.2919589.
Full textBossuet, Lilian, and El Mehdi Benhani. "Performing Cache Timing Attacks from the Reconfigurable Part of a Heterogeneous SoC—An Experimental Study." Applied Sciences 11, no. 14 (July 20, 2021): 6662. http://dx.doi.org/10.3390/app11146662.
Full textHu, Sensen, Weixing Ji, and Yizhuo Wang. "Feedback cache mechanism for dynamically reconfigurable VLIW processors." Tsinghua Science and Technology 22, no. 3 (June 2017): 303–16. http://dx.doi.org/10.23919/tst.2017.7914202.
Full textRama Sangireddy, H. Kim, and A. K. Somani. "Low-power high-performance reconfigurable computing cache architectures." IEEE Transactions on Computers 53, no. 10 (October 2004): 1274–90. http://dx.doi.org/10.1109/tc.2004.80.
Full textPutnam, Andrew, Susan Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, and Ralph Wittig. "Performance and power of cache-based reconfigurable computing." ACM SIGARCH Computer Architecture News 37, no. 3 (June 15, 2009): 395–405. http://dx.doi.org/10.1145/1555815.1555804.
Full textGUPTA, VIPUL, and EUGEN SCHENFELD. "TASK GRAPH PARTITIONING AND MAPPING IN A RECONFIGURABLE PARALLEL ARCHITECTURE." Parallel Processing Letters 05, no. 04 (December 1995): 563–74. http://dx.doi.org/10.1142/s0129626495000503.
Full textKim, Yongjoo. "A Cache-based Reconfigurable Accelerator in Die-stacked DRAM." KIPS Transactions on Computer and Communication Systems 4, no. 2 (February 28, 2015): 41–46. http://dx.doi.org/10.3745/ktccs.2015.4.2.41.
Full textChen, Gang, Biao Hu, Kai Huang, Alois Knoll, Kai Huang, Di Liu, Todor Stefanov, and Feng Li. "Reconfigurable cache for real-time MPSoCs: Scheduling and implementation." Microprocessors and Microsystems 42 (May 2016): 200–214. http://dx.doi.org/10.1016/j.micpro.2015.11.020.
Full textJheng, Geng Cyuan, Dyi Rong Duh, and Cheng Nan Lai. "Real-time reconfigurable cache for low-power embedded systems." International Journal of Embedded Systems 4, no. 3/4 (2010): 235. http://dx.doi.org/10.1504/ijes.2010.039027.
Full textQuislant, Ricardo, Ezequiel Herruzo, Oscar Plata, JosÉ Ignacio Benavides, and Emilio L. Zapata. "Teaching the Cache Memory System Using a Reconfigurable Approach." IEEE Transactions on Education 51, no. 3 (August 2008): 336–41. http://dx.doi.org/10.1109/te.2008.916767.
Full textSe-Jeong Park, Jeong-Su Kim, Ramchan Woo, Se-Joong Lee, Kang-Min Lee, Tae-Hum Yang, Jin-Yong Jung, and Hoi-Jun Yoo. "A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth." IEEE Journal of Solid-State Circuits 37, no. 5 (May 2002): 612–23. http://dx.doi.org/10.1109/4.997855.
Full textZhang, Qinchuan, Min Li, and Jun Jiang. "Study on data acquisition system based on reconfigurable cache technology." Review of Scientific Instruments 89, no. 3 (March 2018): 035110. http://dx.doi.org/10.1063/1.5016905.
Full textTao, Jie, Marcel Kunze, Fabian Nowak, Rainer Buchty, and Wolfgang Karl. "Performance Advantage of Reconfigurable Cache Design on Multicore Processor Systems." International Journal of Parallel Programming 36, no. 3 (April 24, 2008): 347–60. http://dx.doi.org/10.1007/s10766-008-0075-4.
Full textMunaf, S., Dr A. Bharathi, and Dr A. N. Jayanthi. "Double Pumping Low Power Technique for Coarse - Grained Reconfigurable Architecture." International Journal of Electrical and Electronics Research 4, no. 1 (March 31, 2016): 10–15. http://dx.doi.org/10.37391/ijeer.040103.
Full textShahid, Arsalan, Muhammad Yasir Qadri, Martin Fleury, Hira Waris, Ayaz Ahmad, and Nadia N. Qadri. "AC-DSE: Approximate Computing for the Design Space Exploration of Reconfigurable MPSoCs." Journal of Circuits, Systems and Computers 27, no. 09 (April 26, 2018): 1850145. http://dx.doi.org/10.1142/s0218126618501451.
Full textWang, Chao, Peng Cao, Bo Liu, and Jun Yang. "Coarse-grained reconfigurable architecture with hierarchical context cache structure and management approach." IEICE Electronics Express 14, no. 6 (2017): 20170090. http://dx.doi.org/10.1587/elex.14.20170090.
Full textBalasubramani, S., and S. Ram Kumar. "A Comprehensive Survey of Reconfigurable Cache Memories for Energy Efficient Embedded Systems." Asian Journal of Research in Social Sciences and Humanities 7, no. 2 (2017): 393. http://dx.doi.org/10.5958/2249-7315.2017.00098.3.
Full textJiang, Lin, Yang Liu, Rui Shan, Yani Feng, Yuan Zhang, and Xiaoyan Xie. "RDMM: Runtime dynamic migration mechanism of distributed cache for reconfigurable array processor." Integration 72 (May 2020): 82–91. http://dx.doi.org/10.1016/j.vlsi.2020.01.003.
Full textChakraborty, Prasenjit, Preeti Ranjan Panda, and Sandeep Sen. "Partitioning and Data Mapping in Reconfigurable Cache and Scratchpad Memory--Based Architectures." ACM Transactions on Design Automation of Electronic Systems 22, no. 1 (December 28, 2016): 1–25. http://dx.doi.org/10.1145/2934680.
Full textHuang, Xiaoying, Zhichuan Guo, Mangu Song, and Yunfei Guo. "AccelSDP: A Reconfigurable Accelerator for Software Data Plane Based on FPGA SmartNIC." Electronics 10, no. 16 (August 11, 2021): 1927. http://dx.doi.org/10.3390/electronics10161927.
Full textSalkhordeh, Reza, Shahriar Ebrahimi, and Hossein Asadi. "ReCA: An Efficient Reconfigurable Cache Architecture for Storage Systems with Online Workload Characterization." IEEE Transactions on Parallel and Distributed Systems 29, no. 7 (July 1, 2018): 1605–20. http://dx.doi.org/10.1109/tpds.2018.2796100.
Full textHuang, Ing-Jer, Chun-Hung Lai, Yun-Chung Yang, Hsu-Kang Dow, and Hung-Lun Chen. "A Reconfigurable Cache for Efficient Use of Tag RAM as Scratch-Pad Memory." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26, no. 4 (April 2018): 663–70. http://dx.doi.org/10.1109/tvlsi.2017.2785222.
Full textJang, Jin-Ho, Sang-Won Ko, and Jung-Sun Kim. "A Reconfigurable, General-purpose DSM-CC Architecture and User Preference-based Cache Management Strategy." KIPS Transactions:PartC 17C, no. 1 (February 28, 2010): 89–98. http://dx.doi.org/10.3745/kipstc.2010.17c.1.089.
Full textKim, Youngsik. "Reconfigurable Parallel Multi-way Associative Cache with Miss-fetch Merge for Anisotropic Texture Filtering." International Journal of Multimedia and Ubiquitous Engineering 10, no. 8 (October 31, 2015): 401–12. http://dx.doi.org/10.14257/ijmue.2015.10.8.39.
Full textRamesh, Tirumale, and Khalid Abed. "Cost-efficient reconfigurable geometrical bus interconnection system for many-core platforms." International Journal of Reconfigurable and Embedded Systems (IJRES) 10, no. 2 (July 1, 2021): 77. http://dx.doi.org/10.11591/ijres.v10.i2.pp77-89.
Full textLiu, Bing, Danyin Zou, Lei Feng, Shou Feng, Ping Fu, and Junbao Li. "An FPGA-Based CNN Accelerator Integrating Depthwise Separable Convolution." Electronics 8, no. 3 (March 3, 2019): 281. http://dx.doi.org/10.3390/electronics8030281.
Full textYang, Chen, Leibo Liu, Kai Luo, Shouyi Yin, and Shaojun Wei. "CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays." IEEE Transactions on Parallel and Distributed Systems 28, no. 1 (January 1, 2017): 29–43. http://dx.doi.org/10.1109/tpds.2016.2554278.
Full text"An Enhanced Low Power Dual Data Injection Technique for Coarse - Grained Reconfigurable Architecture." International Journal of Innovative Technology and Exploring Engineering 9, no. 2 (December 10, 2019): 4421–24. http://dx.doi.org/10.35940/ijitee.b7299.129219.
Full textEbrahimi, Shahriar, Reza Salkhordeh, Seyed Ali Osia, Ali Taheri, Hamid R. Rabiee, and Hossein Asadi. "RC-RNN: Reconfigurable Cache Architecture for Storage Systems Using Recurrent Neural Networks." IEEE Transactions on Emerging Topics in Computing, 2021, 1. http://dx.doi.org/10.1109/tetc.2021.3102041.
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