Academic literature on the topic 'Reconfigurable Multi-Core architecture'
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Journal articles on the topic "Reconfigurable Multi-Core architecture"
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Yan, Like, Binbin Wu, Yuan Wen, Shaobin Zhang, and Tianzhou Chen. "A reconfigurable processor architecture combining multi-core and reconfigurable processing units." Telecommunication Systems 55, no. 3 (August 10, 2013): 333–44. http://dx.doi.org/10.1007/s11235-013-9791-1.
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Saeed, Ahmed, Ali Ahmadinia, and Mike Just. "Secure On-Chip Communication Architecture for Reconfigurable Multi-Core Systems." Journal of Circuits, Systems and Computers 25, no. 08 (May 17, 2016): 1650089. http://dx.doi.org/10.1142/s0218126616500894.
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Security is becoming the primary concern in today’s embedded systems. Network-on-chip (NoC)-based communication architectures have emerged as an alternative to shared bus mechanism in multi-core system-on-chip (SoC) devices and the increasing number and functionality of processing cores have made such systems vulnerable to security attacks. In this paper, a secure communication architecture has been presented by designing an identity and address verification (IAV) security module, which is embedded in each router at the communication level. IAV module verifies the identity and address range to be accessed by incoming and outgoing data packets in an NoC-based multi-core shared memory architecture. Our IAV module is implemented on an FPGA device for functional verification and evaluated in terms of its area and power consumption overhead. For FPGA-based systems, the IAV module can be reconfigured at run-time through partial reconfiguration. In addition, a cycle-accurate simulation is carried out to analyze the performance and total network energy consumption overhead for different network configurations. The proposed IAV module has presented reduced area and power consumption overhead when compared with similar existing solutions.
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Dudhane, Tanaji M., and T. Ravi. "Design and Implementation of Extended 16 Bit Co-Operative Arithmetic and Logic Unit (CALU) for 16 Bit Instructions." Journal of Low Power Electronics 15, no. 3 (September 1, 2019): 309–14. http://dx.doi.org/10.1166/jolpe.2019.1613.
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CPU architecture has experienced great innovation in its architecture, from 8 bit to 64 bit, CISC to RISC, Single core to multi-core and single pipelined logic to deep multi-pipelined system. Today in an era of 64 bit architectures, 8 bits are still very relevant and has not lost its position and being used in many applications. Hence this research work deals with 8 bit CPU architecture and its features enhancement to make the 8 bit case very relevant in an era of 64 bit. The co-operative ALU, as name suggests, works in tandem with existing ALU and performs 16 bits operations. The specially designed instructions shares knowledge and efficiently handles existing ALU and Co-operative ALU to perform 8 bits and 16 bits operations. The Co-operative ALU is integrated with the 2 stage pipelined 8-bit RISC architecture ensuring that existing architecture is kept intact by way of applying new functionality in the form of an extension. The reconfigurable platform software tools are used for functionality verification and final deployment is done using reconfigurable platform hardware tools.
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Sakthivel, Erulappan, Veluchamy Malathi, and Muruganantham Arunraja. "A New Simulator Based on Multi Core Processor with Improved Sense Amplifier." Journal of Circuits, Systems and Computers 24, no. 09 (August 27, 2015): 1550141. http://dx.doi.org/10.1142/s0218126615501418.
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In recent days, network-on-chip (NoC) researchers focus mainly on the area reduction and low power consumption both in architectural and algorithmic approach. To achieve low power and high performance in NoC architecture, sense amplifiers (SAs) introduced which can consume less power under various traffic conditions. In order to analyze the performance of architectural NoC design before fabrication level, the new simulator is developed based on multi core processor with improved sense amplifier (MCPSA) in this work. The MCPSA simulator provides user, the flexibility of incorporating various traffic configurations and routing algorithm with user reconfigurable option. In addition, the different SA model can be put into the simulation in plug and play manner for evaluation. The NoC case studies are presented to demonstrate the NoC architecture with double tail sense amplifier (DTSA) and modified-DTSA (M-DTSA) design. The performance metric such as delay, data rate and power consumption is evaluated. The main idea of this new simulator is to interface multisim environment (MSE) into a NoC environment for validating any DTSA.
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Brandalero, Marcelo, Thiago Dadalt Souto, Luigi Carro, and Antonio Carlos Schneider Beck. "Predicting performance in multi-core systems with shared reconfigurable accelerators." Journal of Systems Architecture 98 (September 2019): 201–13. http://dx.doi.org/10.1016/j.sysarc.2019.07.010.
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Kim, Yoonjin, Hyejin Joo, and Sohyun Yoon. "Inter‐coarse‐grained reconfigurable architecture reconfiguration technique for efficient pipelining of kernel‐stream on coarse‐grained reconfigurable architecture‐based multi‐core architecture." IET Circuits, Devices & Systems 10, no. 4 (July 2016): 251–65. http://dx.doi.org/10.1049/iet-cds.2015.0047.
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Venkatavara Prasad, D., and Maddineni Deepthi. "Reconfigurable Architecture for Minimizing the Network Delays in the Multi-core Systems." Research Journal of Applied Sciences, Engineering and Technology 9, no. 8 (March 15, 2015): 637–44. http://dx.doi.org/10.19026/rjaset.9.1448.
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Garzia, Fabio, Roberto Airoldi, and Jari Nurmi. "Implementation of FFT on General-Purpose Architectures for FPGA." International Journal of Embedded and Real-Time Communication Systems 1, no. 3 (July 2010): 24–43. http://dx.doi.org/10.4018/jertcs.2010070102.
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This paper describes two general-purpose architectures targeted to Field Programmable Gate Array (FPGA) implementation. The first architecture is based on the coupling of a coarse-grain reconfigurable array with a general-purpose processor core. The second architecture is a homogeneous multi-processor system-on-chip (MP-SoC). Both architectures have been mapped onto two different Altera FPGA devices, a StratixII and a StratixIV. Although mapping onto the StratixIV results in higher operating frequencies, the capabilities of the device are not fully exploited. The implementation of a FFT on the two platforms shows a considerable speed-up in comparison with a single-processor reference architecture. The speed-up is higher in the reconfigurable solution but the MP-SoC provides an easier programming interface that is completely based on C language. The authors’ approach proves that implementing a programmable architecture on FPGA and then programming it using a high-level software language is a viable alternative to designing a dedicated hardware block with a hardware description language (HDL) and mapping it on FPGA.
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Lu, Chun Hsien, Chih Sheng Lin, Hung Lin Chao, Jih g. Shen, and Pao Ann Hsiung. "Reconfigurable multi-core architecture - a plausible solution to the von Neumann performance bottleneck." International Journal of Adaptive and Innovative Systems 2, no. 3 (2015): 217. http://dx.doi.org/10.1504/ijais.2015.074399.
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R, Maheswari, Pattabiraman V, and Sharmila P. "RECONFIGURABLE FPGA BASED SOFT-CORE PROCESSOR FOR SIMD APPLICATIONS." Asian Journal of Pharmaceutical and Clinical Research 10, no. 13 (April 1, 2017): 180. http://dx.doi.org/10.22159/ajpcr.2017.v10s1.19632.
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Objective: The prospective need of SIMD (Single Instruction and Multiple Data) applications like video and image processing in single system requires greater flexibility in computation to deliver high quality real time data. This paper performs an analysis of FPGA (Field Programmable Gate Array) based high performance Reconfigurable OpenRISC1200 (ROR) soft-core processor for SIMD.Methods: The ROR1200 ensures performance improvement by data level parallelism executing SIMD instruction simultaneously in HPRC (High Performance Reconfigurable Computing) at reduced resource utilization through RRF (Reconfigurable Register File) with multiple core functionalities. This work aims at analyzing the functionality of the reconfigurable architecture, by illustrating the implementation of two different image processing operations such as image convolution and image quality improvement. The MAC (Multiply-Accumulate) unit of ROR1200 used to perform image convolution and execution unit with HPRC is used for image quality improvement.Result: With parallel execution in multi-core, the proposed processor improves image quality by doubling the frame rate up-to 60 fps (frames per second) with peak power consumption of 400mWatt. Thus the processor gives a significant computational cost of 12ms with a refresh rate of 60Hz and 1.29ns of MAC critical path delay.Conclusion:This FPGA based processor becomes a feasible solution for portable embedded SIMD based applications which need high performance at reduced power consumptions
Dissertations / Theses on the topic "Reconfigurable Multi-Core architecture"
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Das, Satyajit. "Architecture and Programming Model Support for Reconfigurable Accelerators in Multi-Core Embedded Systems." Thesis, Lorient, 2018. http://www.theses.fr/2018LORIS490/document.
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La complexité des systèmes embarqués et des applications impose des besoins croissants en puissance de calcul et de consommation énergétique. Couplé au rendement en baisse de la technologie, le monde académique et industriel est toujours en quête d'accélérateurs matériels efficaces en énergie. L'inconvénient d'un accélérateur matériel est qu'il est non programmable, le rendant ainsi dédié à une fonction particulière. La multiplication des accélérateurs dédiés dans les systèmes sur puce conduit à une faible efficacité en surface et pose des problèmes de passage à l'échelle et d'interconnexion. Les accélérateurs programmables fournissent le bon compromis efficacité et flexibilité. Les architectures reconfigurables à gros grains (CGRA) sont composées d'éléments de calcul au niveau mot et constituent un choix prometteur d'accélérateurs programmables. Cette thèse propose d'exploiter le potentiel des architectures reconfigurables à gros grains et de pousser le matériel aux limites énergétiques dans un flot de conception complet. Les contributions de cette thèse sont une architecture de type CGRA, appelé IPA pour Integrated Programmable Array, sa mise en œuvre et son intégration dans un système sur puce, avec le flot de compilation associé qui permet d'exploiter les caractéristiques uniques du nouveau composant, notamment sa capacité à supporter du flot de contrôle. L'efficacité de l'approche est éprouvée à travers le déploiement de plusieurs applications de traitement intensif. L'accélérateur proposé est enfin intégré à PULP, a Parallel Ultra-Low-Power Processing-Platform, pour explorer le bénéfice de ce genre de plate-forme hétérogène ultra basse consommationEmerging trends in embedded systems and applications need high throughput and low power consumption. Due to the increasing demand for low power computing and diminishing returns from technology scaling, industry and academia are turning with renewed interest toward energy efficient hardware accelerators. The main drawback of hardware accelerators is that they are not programmable. Therefore, their utilization can be low is they perform one specific function and increasing the number of the accelerators in a system on chip (SoC) causes scalability issues. Programmable accelerators provide flexibility and solve the scalability issues. Coarse-Grained Reconfigurable Array (CGRA) architecture consisting of several processing elements with word level granularity is a promising choice for programmable accelerator. Inspired by the promising characteristics of programmable accelerators, potentials of CGRAs in near threshold computing platforms are studied and an end-to-end CGRA research framework is developed in this thesis. The major contributions of this framework are: CGRA design, implementation, integration in a computing system, and compilation for CGRA. First, the design and implementation of a CGRA named Integrated Programmable Array (IPA) is presented. Next, the problem of mapping applications with control and data flow onto CGRA is formulated. From this formulation, several efficient algorithms are developed using internal resources of a CGRA, with a vision for low power acceleration. The algorithms are integrated into an automated compilation flow. Finally, the IPA accelerator is augmented in PULP - a Parallel Ultra-Low-Power Processing-Platform to explore heterogeneous computing
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Brière, Alexandre. "Modélisation système d'une architecture d'interconnexion RF reconfigurable pour les many-cœurs." Thesis, Paris 6, 2017. http://www.theses.fr/2017PA066296/document.
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La multiplication du nombre de cœurs de calcul présents sur une même puce va depair avec une augmentation des besoins en communication. De plus, la variété des applications s’exécutant sur la puce provoque une hétérogénéité spatiale et temporelle des communications. C’est pour répondre à ces problématiques que nous pré-sentons dans ce manuscrit un réseau d’interconnexion sur puce dynamiquement reconfigurable utilisant la Radio Fréquence (RF). L’utilisation de la RF permet de disposer d’une bande passante plus importante tout en minimisant la latence. La possibilité de reconfigurer dynamiquement le réseau permet d’adapter cette puce many-cœur à la variabilité des applications et des communications. Nous présentons les raisons du choix de la RF par rapport aux autres nouvelles technologies du domaine que sont l’optique et la 3D, l’architecture détaillée de ce réseau et d’une puce le mettant en œuvre ainsi que l’évaluation de sa faisabilité et de ses performances. Durant la phase d’évaluation nous avons pu montrer que pour un Chip Multiprocessor (CMP) de 1 024 tuiles, notre solution permettait un gain en performance de 13 %. Un des avantages de ce réseau d’interconnexion RF est la possibilité de faire du broadcast sans surcoût par rapport aux communications point-à-point,ouvrant ainsi de nouvelles perspectives en termes de gestion de la cohérence mémoire notammentThe growing number of cores in a single chip goes along with an increase in com-munications. The variety of applications running on the chip causes spatial andtemporal heterogeneity of communications. To address these issues, we presentin this thesis a dynamically reconfigurable interconnect based on Radio Frequency(RF) for intra chip communications. The use of RF allows to increase the bandwidthwhile minimizing the latency. Dynamic reconfiguration of the interconnect allowsto handle the heterogeneity of communications. We present the rationale for choos-ing RF over optics and 3D, the detailed architecture of the network and the chipimplementing it, the evaluation of its feasibility and its performances. During theevaluation phase we were able to show that for a CMP of 1 024 tiles, our solutionallowed a performance gain of 13 %. One advantage of this RF interconnect is theability to broadcast without additional cost compared to point-to-point communi-cations, opening new perspectives in terms of cache coherence
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Mansouri, Imen. "Contrôle distribué pour les systèmes multi-cœurs auto-adaptatifs." Thesis, Montpellier 2, 2011. http://www.theses.fr/2011MON20087.
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Les architectures régulières intégrant plusieurs cœurs de traitement sont davantage utilisées dans les systèmes embarqués. Dans cette thèse, on s'intéresse aux mécanismes d'optimisation d'énergie dans des architectures avec une dimension étendue; pour faire face aux problèmes de variabilité technologique et aux changements du contexte applicatif, le processus d'optimisation se déroule en temps réel. Des capteurs in-situ détectent le degré de dégradation du circuit. Quant a la variabilité applicative, des moniteurs d'activité sont insérés sur un niveau architectural pour estimer la charge de travail engendrée par l'application en cours et la consommation qui en découle. Nous avons développé une méthode systématique pour l'intégration de ces capteurs avec un moindre coût en surface. Leurs sorties alimentent un processus d'optimisation basé sur la théorie de consensus et dupliqué dans chaque cœur. Ce contrôle vise à fixer la meilleure configuration locale à chaque cœur permettant d'optimiser la consommation globale du système tout en respectant les contraintes temps réel de l'application en cours. Ce schéma opère d'une manière complètement distribuée afin de garantir la scalabilité de notre solution, et donc sa faisabilité, compte tenu de la complexité des circuits actuels et futursRegular architectures embedding several processing elements are increasingly used in embedded systems. They require careful design to avoid high power consumption and to improve their flexibility. This thesis work deals with optimization mechanisms of large scale architectures; to meet variability issues, optimization is processed at run-time. The target design implements in-situ features to collect physical information about its yield and to monitor application workload and generated consumption. As for workload monitoring, we use activity counters connected at architecture level to a set of critical signals. We developed an automated method to optimally place these features with a minimal area overhead. The collected information are used further jointly with a power model to estimate the dissipated power and then driven appropriate optimization process. Optimal frequency for each core is set by means of a distributed controller based on consensus theory. The resulting settings aim to reduce the whole system power while fulfilling application constraints. The scheme needs to be fully distributed to garantee the control scalability, and so feasibility, as the number of cores scales
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Grand, Michaël. "Conception d’un crypto-système reconfigurable pour la radio logicielle sécurisée." Thesis, Bordeaux 1, 2011. http://www.theses.fr/2011BOR14388/document.
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Les travaux de recherche détaillés dans ce document portent sur la conception et l’implantation d’un composant matériel jouant le rôle du sous-système cryptographique d’une radio logicielle sécurisée.A partir du début des années 90, les systèmes radios ont peu à peu évolué de la radio classique vers la radio logicielle. Le développement de la radio logicielle a permis l’intégration d’un nombre toujours plus grand de standards de communication sur une même plateforme matérielle. La réalisation concrète d’une radio logicielle sécurisée amène son concepteur à faire face à de nombreuses problématiques qui peuvent se résumer par la question suivante : Comment implanter un maximum de standards de communication sur une même plateforme matérielle et logicielle ? Ce document s’intéresse plus particulièrement à l’implantation des standards cryptographiques destinés à protéger les radiocommunications.Idéalement, la solution apportée à ce problème repose exclusivement sur l’utilisation de processeurs numériques. Cependant, les algorithmes cryptographiques nécessitent le plus souvent une puissance de calcul telle que leur implantation sous forme logicielle n’est pas envisageable. Il s’ensuit qu’une radio logicielle doit parfois intégrer des composants matériels dédiés dont l'utilisation entre en conflit avec la propriété de flexibilité propre aux radios logicielles.Or depuis quelques années, le développement de la technologie FPGA a changé la donne. En effet, les derniers FPGA embarquent un nombre de ressources logiques suffisant à l’implantation des fonctions numériques complexes utilisées par la radio logicielle. Plus précisément, la possibilité offerte par les FPGA d'être reconfiguré dans leur totalité (voir même partiellement pour les derniers d’entre eux) fait d’eux des candidats idéaux à l’implantation de composants matériels flexibles et évolutifs dans le temps. À la suite de ces constatations, des travaux de recherche ont été menés au sein de l’équipe Conception des Systèmes Numériques du Laboratoire IMS. Ces travaux ont d’abord débouché sur la publication d’une architecture de sous-système cryptographique pour la radio logicielle sécurisée telle qu’elle est définie par la Software Communication Architecture. Puis, ils se sont poursuivis par la conception et l’implantation d’un cryptoprocesseur multi-cœur dynamiquement reconfigurable sur FPGAThe research detailed in this document deal with the design and implementation of a hardware integrated circuit intended to be used as a cryptographic sub-system in secure software defined radios.Since the early 90’s, radio systems have gradually evolved from traditional radio to software defined radio. Improvement of the software defined radio has enabled the integration of an increasing number of communication standards on a single radio device. The designer of a software defined radio faces many problems that can be summarized by the following question: How to implement a maximum of communication standards into a single radio device? Specifically, this work focuses on the implementation of cryptographic standards aimed to protect radio communications.Ideally, the solution to this problem is based exclusively on the use of digital processors. However, cryptographic algorithms usually require a large amount of computing power which makes their software implementation inefficient. Therefore, a secure software defined radio needs to incorporate dedicated hardware even if this usage is conflicting with the property of flexibility specific to software defined radios.Yet, in recent years, the improvement of FPGA circuits has changed the deal. Indeed, the latest FPGAs embed a number of logic gates which is sufficient to meet the needs of the complex digital functions used by software defined radios. The possibility offered by FPGAs to be reconfigured in their entirety (or even partially for the last of them) makes them ideal candidates for implementation of hardware components which have to be flexible and scalable over time.Following these observations, research was conducted within the Conception des Systèmes Numériques team of the IMS laboratory. These works led first to the publication of an architecture of cryptographic subsystem compliant with the security supplement of the Software Communication Architecture. Then, they continued with the design and implementation of a partially reconfigurable multi-core cryptoprocessor intended to be used in the latest FPGAs
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Arad, Cosmin Ionel. "Programming Model and Protocols for Reconfigurable Distributed Systems." Doctoral thesis, KTH, Programvaruteknik och Datorsystem, SCS, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-122311.
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Distributed systems are everywhere. From large datacenters to mobile devices, an ever richer assortment of applications and services relies on distributed systems, infrastructure, and protocols. Despite their ubiquity, testing and debugging distributed systems remains notoriously hard. Moreover, aside from inherent design challenges posed by partial failure, concurrency, or asynchrony, there remain significant challenges in the implementation of distributed systems. These programming challenges stem from the increasing complexity of the concurrent activities and reactive behaviors in a distributed system on the one hand, and the need to effectively leverage the parallelism offered by modern multi-core hardware, on the other hand. This thesis contributes Kompics, a programming model designed to alleviate some of these challenges. Kompics is a component model and programming framework for building distributed systems by composing message-passing concurrent components. Systems built with Kompics leverage multi-core machines out of the box, and they can be dynamically reconfigured to support hot software upgrades. A simulation framework enables deterministic execution replay for debugging, testing, and reproducible behavior evaluation for largescale Kompics distributed systems. The same system code is used for both simulation and production deployment, greatly simplifying the system development, testing, and debugging cycle. We highlight the architectural patterns and abstractions facilitated by Kompics through a case study of a non-trivial distributed key-value storage system. CATS is a scalable, fault-tolerant, elastic, and self-managing key-value store which trades off service availability for guarantees of atomic data consistency and tolerance to network partitions. We present the composition architecture for the numerous protocols employed by the CATS system, as well as our methodology for testing the correctness of key CATS algorithms using the Kompics simulation framework. Results from a comprehensive performance evaluation attest that CATS achieves its claimed properties and delivers a level of performance competitive with similar systems which provide only weaker consistency guarantees. More importantly, this testifies that Kompics admits efficient system implementations. Its use as a teaching framework as well as its use for rapid prototyping, development, and evaluation of a myriad of scalable distributed systems, both within and outside our research group, confirm the practicality of Kompics.QC 20130520
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Arad, Cosmin. "Programming Model and Protocols for Reconfigurable Distributed Systems." Doctoral thesis, SICS, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:ri:diva-24202.
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Distributed systems are everywhere. From large datacenters to mobile devices, an ever richer assortment of applications and services relies on distributed systems, infrastructure, and protocols. Despite their ubiquity, testing and debugging distributed systems remains notoriously hard. Moreover, aside from inherent design challenges posed by partial failure, concurrency, or asynchrony, there remain significant challenges in the implementation of distributed systems. These programming challenges stem from the increasing complexity of the concurrent activities and reactive behaviors in a distributed system on the one hand, and the need to effectively leverage the parallelism offered by modern multi-core hardware, on the other hand. This thesis contributes Kompics, a programming model designed to alleviate some of these challenges. Kompics is a component model and programming framework for building distributed systems by composing message-passing concurrent components. Systems built with Kompics leverage multi-core machines out of the box, and they can be dynamically reconfigured to support hot software upgrades. A simulation framework enables deterministic execution replay for debugging, testing, and reproducible behavior evaluation for large-scale Kompics distributed systems. The same system code is used for both simulation and production deployment, greatly simplifying the system development, testing, and debugging cycle. We highlight the architectural patterns and abstractions facilitated by Kompics through a case study of a non-trivial distributed key-value storage system. CATS is a scalable, fault-tolerant, elastic, and self-managing key-value store which trades off service availability for guarantees of atomic data consistency and tolerance to network partitions. We present the composition architecture for the numerous protocols employed by the CATS system, as well as our methodology for testing the correctness of key CATS algorithms using the Kompics simulation framework. Results from a comprehensive performance evaluation attest that CATS achieves its claimed properties and delivers a level of performance competitive with similar systems which provide only weaker consistency guarantees. More importantly, this testifies that Kompics admits efficient system implementations. Its use as a teaching framework as well as its use for rapid prototyping, development, and evaluation of a myriad of scalable distributed systems, both within and outside our research group, confirm the practicality of Kompics.Kompics
CATS
REST
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Han, Wei. "Multi-core architectures with coarse-grained dynamically reconfigurable processors for broadband wireless access technologies." Thesis, University of Edinburgh, 2010. http://hdl.handle.net/1842/3812.
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Broadband Wireless Access technologies have significant market potential, especially the WiMAX protocol which can deliver data rates of tens of Mbps. Strong demand for high performance WiMAX solutions is forcing designers to seek help from multi-core processors that offer competitive advantages in terms of all performance metrics, such as speed, power and area. Through the provision of a degree of flexibility similar to that of a DSP and performance and power consumption advantages approaching that of an ASIC, coarse-grained dynamically reconfigurable processors are proving to be strong candidates for processing cores used in future high performance multi-core processor systems. This thesis investigates multi-core architectures with a newly emerging dynamically reconfigurable processor – RICA, targeting WiMAX physical layer applications. A novel master-slave multi-core architecture is proposed, using RICA processing cores. A SystemC based simulator, called MRPSIM, is devised to model this multi-core architecture. This simulator provides fast simulation speed and timing accuracy, offers flexible architectural options to configure the multi-core architecture, and enables the analysis and investigation of multi-core architectures. Meanwhile a profiling-driven mapping methodology is developed to partition the WiMAX application into multiple tasks as well as schedule and map these tasks onto the multi-core architecture, aiming to reduce the overall system execution time. Both the MRPSIM simulator and the mapping methodology are seamlessly integrated with the existing RICA tool flow. Based on the proposed master-slave multi-core architecture, a series of diverse homogeneous and heterogeneous multi-core solutions are designed for different fixed WiMAX physical layer profiles. Implemented in ANSI C and executed on the MRPSIM simulator, these multi-core solutions contain different numbers of cores, combine various memory architectures and task partitioning schemes, and deliver high throughputs at relatively low area costs. Meanwhile a design space exploration methodology is developed to search the design space for multi-core systems to find suitable solutions under certain system constraints. Finally, laying a foundation for future multithreading exploration on the proposed multi-core architecture, this thesis investigates the porting of a real-time operating system – Micro C/OS-II to a single RICA processor. A multitasking version of WiMAX is implemented on a single RICA processor with the operating system support.
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Grudnitsky, Artjom [Verfasser], and J. [Akademischer Betreuer] Henkel. "A Reconfigurable Processor for Heterogeneous Multi-Core Architectures / Artjom Grudnitsky ; Betreuer: J. Henkel." Karlsruhe : KIT-Bibliothek, 2015. http://d-nb.info/1120498201/34.
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Gammoudi, Aymen. "Stratégie de placement et d'ordonnancement de taches logicielles pour architectures reconfigurables sous contrainte énergétique." Thesis, Rennes 1, 2018. http://www.theses.fr/2018REN1S030/document.
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La conception de systèmes temps-réel embarqués se développe de plus en plus avec l’intégration croissante de fonctionnalités critiques pour les applications de surveillance, notamment dans le domaine biomédical, environnemental, domotique, etc. Le développement de ces systèmes doit relever divers défis en termes de minimisation de la consommation énergétique. Gérer de tels dispositifs embarqués, entièrement autonomes, nécessite cependant de résoudre différents problèmes liés à la quantité d’énergie disponible dans la batterie, à l’ordonnancement temps-réel des tâches qui doivent être exécutées avant leurs échéances, aux scénarios de reconfiguration, particulièrement dans le cas d’ajout de tâches, et à la contrainte de communication pour pouvoir assurer l’échange des messages entre les processeurs, de façon à assurer une autonomie durable jusqu’à la prochaine recharge et ce, tout en maintenant un niveau de qualité de service acceptable du système de traitement. Pour traiter cette problématique, nous proposons dans ces travaux une stratégie de placement et d’ordonnancement de tâches permettant d’exécuter des applications temps-réel sur une architecture contenant des cœurs hétérogènes. Dans cette thèse, nous avons choisi d’aborder cette problématique de façon incrémentale pour traiter progressivement les problèmes liés aux contraintes temps-réel, énergétique et de communications. Tout d’abord, nous nous intéressons particulièrement à l’ordonnancement des tâches sur une architecture mono-cœur. Nous proposons une stratégie d’ordonnancement basée sur le regroupement des tâches dans des packs pour pouvoir calculer facilement les nouveaux paramètres des tâches afin de réobtenir la faisabilité du système. Puis, nous l’avons étendu pour traiter le cas de l’ordonnancement sur une architecture multi-cœurs homogènes. Finalement, une extension de ce dernier sera réalisée afin d’arriver à l’objectif principal qui est l’ordonnancement des tâches pour les architectures hétérogènes. L’idée est de prendre progressivement en compte des contraintes d’exécution de plus en plus complexes. Nous formalisons tous les problèmes en utilisant la formulation ILP afin de pouvoir produire des résultats optimaux. L’idée est de pouvoir situer nos solutions proposées par rapport aux solutions optimales produites par un solveur et par rapport aux autres algorithmes de l’état de l’art. Par ailleurs, la validation par simulation des stratégies proposées montre qu’elles engendrent un gain appréciable vis-à-vis des critères considérés importants dans les systèmes embarqués, notamment le coût de la communication entre cœurs et le taux de rejet des tâchesThe design of embedded real-time systems is developing more and more with the increasing integration of critical functionalities for monitoring applications, particularly in the biomedical, environmental, home automation, etc. The developement of these systems faces various challenges particularly in terms of minimizing energy consumption. Managing such autonomous embedded devices, requires solving various problems related to the amount of energy available in the battery and the real-time scheduling of tasks that must be executed before their deadlines, to the reconfiguration scenarios, especially in the case of adding tasks, and to the communication constraint to be able to ensure messages exchange between cores, so as to ensure a lasting autonomy until the next recharge, while maintaining an acceptable level of quality of services for the processing system. To address this problem, we propose in this work a new strategy of placement and scheduling of tasks to execute real-time applications on an architecture containing heterogeneous cores. In this thesis, we have chosen to tackle this problem in an incremental manner in order to deal progressively with problems related to real-time, energy and communication constraints. First of all, we are particularly interested in the scheduling of tasks for single-core architecture. We propose a new scheduling strategy based on grouping tasks in packs to calculate the new task parameters in order to re-obtain the system feasibility. Then we have extended it to address the scheduling tasks on an homogeneous multi-core architecture. Finally, an extension of the latter will be achieved in order to realize the main objective, which is the scheduling of tasks for the heterogeneous architectures. The idea is to gradually take into account the constraints that are more and more complex. We formalize the proposed strategy as an optimization problem by using integer linear programming (ILP) and we compare the proposed solutions with the optimal results provided by the CPLEX solver. Inaddition, the validation by simulation of the proposed strategies shows that they generate a respectable gain compared with the criteria considered important in embedded systems, in particular the cost of communication between cores and the rate of new tasks rejection
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Chih-HsaingPeng and 彭志祥. "A Study of Reconfigurable Multi-Core VLSI Architecture Design for Speaker-Speech Recognition." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/cwj2k3.
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博士國立成功大學
電機工程學系
103
In multimedia applications, audio processing usually requires amounts of high-dimensional computations. When intelligent applications grow up, automatic speaker-speech recognition (ASSR), which requires extraction, recognition, and learning (ERL) functions, are more and more popular. Conventional VLSI designs focus on the enhancement of single component; in addition, most chip solutions belong to high-cost and non-specified design for ASSR. This dissertation proposes a novel reconfigurable multi-core architecture which has five self-reconfigurable modes and four pre-configurable modes for low cost and high efficiency. According to this architecture, this work focuses on ASSR to design a high-dimensional processing ability chip with real-time performance. In the first part of this dissertation, this work uses a hardware/software co-design to analyze the bottleneck of whole ERL system. In the second part of this dissertation, in the bottleneck of training phase, learning is realized by hardware acceleration which has tri-mode reconfigurable ability. Compared with the baseline, the proposed work has higher usage rate of hardware. Therefore, in a low-cost limitation, this work still has high speed factor. The work is completed based on a standard library for 0.18 um CMOS technology. The chip requires a die size of 8.6 mm2 and a power comsuption of 77.33 mW to achieve 31% less gate count and 16-fold improvement of learning speed. In the third part of this dissertation, to consider the performance of whole ERL system, extraction and recognition hardware are integrated into the previous design. Because the bottleneck of testing phase comes to the extraction part, the hardware acceleration of extraction is realized. The hardware of recognition is designed for low cost. The work is manufactured based on a standard library for 90 nm CMOS technology. The chip requires a die size of 4.3 mm2 and a power comsuption of 8.9 mW to achieve 3-fold improvement of extraction speed with 26% increase of gate count. The next work integrates extraction and recognition architecture into reconfigurable architecture efficiently. The reconfigurable architecture becomes the mixing of five self-reconfigurable modes and four pre-configurable modes. The simulation results show that 3-fold improvement of extraction speed requires 17% decrease of gate count. In the fourth part of this dissertation, the specification is to achieve lower cost. Accordingly, this work presents a novel algorithm, namely binary halved clustering (BHC) to replace the conventional training method, that is, sequential minimal optimization (SMO). Compared with the popular algorithm, K-means, the proposed algorithm can save 87% less computational quantity and an average accuracy of 92.7%. This system can be applied in a case study of automatic speech-speaker recognition, and it achieves both low-computation time and high accuracy. This work is also manufactured based on a standard library for 90 nm CMOS technology. The chip requires a die size of 2.2 mm2 and a power comsuption of 8.74 mW.
Book chapters on the topic "Reconfigurable Multi-Core architecture"
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Hoppe, Augusto W., Fernanda Lima Kastensmidt, and Jürgen Becker. "Control Flow Analysis for Embedded Multi-core Hybrid Systems." In Applied Reconfigurable Computing. Architectures, Tools, and Applications, 485–96. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-78890-6_39.
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Modarressi, Mehdi, and Hamid Sarbazi-Azad. "A High-Performance and Low-Power On-Chip Network with Reconfigurable Topology." In Dynamic Reconfigurable Network-on-Chip Design, 309–29. IGI Global, 2010. http://dx.doi.org/10.4018/978-1-61520-807-4.ch013.
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In this chapter, we present a reconfigurable architecture for network-on-chips (NoC) on which arbitrary application-specific topologies can be implemented. The proposed NoC can dynamically tailor its topology to the traffic pattern of different applications, aiming to address one of the main drawbacks of existing application-specific NoC optimization methods, i.e. optimizing NoCs based on the traffic pattern of a single application. Supporting multiple applications is a critical feature of an NoC as several different applications are integrated into the modern and complex multi-core system-on-chips and chip multiprocessors and an NoC that is designed to run exactly one application does not necessarily meet the design constraints of other applications. The proposed NoC supports multiple applications by configuring as a topology which matches the traffic pattern of the currently running application in the best way. In this chapter, we first introduce the proposed reconfigurable topology and then address the two problems of core to network mapping and topology exploration. Experimental results show that this architecture effectively improves the performance of NoCs and reduces power consumption.
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Walters, John, Vipin Chaudhary, and Bertil Schmidt. "Database Searching with Profile-Hidden Markov Models on Reconfigurable and Many-Core Architectures." In Embedded Multi-Core Systems, 203–22. CRC Press, 2010. http://dx.doi.org/10.1201/ebk1439814888-c10.
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Ahmad, Balal, Ali Ahmadinia, and Tughrul Arslan. "Dynamically Reconfigurable NoC for Future Heterogeneous Multi-core Architectures." In Dynamic Reconfigurable Network-on-Chip Design, 256–76. IGI Global, 2010. http://dx.doi.org/10.4018/978-1-61520-807-4.ch010.
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To increase the efficiency of NoCs and to efficiently utilize the available hardware resources, a novel dynamically reconfigurable NoC (drNoC) is proposed in this chapter. Exploiting the notion of hardware reconfigurability, the proposed drNoC reconfigures itself in terms of switching, routing and packet size with the changing communication requirements of the system at run time, thus utilizing the maximum available channel bandwidth. In order to increase the applicability of drNoC, the network interface is designed to support OCP socket standard. This makes drNoC a highly re-useable communication framework, qualifying it as a communication centric platform for high data intensive SoC architectures. Simulation results show a 32% increase in data throughput and 22-35% decrease in network delay when compared with a traditional NoC with fixed parameters.
Conference papers on the topic "Reconfigurable Multi-Core architecture"
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Serres, Olivier, Vikram K. Narayana, and Tarek El-Ghazawi. "An Architecture for Reconfigurable Multi-core Explorations." In 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011). IEEE, 2011. http://dx.doi.org/10.1109/reconfig.2011.10.
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Chiu, Jih-Ching, Yu-Liang Chou, and Po-Kai Chen. "Hyperscalar: A Novel Dynamically Reconfigurable Multi-core Architecture." In 2010 39th International Conference on Parallel Processing (ICPP). IEEE, 2010. http://dx.doi.org/10.1109/icpp.2010.35.
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Yan, Like, Binbin Wu, Yuan Wen, Shaobin Zhang, and Tianzhou Chen. "A Reconfigurable Processor Architecture Combining Multi-core and Reconfigurable Processing Unit." In 2010 IEEE 10th International Conference on Computer and Information Technology (CIT). IEEE, 2010. http://dx.doi.org/10.1109/cit.2010.484.
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Kliem, Daniel, and Sven-Ole Voigt. "A multi-core FPGA-based SoC architecture with domain segregation." In 2012 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2012). IEEE, 2012. http://dx.doi.org/10.1109/reconfig.2012.6416764.
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Zhao, Baohua, Xiao Liang, Ningyu An, Hui Lu, and Zhan Zhang. "The Design of Heterogeneous Multi-core Reconfigurable Mobile Terminal Architecture." In the 2nd International Conference. New York, New York, USA: ACM Press, 2018. http://dx.doi.org/10.1145/3207677.3278021.
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Sutter, Louis, Thanakorn Khamvilai, Philippe Monmousseau, John B. Mains, Eric Feron, Philippe Baufreton, Francois Neumann, et al. "Experimental Allocation of Safety-Critical Applications on Reconfigurable Multi-Core Architecture." In 2018 IEEE/AIAA 37th Digital Avionics Systems Conference (DASC). IEEE, 2018. http://dx.doi.org/10.1109/dasc.2018.8569348.
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Khamvilai, Thanakorn, Louis Sutter, Jose M. Magalhaes Junior, Aqib A. Syed, and Eric Feron. "Fault Assessment of Safety-Critical Applications on Reconfigurable Multi-Core Architecture." In 2019 IEEE/AIAA 38th Digital Avionics Systems Conference (DASC). IEEE, 2019. http://dx.doi.org/10.1109/dasc43569.2019.9081703.
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Shen, Jih-Sheng, Pao-Ann Hsiung, and Juin-Ming Lu. "Reconfigurable Network-on-chip design for heterogeneous multi-core system architecture." In 2014 International Conference on High Performance Computing & Simulation (HPCS). IEEE, 2014. http://dx.doi.org/10.1109/hpcsim.2014.6903730.
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Carlos Junior, Francisco, Ivan Silva, and Ricardo Jacobi. "A Partially Shared Thin Reconfigurable Array For Multicore Processor." In IX Simpósio Brasileiro de Engenharia de Sistemas Computacionais. Sociedade Brasileira de Computação - SBC, 2019. http://dx.doi.org/10.5753/sbesc_estendido.2019.8645.
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Reconfigurable architectures have been widely used as single core processor accelerators. In the multi-core era, however, it is necessary to review the way that reconfigurable arrays are integrated into multi-core processor. Generally, a set of reconfigurable functional units are employed in a similar way as they are used in single core processors. Unfortunately, a considerable increase in the area ensues from this practice. Besides, in applications with unbalanced workload in their threads this approach can lead to a inefficient use of the reconfigurable architecture in cores with a low or even idle workload. To cope with this issue, this work proposes and evaluates a partially shared thin reconfigurable array, which allows to share reconfigurable resources among the processor's cores. Sharing is performed dynamically by the configuration scheduler hardware. The results shows that the sharing mechanism provided 76% of energy savings, improving the performance 41% in average when compared with a version without the proposed reconfigurable array. A comparison with a version of the reconfigurable array without the sharing mechanism was performed and shows that the sharing mechanism improved up to 11.16% in the system performance.
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Duch, Loris, Soumya Basu, Ruben Braojos, David Atienza, Giovanni Ansaloni, and Laura Pozzi. "A multi-core reconfigurable architecture for ultra-low power bio-signal analysis." In 2016 IEEE Biomedical Circuits and Systems Conference (BioCAS). IEEE, 2016. http://dx.doi.org/10.1109/biocas.2016.7833820.
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