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Relevant bibliographies by topics / Reduced Instruction Set Computer (RISC)

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Academic literature on the topic 'Reduced Instruction Set Computer (RISC)'

Author: Grafiati

Published: 2 June 2025

Last updated: 31 July 2025

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Journal articles on the topic "Reduced Instruction Set Computer (RISC)"

1

Achmad Maulana, Allyssa Putri, Muhamad Alif Farras Syakir, Revan Sabilillah Saputra, and Maulina Diah Lestari. "RISC vs CISC: Studi Kinerja dan Efisiensi dalam Organisasi Arsitektur Komputer." Jupiter: Publikasi Ilmu Keteknikan Industri, Teknik Elektro dan Informatika 3, no. 4 (2025): 157–71. https://doi.org/10.61132/jupiter.v3i4.973.

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The evolution of computer architecture has given rise to two main approaches: RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer). These architectures differ significantly in terms of instruction design, efficiency, and performance. This study aims to analyze the performance and efficiency of RISC and CISC in the context of computer architecture organization. The methodology includes a literature review, comparative analysis, and performance evaluation based on parameters such as processing speed, power consumption, and design complexity. The results indicate th

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Chow, P. "RISC-(reduced instruction set computers)." IEEE Potentials 10, no. 3 (1991): 28–31. http://dx.doi.org/10.1109/45.127642.

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Bansal, Malti, and Harsh. "Reduced Instruction Set Computer (RISC): A Survey." Journal of Physics: Conference Series 1916, no. 1 (2021): 012040. http://dx.doi.org/10.1088/1742-6596/1916/1/012040.

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P, Pavan, Kamal P S, Govardhan G, and Suresh Kumar V. "Basic RISC-V Instruction Set Architecture: Design and Validation." International Journal for Research in Applied Science and Engineering Technology 11, no. 5 (2023): 2845–50. http://dx.doi.org/10.22214/ijraset.2023.52205.

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Abstract: This project's primary goal is to design and implement a simple RISC V instruction set architecture. This paper offers insights into the architecture of the risc v instruction set. This system employs the RISC V R-type (register) type instruction format. Using this format, we designed the fundamental isa and tested its functionality using verilog code. There is no licence fee for using RISC V, an open source isa that is available to everyone. Reduced instruction set (RISC) computers are created to make the individual instructions given to computers to perform various tasks more manag

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Galani, Tina G., Saini Riya, and R.D.Daruwala. "Design and Implementation of 32 – bit RISC Processor using Xilinx." International Journal of Emerging Trends in Electrical and Electronics 5, no. 1 (2013): 18–24. https://doi.org/10.5281/zenodo.32433.

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These RISC or Reduced Instruction Set Computer is a design philosophy that has become a mainstream in Scientific and engineering applications. The main objective of this paper is to design and implement of 32 – bit RISC (Reduced Instruction Set Computer) processor using XILINX VIRTEX4 Tool for embedded and portable applications. The design will help to improve the speed of processor, and to give the higher performance of the processor. The most important feature of the RISC processor is that this processor is very simple and support load/store architecture. The important components of th

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Prathap, Joseph Anthony, and Sai Ramesh. "A novel reduced instruction set computer-communication processor design using field programmable gate array." International Journal of Reconfigurable and Embedded Systems (IJRES) 12, no. 2 (2023): 165. http://dx.doi.org/10.11591/ijres.v12.i2.pp165-173.

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In this paper, a novel reduced instruction set computer (RISC)- communication processor (RCP) has been designed with 32-bit operations which access 64-bit instruction format and implemented using field programmable gate array (FPGA). The design of the RISC processor is facilitated with communication operations like basic signals sine, cosine, and square, and modulation schemes like amplitude modulation, amplitude shift keying, analog, and digital quadrature amplitude modulation. Additionally, application-oriented operations like a traffic light, digital clock, and linear feedback shift registe

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Joseph, Anthony Prathap, and Ramesh Sai. "A novel reduced instruction set computer-communication processor design using field programmable gate array." International Journal of Reconfigurable and Embedded Systems (IJRES) 12, no. 2 (2023): 165–73. https://doi.org/10.11591/ijres.v12.i2.pp165-173.

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In this paper, a novel reduced instruction set computer (RISC)- communication processor (RCP) has been designed with 32-bit operations which access 64-bit instruction format and implemented using field programmable gate array (FPGA). The design of the RISC processor is facilitated with communication operations like basic signals sine, cosine, and square, and modulation schemes like amplitude modulation, amplitude shift keying, analog, and digital quadrature amplitude modulation. Additionally, application-oriented operations like a traffic light, digital clock, and linear feedback shift registe

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Deng, Lifu. "Design a 5-stage pipeline RISC-V CPU and optimise its ALU." Applied and Computational Engineering 34, no. 1 (2024): 237–44. http://dx.doi.org/10.54254/2755-2721/34/20230334.

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The RISC-V instruction set has advanced and expanded significantly in recent years. It is an open instruction set architecture (ISA) based on the concept of Reduced Instruction Set Computing (RISC). This article uses Verilog to design a 5-stage pipeline CPU based on RISC-V architecture in Vivado 2022.2. The CPU can execute 38 instructions and optimises its arithmetic logic unit (ALU) by optimising adders, shifters, and multipliers. Next, write a testbench in the simulation software to verify the functionality of the CPU. RTL diagrams and reports are then generated to verify the design structur

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Divya., D., R. Balasaraswathi., kalyani. M. Harini, and Anand. I. Vivek. "Modeling and Execution of Floating Point Parallel Processing Operation for RISC Processor." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 3 (2020): 3783–89. https://doi.org/10.35940/ijeat.C6203.029320.

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The development of processors with sundry suggestions have been made regarding a exactitude definition of RISC, but the prosaic concept is that such a computer has a small set of simple and prosaic instructions, instead of an outsized set of intricate and specialized instructions. This project proposes the planning of a high speed 64 bit RISC processor. The miens of this processor consume less power and it contrives on high speed. The processor comprises of sections namely Instruction Fetch section, Instruction Decode section, and Execution section. The ALU within the execution section compris

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Michel Deves de Souza, Eduardo, Nathalia Nathalia Adriana de Oliveira, Douglas Almeida dos Santos Almeida dos Santos, and Douglas Rossi de Melo. "RVSH - Um processador RISC-V para fins didáticos." Anais do Computer on the Beach 14 (May 3, 2023): 450–52. http://dx.doi.org/10.14210/cotb.v14.p450-452.

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ABSTRACTEmbedded systems constitute the class of computers that presentthe most significant volume and are increasingly present ineveryday life. The main element of these systems is the processor,which can be found in discrete form, represented by a physicalcomponent, or cores, as used in programmable logic devices.Processors of the same architecture share the same instructionset but may differ in the organization’s implementation. RISC(Reduced Instruction Set Computer) is the class of architecturesthat favors a simple, reduced instruction set. RISC-V is an exampleof such architecture, which c

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Dissertations / Theses on the topic "Reduced Instruction Set Computer (RISC)"

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Chatterjee, Aakriti. "Development of an RSA Algorithm using Reduced RISC V instruction Set." University of Cincinnati / OhioLINK, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1617104502129937.

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Chen, Wan-Fu. "A high speed 16-bit RISC processor chip /." Online version of thesis, 1994. http://hdl.handle.net/1850/11754.

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Afuah, Allan Nembo. "Strategic adoption of innovation--the case of reduced instruction set computer (RISC) technology." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/11613.

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Moustakas, Evangelos. "Design and simulation of a primitive RISC architecture using VHDL /." Online version of thesis, 1991. http://hdl.handle.net/1850/11229.

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Tharpe, Leonard. "A study on the effectiveness of lockup-free caches for a Reduced Instruction Set Computer (RISC) processor." Thesis, Monterey, California. Naval Postgraduate School, 1992. http://hdl.handle.net/10945/24057.

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Approved for public release; distribution is unlimited<br>This thesis presents a simulation and analysis of the Reduced Instruction Set Computer (RISC) architecture and the effects on RISC performance of a lockup-free cache interface. RISC architectures achieve high performance by having a small, but sufficient, instruction set with most instructions executing in one clock cycle. Current RISC performance range from 1.5 to 2.0 CPI. The goal of RISC is to attain a CPI of 1.0. The major hindrance in attaining that goal is attributed to instructions that require main memory access. In this th

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Marwood, Warren. "An integrated multiprocessor for matrix algorithms /." Title page, table of contents and abstract only, 1994. http://web4.library.adelaide.edu.au/theses/09PH/09phm391.pdf.

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Varanasi, Archana. "Course grained low power design flow using UPF /." Online version of thesis, 2009. http://hdl.handle.net/1850/11768.

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Musasa, Mutombo Mike. "Evaluation of embedded processors for next generation asic : Evaluation of open source Risc-V processors and tools ability to perform packet processing operations compared to Arm Cortex M7 processors." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-299656.

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Nowadays, network processors are an integral part of information technology. With the deployment of 5G network ramping up around the world, numerous new devices are going to take advantage of their processing power and programming flexibility. Contemporary information technology providers of today such as Ericsson, spend a great amount of financial resources on licensing deals to use processors with proprietary instruction set architecture designs from companies like Arm holdings. There is a new non-proprietary instruction set architecture technology being developed known as Risc-V. There are

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Gribble, Donald L. "A new RISC architecture for high speed data acquisition." Thesis, 1991. http://hdl.handle.net/1957/37001.

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This thesis describes the design of a RISC architecture for high speed data acquisition. The structure of existing data acquisition systems is first examined. An instruction set is created to allow the data acquisition system to serve a wide variety of applications. The architecture is designed to allow the execution of an instruction each clock cycle. The utility of the RISC system is illustrated by implementing several representative applications. Performance of the system is analyzed and future enhancements discussed.<br>Graduation date: 1992

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Beaumont-Smith, Andrew James. "MatRISC : a RISC multiprocessor for matrix applications / Andrew James Beaumont-Smith." 2001. http://hdl.handle.net/2440/21852.

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"November, 2001"<br>Errata on back page.<br>Includes bibliographical references (p. 179-183)<br>xxii, 193 p. : ill. (some col.), plates (col.) ; 30 cm.<br>Title page, contents and abstract only. The complete thesis in print form is available from the University Library.<br>This thesis proposes a highly integrated SOC (system on a chip) matrix-based parallel processor which can be used as a co-processor when integrated into the on-chip cache memory of a microprocessor in a workstation environment.<br>Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 2002

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Books on the topic "Reduced Instruction Set Computer (RISC)"

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William, Stallings, ed. Tutorial: Reduced instruction set computers. IEEE Computer Society Press, 1986.

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Feldman, James M. Computer architecture: A designer's text based on a generic RISC. McGraw-Hill, 1994.

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Feldman, James M. Computer architecture: A designer's text based on a generic RISC. McGraw-Hill, 1994.

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James, Goodman. A programmer's view of computer architecture: With examples from the MIPS RISC architecture. Saunders College Pub., 1993.

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Tabak, Daniel. RISC systems. Research Studies Press, 1990.

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Kane, Gerry. MIPS R2000 RISC architecture. Prentice Hall, 1987.

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Afuah, Allan Nembo. Successful incumbents: Puzzles in the adoption of RISC (reduced instruction set computers). Alfred P. Sloan School of Management, Massachusetts Institute of Technology, 1994.

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Waldron, John. Introduction to RISC assembly language programming. Addison-Wesley, 1999.

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Konsek, Marian B. Context switching with multiple register windows: A RISC performance study. Dept. of Computer Science, University of Illinois at Urbana-Champaign, 1987.

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Tharpe, Leonard. A study on the effectiveness of lockup-free caches for a Reduced Instruction Set Computer (RISC) processor. Naval Postgraduate School, 1992.

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Book chapters on the topic "Reduced Instruction Set Computer (RISC)"

1

Schiffmann, Wolfram, and Robert Schmitz. "Reduced Instruction Set Computer." In Springer-Lehrbuch. Springer Berlin Heidelberg, 1994. http://dx.doi.org/10.1007/978-3-662-10238-1_5.

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Schiffmann, Wolfram, and Robert Schmitz. "Reduced Instruction Set Computer." In Technische Informatik 2. Springer Berlin Heidelberg, 1992. http://dx.doi.org/10.1007/978-3-662-22465-6_5.

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Weik, Martin H. "reduced-instruction-set computer." In Computer Science and Communications Dictionary. Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_15767.

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Chalk, B. S. "Reduced Instruction Set Computers." In Computer Organisation and Architecture. Macmillan Education UK, 1996. http://dx.doi.org/10.1007/978-1-349-13871-5_9.

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Chalk, B. S., A. T. Carter, and R. W. Hind. "Reduced instruction set computers." In Computer Organisation and Architecture. Macmillan Education UK, 2004. http://dx.doi.org/10.1007/978-0-230-00060-5_10.

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Wang, Chao. "RISC-V Open Source Instruction Set and Architecture." In Domain-Specific Computer Architectures for Emerging Applications. Chapman and Hall/CRC, 2024. http://dx.doi.org/10.1201/9780429355080-12.

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Tempel, Sören, Tobias Brandt, and Christoph Lüth. "Versatile and Flexible Modelling of the RISC-V Instruction Set Architecture." In Lecture Notes in Computer Science. Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-38938-2_2.

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Gesper, Sven, Fabian Stuckmann, Lucy Wöbbekind, and Guillermo Payá-Vayá. "PATARA: Extension of a Verification Framework for RISC-V Instruction Set Implementations." In Lecture Notes in Computer Science. Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-46077-7_15.

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Raveendran, Aneesh, Sandra Jean, J. Mervin, D. Vivian, and David Selvakumar. "RISC-V Half Precision Floating Point Instruction Set Extensions and Co-processor." In Communications in Computer and Information Science. Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-32-9767-8_40.

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Armstrong, Alasdair, Brian Campbell, Ben Simner, Christopher Pulte, and Peter Sewell. "Isla: Integrating Full-Scale ISA Semantics and Axiomatic Concurrency Models." In Computer Aided Verification. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-81685-8_14.

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AbstractArchitecture specifications such as Armv8-A and RISC-V are the ultimate foundation for software verification and the correctness criteria for hardware verification. They should define the allowed sequential and relaxed-memory concurrency behaviour of programs, but hitherto there has been no integration of full-scale instruction-set architecture (ISA) semantics with axiomatic concurrency models, either in mathematics or in tools. These ISA semantics can be surprisingly large and intricate, e.g. 100k+ lines for Armv8-A. In this paper we present a tool, Isla, for computing the allowed beh

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Conference papers on the topic "Reduced Instruction Set Computer (RISC)"

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K, Paldurai, Srivarsa T, Ashwin Kumar S, Bharath Ram K, and Chandra Prakash S. "UVM Verification of RISC-V Instruction set." In 2024 International Conference on Smart Systems for Electrical, Electronics, Communication and Computer Engineering (ICSSEECC). IEEE, 2024. http://dx.doi.org/10.1109/icsseecc61126.2024.10649455.

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Chen, Jianxin, Hong Hao, Shuai Wang, et al. "A Multiple Precision Floating-Point Arithmetic Unit Based on the RISC-V Instruction Set." In 2024 4th International Conference on Electronic Information Engineering and Computer (EIECT). IEEE, 2024. https://doi.org/10.1109/eiect64462.2024.10867213.

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Migliorini Magagnin, Nicole, Benjamin William Mezger, and Douglas Rossi de Melo. "Técnica de confiabilidade em nível de sistema operacional para a arquitetura RISC-V." In Computer on the Beach. Universidade do Vale do Itajaí, 2024. http://dx.doi.org/10.14210/cotb.v15.p165-171.

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ABSTRACTEmbedded systems are applications used for specific tasks or as partof a general purpose, having constraints and design metrics. Thesesystems are implemented using microprocessors, with a favorableoption being the RISC (Reduced Instruction Set Computer), whichhas a reduced number of instructions and shorter execution time. Ahighlight within the RISC architecture is the RISC-V, an open andstable instruction set. Since the increase in reliability is essentialfor embedded systems operating in critical environments, thereis a need for fault tolerance provision in hardware and software.Thus

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Dickinson, Alex. "An Optical Respite from the Von Neumann Bottleneck." In Optical Computing. Optica Publishing Group, 1991. http://dx.doi.org/10.1364/optcomp.1991.tuc4.

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The high end of microprocessor performance is currently dominated by Reduced Instruction Set Computer (RISC) architectures. These machines execute one or more instructions per clock cycle. A processor such as the i8601 [1] runs with a 40MHz clock - requiring that on average an instruction must be delivered to the CPU every 25nS. With DRAM access times currently at around 100nS, timely instruction delivery has become a critical constraint on processor speed.

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Lazaro, Jose B., Maribelle D. Pabiania, Lewmorc James S. Bitangcor, John Carlo Benedict De Torres, Joseph Marxlen A. Dumapit, and Jayvee N. Mapote. "Design of a 32-bit Datapath for a Reduced Instruction Set Computers (RISC) Implementation using the DE0-nano FPGA." In 2024 16th International Conference on Computer and Automation Engineering (ICCAE). IEEE, 2024. http://dx.doi.org/10.1109/iccae59995.2024.10569847.

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William Mezger, Benjamin, Fabricio Bortoluzzi, Cesar Albenes Zeferino, Paulo Roberto Oliveira Valim, and Douglas Rossi Melo. "A Basic Microkernel for the RISC-V Instruction Set Architecture." In Computer on the Beach. Universidade do Vale do Itajaí, 2021. http://dx.doi.org/10.14210/cotb.v12.p057-063.

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ABSTRACTComputer processors provide an abstract model known as theinstruction set architecture, which serves as an interface betweenthe available hardware and the software. Application developersneed to communicate with these types of hardware, and having tolearn each computer specification is difficult and time-consuming.Operating systems provide an abstraction towards the availablecomputer hardware and user software. They manage computerresources to enable application programmers to communicate withthe available hardware. This work introduces an academic-orientedoperating system for the RISC

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Eljhani, Mohamed M., and Veton Z. Kepuska. "Reduced Instruction Set Computer Design on FPGA." In 2021 IEEE 1st International Maghreb Meeting of the Conference on Sciences and Techniques of Automatic Control and Computer Engineering MI-STA. IEEE, 2021. http://dx.doi.org/10.1109/mi-sta52233.2021.9464409.

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Sarkisla, Mehmet Alp, and Arda Yurdakul. "SIMDify: Framework for SIMD-Processing with RISC-V Scalar Instruction Set." In ACSW '21: 2021 Australasian Computer Science Week Multiconference. ACM, 2021. http://dx.doi.org/10.1145/3437378.3444364.

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Gao, Zhanyuan, Laiping Zhao, and Haonan Chen. "A Trigonometric Function Instruction Set Extension Method Based on RISC-V." In 2022 IEEE/ACIS 22nd International Conference on Computer and Information Science (ICIS). IEEE, 2022. http://dx.doi.org/10.1109/icis54925.2022.9882453.

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Liu, Ya, Yanling Zhou, Xianping Zheng, and Wangping Xiong. "The research and development of reduced instruction set computer." In 2011 IEEE 3rd International Conference on Communication Software and Networks (ICCSN). IEEE, 2011. http://dx.doi.org/10.1109/iccsn.2011.6014365.

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Reports on the topic "Reduced Instruction Set Computer (RISC)"

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McDonald, John F. F-RISC- A 1.0 GOPS Fast Reduced Instruction Set Computer for Super Workstation and Teraops Parallel Processor Applications. Defense Technical Information Center, 2001. http://dx.doi.org/10.21236/ada394207.

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