Academic literature on the topic 'Redundant number systems'
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Journal articles on the topic "Redundant number systems"
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Timmermann, D., and B. J. Hosticka. "Overflow effects in redundant binary number systems." Electronics Letters 29, no. 5 (1993): 440. http://dx.doi.org/10.1049/el:19930294.
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Seo, Jong Hyen, and Seon Ah Roh. "Design and Inspection Policy for Redundant Systems Using Information of Warranty." Key Engineering Materials 277-279 (January 2005): 226–32. http://dx.doi.org/10.4028/www.scientific.net/kem.277-279.226.
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This paper considers the problem of determining the optimal number of redundant units in redundant systems with random unit failures and warranty. Parallel and k out of n systems are considered. The optimal number of redundant units which minimize the expected cost rate is found and the number is shown to be finite and unique. For given inspection interval before expiration of warranty, the optimal number of redundant units is also obtained. The effects of inspection and the warranty to the optimal number of redundant units are studied.
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Parhami, B. "Generalized signed-digit number systems: a unifying framework for redundant number representations." IEEE Transactions on Computers 39, no. 1 (1990): 89–98. http://dx.doi.org/10.1109/12.46283.
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Anwer, Jahanzeb, Sebastian Meisner, and Marco Platzner. "Dynamic Reliability Management for FPGA-Based Systems." International Journal of Reconfigurable Computing 2020 (June 13, 2020): 1–19. http://dx.doi.org/10.1155/2020/2808710.
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Radiation tolerance in FPGAs is an important field of research particularly for reliable computation in electronics used in aerospace and satellite missions. The motivation behind this research is the degradation of reliability in FPGA hardware due to single-event effects caused by radiation particles. Redundancy is a commonly used technique to enhance the fault-tolerance capability of radiation-sensitive applications. However, redundancy comes with an overhead in terms of excessive area consumption, latency, and power dissipation. Moreover, the redundant circuit implementations vary in structure and resource usage with the redundancy insertion algorithms as well as number of used redundant stages. The radiation environment varies during the operation time span of the mission depending on the orbit and space weather conditions. Therefore, the overheads due to redundancy should also be optimized at run-time with respect to the current radiation level. In this paper, we propose a technique called Dynamic Reliability Management (DRM) that utilizes the radiation data, interprets it, selects a suitable redundancy level, and performs the run-time reconfiguration, thus varying the reliability levels of the target computation modules. DRM is composed of two parts. The design-time tool flow of DRM generates a library of various redundant implementations of the circuit with different magnitudes of performance factors. The run-time tool flow, while utilizing the radiation/error-rate data, selects a required redundancy level and reconfigures the computation module with the corresponding redundant implementation. Both parts of DRM have been verified by experimentation on various benchmarks. The most significant finding we have from this experimentation is that the performance can be scaled multiple times by using partial reconfiguration feature of DRM, e.g., 7.7 and 3.7 times better performance results obtained for our data sorter and matrix multiplier case studies compared with static reliability management techniques. Therefore, DRM allows for maintaining a suitable trade-off between computation reliability and performance overhead during run-time of an application.
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Sahoo, S. K., Anu Gupta, Abhijit R. Asati, and Chandra Shekhar. "A Novel Redundant Binary Number to Natural Binary Number Converter." Journal of Signal Processing Systems 59, no. 3 (August 11, 2009): 297–307. http://dx.doi.org/10.1007/s11265-009-0392-x.
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Potkonjak, Veljko. "Distributed positioning for redundant robotic systems." Robotica 8, no. 1 (January 1990): 61–67. http://dx.doi.org/10.1017/s0263574700007323.
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SUMMARYA new approach to redundant robots is presented. The problem of the multiple solutions of the inverse kinematic is solved by making a special distribution of robot external motions to the redundant number of joint motions. The distribution is made in such a way to separate the smooth transport motion from the relative motion which could be fast and have high acceleration.
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Bhattacharya, Debasis, and Soma Roychowdhury. "On constrained reliability maximization using active redundancy in coherent systems with non-overlapping subsystems." An International Journal of Optimization and Control: Theories & Applications (IJOCTA) 5, no. 1 (October 25, 2014): 33–39. http://dx.doi.org/10.11121/ijocta.01.2015.00205.
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The paper investigates a problem of constrained reliability maximization by allocating redundancy and proposes how to solve it for a broad group of complex coherent systems. Redundancy is an effective engineering tool to enhance system reliability to make a system fail-safe. Since adding redundancy increases the cost and complexity of a system design, it should be used wisely. The work considers an exact solution to the problem under resource constraints and finds optimal redundancy numbers. The proposed method can accommodate any number of constraints. Numerical examples have been included. A sensitivity analysis has been carried out to show how sensitive the optimal allocation of redundant components and the gain in system reliability are to the budget allocation.
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Vik Tor Goh and M. U. Siddiqi. "Multiple error detection and correction based on redundant residue number systems." IEEE Transactions on Communications 56, no. 3 (March 2008): 325–30. http://dx.doi.org/10.1109/tcomm.2008.050401.
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Heuberger, Clemens. "Minimal expansions in redundant number systems: Fibonacci bases and Greedy algorithms." Periodica Mathematica Hungarica 49, no. 2 (December 2004): 65–89. http://dx.doi.org/10.1007/s10998-004-0523-x.
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Amanollahi, Saba, and Ghassem Jaberipur. "Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 3 (March 2017): 954–61. http://dx.doi.org/10.1109/tvlsi.2016.2604346.
Full textDissertations / Theses on the topic "Redundant number systems"
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Sengupta, Avik. "Redundant residue number system based space-time block codes." Thesis, Kansas State University, 2012. http://hdl.handle.net/2097/14111.
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Master of ScienceDepartment of Electrical and Computer Engineering
Balasubramaniam Natarajan
Space-time coding (STC) schemes for Multiple Input Multiple Output (MIMO) systems have been an area of active research in the past decade. In this thesis, we propose a novel design of Space-Time Block Codes (STBCs) using Redundant Residue Number System (RRNS) codes, which are ideal for high data rate communication systems. Application of RRNS as a concatenated STC scheme to a MIMO wireless communication system is the main motivation for this work. We have optimized the link between residues and complex constellations by incorporating the “Direct Mapping” scheme, where residues are mapped directly to Gray coded constellations. Knowledge of apriori probabilities of residues is utilized to implement a probability based “Distance-Aware Direct Mapping” (DA) scheme, which uses a set-partitioning approach to map the most probable residues such that they are separated by the maximum possible distance. We have proposed an “Indirect Mapping” scheme, where we convert the residues back to bits before mapping them. We have also proposed an adaptive demapping scheme which utilizes the RRNS code structure to reduce the ML decoding complexity and improve the error performance. We quantify the upper bounds on codeword and bit error probabilities of both Systematic and Non-systematic RRNS-STBC and characterize the achievable coding and diversity gains assuming maximum likelihood decoding (MLD). Simulation results demonstrate that the DA Mapping scheme provides performance gain relative to a Gray coded direct mapping scheme. We show that Systematic RRNS-STBC codes provide superior performance compared to Nonsystematic RRNS-STBC, for the same code parameters, owing to more efficient binary to residue mapping. When compared to other concatenated STBC and Orthogonal STBC (OSTBC) schemes, the proposed system gives better performance at low SNRs.
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Kamp, William Hermanus Michael. "Redundant Number Systems for Optimising Digital Signal Processing Performance in Field Programmable Gate Array." Thesis, University of Canterbury. Electrical and Computer Engineering, 2010. http://hdl.handle.net/10092/4623.
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Speeding up addition is the key to faster digital signal processing (DSP). This can be achieved by exploiting the properties of redundant number systems. Their expanded symbol (digit) alphabet gives them multiple representations for most values. Utilising redundant representations at the output of an adder permits addition to be performed without carry-propagation, yielding fast, constant time performance irrespective of the word length. A resource efficient implementation of this fast adder structure is developed that re-purposes the fast carry logic of low-cost field programmable gate arrays (FPGAs). Experiments confirm constant time addition and show that it outperforms binary ripple carry addition at word lengths of greater than 44 bits in a Xilinx Spartan 3 FPGA and 24 bits in an Altera Cyclone III FPGA.
Redundancy also provides other properties that can be exploited for performance gain. Some redundant representations will have more zero-symbols than others. These maximise the opportunities to exploit the multiplicative absorbing and additive identity properties of zero that when exercised reduce superfluous calculations. A serial recoding algorithm is developed that generates a redundant representation for a specified value with as few nonzero symbols as possible. Unlike previously published methods, it accepts a wide specification of number systems including those with irregularly spaced symbol alphabets. A Markov analysis and analysis of the elementary cycles in the formulated state machine provides average and worst case measures for the tested number system. Typically, the average number of non-zero symbols is less than a third and the worst case is less than a half.
Further to the increase in zero-symbols, zero-dominance is proposed as a new property of redundant number representations. It promotes a set of representations that have uniquely positioned zero-symbols, in a Pareto-optimal sense. This set covers all representations of a value and is used to select representations to optimise the calculation of a dot-product.
The dot-product or vector-multiply is a fundamental operation in DSP, since it is employed in filtering, correlation and convolution. The nonzero partial products can be packed together, substantially reducing the calculation time. The application of redundant number systems provides a two-fold benefit. Firstly, the number of nonzero partial products is reduced. Secondly, a novel opportunity is identified to use the representations in the zero-dominant set to optimise the packing further, gaining an extra 18% improvement.
An implementation of the proposed dot-product with partial product packing is developed for a Cyclone II FPGA. It outperforms a quad-multiplier binary implementation in throughput by 50% .
Redundant number systems excel at increasing performance in particular DSP subsystems, those that are numerically intensive and consist of considerable accumulation. The conversion back to a binary result is the performance bottleneck in the DSP algorithm, taking a time proportional to a binary adder. Therefore, redundant number systems are best utilised when this conversion cost can be amortised over many fast redundant additions, which is typical in many DSP and communications applications.
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Al-Hasani, Firas Ali Jawad. "Multiple Constant Multiplication Optimization Using Common Subexpression Elimination and Redundant Numbers." Thesis, University of Canterbury. Electrical and Computer Engineering, 2014. http://hdl.handle.net/10092/9054.
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The multiple constant multiplication (MCM) operation is a fundamental operation in digital signal processing (DSP) and digital image processing (DIP). Examples of the MCM are in finite impulse response (FIR) and infinite impulse response (IIR) filters, matrix multiplication, and transforms.
The aim of this work is minimizing the complexity of the MCM operation using common subexpression elimination (CSE) technique and redundant number representations. The CSE technique searches and eliminates common digit patterns (subexpressions) among MCM coefficients. More common subexpressions can be found by representing the MCM coefficients using redundant number representations.
A CSE algorithm is proposed that works on a type of redundant numbers called the zero-dominant set (ZDS). The ZDS is an extension over the representations of minimum number of non-zero digits called minimum Hamming weight (MHW). Using the ZDS improves CSE algorithms' performance as compared with using the MHW representations. The disadvantage of using the ZDS is it increases the possibility of overlapping patterns (digit collisions). In this case, one or more digits are shared between a number of patterns. Eliminating a pattern results in losing other patterns because of eliminating the common digits. A pattern preservation algorithm (PPA) is developed to resolve the overlapping patterns in the representations.
A tree and graph encoders are proposed to generate a larger space of number representations. The algorithms generate redundant representations of a value for a given digit set, radix, and wordlength. The tree encoder is modified to search for common subexpressions simultaneously with generating of the representation tree. A complexity measure is proposed to compare between the subexpressions at each node. The algorithm terminates generating the rest of the representation tree when it finds subexpressions with maximum sharing. This reduces the search space while minimizes the hardware complexity.
A combinatoric model of the MCM problem is proposed in this work. The model is obtained by enumerating all the possible solutions of the MCM that resemble a graph called the demand graph. Arc routing on this graph gives the solutions of the MCM problem. A similar arc routing is found in the capacitated arc routing such as the winter salting problem. Ant colony optimization (ACO) meta-heuristics is proposed to traverse the demand graph. The ACO is simulated on a PC using Python programming language. This is to verify the model correctness and the work of the ACO. A parallel simulation of the ACO is carried out on a multi-core super computer using C++ boost graph library.
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Rocha, Eugénio Alexandre Miguel. "Uma Abordagem Algébrica à Teoria de Controlo Não Linear." Doctoral thesis, Universidade de Aveiro, 2003. http://hdl.handle.net/10773/21444.
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Doutoramento em MatemáticaNesta tese de Doutoramento desenvolve-se principalmente uma abordagem algébrica à teoria de sistemas de controlo não lineares. No entanto, outros tópicos são também estudados. Os tópicos tratados são os seguidamente enunciados: fórmulas para sistemas de controlo sobre álgebras de Lie livres, estabilidade de um sistema de corpos rolantes, algoritmos para aritmética digital, e equações integrais de Fredholm não lineares. No primeiro e principal tópico estudam-se representações para as soluções de sistemas de controlo lineares no controlo. As suas trajetórias são representadas pelas chamadas séries de Chen. Estuda-se a representação formal destas séries através da introdução de várias álgebras não associativas e técnicas específicas de álgebras de Lie livres. Sistemas de coordenadas para estes sistemas são estudados, nomeadamente, coordenadas de primeiro tipo e de segundo tipo. Apresenta-se uma demonstração alternativa para as coordenadas de segundo tipo e obtêm-se expressões explícitas para as coordenadas de primeiro tipo. Estas últimas estão intimamente ligadas ao logaritmo da série de Chen que, por sua vez, tem fortes relações com uma fórmula designada na literatura por “continuous Baker-Campbell- Hausdorff formula”. São ainda apresentadas aplicações à teoria de funções simétricas não comutativas. É, por fim, caracterizado o mapa de monodromia de um campo de vectores não linear e periódico no tempo em relação a uma truncatura do logaritmo de Chen. No segundo tópico é estudada a estabilizabilidade de um sistema de quaisquer dois corpos que rolem um sobre o outro sem deslizar ou torcer. Constroem-se controlos fechados e dependentes do tempo que tornam a origem do sistema de dois corpos num sistema localmente assimptoticamente estável. Vários exemplos e algumas implementações em Maple°c são discutidos. No terceiro tópico, em apêndice, constroem-se algoritmos para calcular o valor de várias funções fundamentais na aritmética digital, sendo possível a sua implementação em microprocessadores. São também obtidos os seus domínios de convergência. No último tópico, também em apêndice, demonstra-se a existência e unicidade de solução para uma classe de equações integrais não lineares com atraso. O atraso tem um carácter funcional, mostrando-se ainda a diferenciabilidade no sentido de Fréchet da solução em relação à função de atraso.
In this PhD thesis several subjects are studied regarding the following topics: formulas for nonlinear control systems on free Lie algebras, stabilizability of nonlinear control systems, digital arithmetic algorithms, and nonlinear Fredholm integral equations with delay. The first and principal topic is mainly related with a problem known as the continuous Baker-Campbell-Hausdorff exponents. We propose a calculus to deal with formal nonautonomous ordinary differential equations evolving on the algebra of formal series defined on an alphabet. We introduce and connect several (non)associative algebras as Lie, shuffle, zinbiel, pre-zinbiel, chronological (pre-Lie), pre-chronological, dendriform, D-I, and I-D. Most of those notions were also introduced into the universal enveloping algebra of a free Lie algebra. We study Chen series and iterated integrals by relating them with nonlinear control systems linear in control. At the heart of all the theory of Chen series resides a zinbiel and shuffle homomorphism that allows us to construct a purely formal representation of Chen series on algebras of words. It is also given a pre-zinbiel representation of the chronological exponential, introduced by A.Agrachev and R.Gamkrelidze on the context of a tool to deal with nonlinear nonautonomous ordinary differential equations over a manifold, the so-called chronological calculus. An extensive description of that calculus is made, collecting some fragmented results on several publications. It is a fundamental tool of study along the thesis. We also present an alternative demonstration of the result of H.Sussmann about coordinates of second kind using the mentioned tools. This simple and comprehensive proof shows that coordinates of second kind are exactly the image of elements of the dual basis of a Hall basis, under the above discussed homomorphism. We obtain explicit expressions for the logarithm of Chen series and the respective coordinates of first kind, by defining several operations on a forest of leaf-labelled trees. It is the same as saying that we have an explicit formula for the functional coefficients of the Lie brackets on a continuous Baker-Campbell-Hausdorff-Dynkin formula when a Hall basis is used. We apply those formulas to relate some noncommutative symmetric functions, and we also connect the monodromy map of a time-periodic nonlinear vector field with a truncation of the Chen logarithm. On the second topic, we study any system of two bodies rolling one over the other without twisting or slipping. By using the Chen logarithm expressions, the monodromy map of a flow and Lyapunov functions, we construct time-variant controls that turn the origin of a control system linear in control into a locally asymptotically stable equilibrium point. Stabilizers for control systems whose vector fields generate a nilpotent Lie algebra with degree of nilpotency · 3 are also given. Some examples are presented and Maple°c were implemented. The third topic, on appendix, concerns the construction of efficient algorithms for Digital Arithmetic, potentially for the implementation in microprocessors. The algorithms are intended for the computation of several functions as the division, square root, sines, cosines, exponential, logarithm, etc. By using redundant number representations and methods of Lyapunov stability for discrete dynamical systems, we obtain several algorithms (that can be glued together into an algorithm for parallel execution) having the same core and selection scheme in each iteration. We also prove their domains of convergence and discuss possible extensions. The last topic, also on appendix, studies the set of solutions of a class of nonlinear Fredholm integral equations with general delay. The delay is of functional character modelled by a continuous lag function. We ensure existence and uniqueness of a continuous (positive) solution of such equation. Moreover, under additional conditions, it is obtained the Fr´echet differentiability of the solution with respect to the lag function.
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Shieh, Shao-Hui, and 謝韶徽. "Minimally Redundant Signed-Digit Number Systems." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/11129512062151387099.
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博士國立清華大學
電機工程學系
91
We propose the minimally redundant signed-digit (MRSD) number system, including its subsets the asymmetric high-radix signed-digit (AHSD), the minimal redundant positive-digit (MRPD), the symmetric high-radix signed-digit (SHSD) and the binary signed-digit (BSD) number systems, for fast binary addition and multiplication, and show that the MRSD number system supports carry-free (CF) addition. The CF additions in MRSD, to be classified as fully-closed, quasi-closed and sub-closed additions, use only one redundant digit for any radix r≧2. The criterion for the existence of carry-free additions, in terms of redundancy-index and radix, is thus from tightly bounded down to loosely bounded. Novel algorithms for constructing the two-stage and three-stage CF adders (CFA) based on the MRSD number system are also presented. Moreover, if the radix is specified as r= , where m is any positive integer, the binary-to-MRSD conversion can be done in constant time regardless of the word-length. Hence, the MRSD-to-binary conversion dominates the performance of an MRSD-based arithmetic system. We also propose two efficient algorithms for converting MRSD numbers to binary ones. The first one uses a novel structure to achieve high speed, while the second one uses simple transformations and conventional additions to provide hardware reusability. These results are important since the conversion from MRSD numbers to binary ones has been considered the performance bottleneck of the MRSD-based arithmetic systems. Algorithms for converting from asymmetric high-radix signed-digit (AHSD) numbers and minimal redundant positive-digit (MRPD) numbers to binary numbers are proposed. Our approach is based on simple transformation among AHSD, MRPD, and conventional radix-r (CR) number systems. We also show that the conversion from AHSD or MRPD numbers to binary numbers can be reduced to r''s-complement addition. The result is important since the conversion from AHSD or MRPD to binary has been considered the performance bottleneck of the AHSD-based or MRPD-based arithmetic systems. We show that the AHSD-to-binary conversion is similar to the MRPD-to-binary conversion. Therefore, a good hardware architecture for any of the following three applications can be used for the other two: 1) r''s-complement addition, 2) AHSD-to-binary conversion, and 3) MRPD-to-binary conversion. In addition to performance improvement, the main contribution of this work is hardware reusability and design flexibility, so far as the involved number systems are concerned. We also show that Blair''s work is just a special case (for r=2) as discussed in this dissertation. Examples are given to demonstrate the proposed algorithms. The CF adder based on MRSD is especially suited to high-performance arithmetic with long sequences of addition-related computations performed on a massive amount of data. Practical implementations of the high-performance CF adder and array multiplier are presented. We conclude that MRSD is one of the excellent number systems to have the possibility to achieve high-performance operations with the smaller integrated circuits in high circuitry density. The conditions for the existence of various carry-free additions, performed over different digit sets with sufficient redundancy, are also concluded as loosely-bounded, Parhami''s, tightly-bounded and uppermost-bounded criteria in terms of redundancy-index and radix.
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"HIGH-SPEED CO-PROCESSORS BASED ON REDUNDANT NUMBER SYSTEMS." Thesis, 2015. http://hdl.handle.net/10388/ETD-2015-02-1945.
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There is a growing demand for high-speed arithmetic co-processors for use in applications with computationally intensive tasks. For instance, Fast Fourier Transform (FFT) co-processors are used in real-time multimedia services and financial applications use decimal co-processors to perform large amounts of decimal computations.
Using redundant number systems to eliminate word-wide carry propagation within interim operations is a well-known technique to increase the speed of arithmetic hardware units. Redundant number systems are mostly useful in applications where many consecutive arithmetic operations are performed prior to the final result, making it advantageous for arithmetic co-processors. This thesis discusses the implementation of two popular arithmetic co-processors based on redundant number systems: namely, the binary FFT co-processor and the decimal arithmetic co-processor.
FFT co-processors consist of several consecutive multipliers and adders over complex numbers. FFT architectures are implemented based on fixed-point and floating-point arithmetic. The main advantage of floating-point over fixed-point arithmetic is the wide dynamic range it introduces. Moreover, it avoids numerical issues such as scaling and overflow/underflow concerns at the expense of higher cost. Furthermore, floating-point implementation allows for an FFT co-processor to collaborate with general purpose processors. This offloads computationally intensive tasks from the primary processor.
The first part of this thesis, which is devoted to FFT co-processors, proposes a new FFT architecture that uses a new Binary-Signed Digit (BSD) carry-limited adder, a new floating-point BSD multiplier and a new floating-point BSD three-operand adder. Finally, a new unit labeled as Fused-Dot-Product-Add (FDPA) is designed to compute AB+CD+E over floating-point BSD operands.
The second part of the thesis discusses decimal arithmetic operations implemented in hardware using redundant number systems. These operations are popularly used in decimal floating-point co-processors. A new signed-digit decimal adder is proposed along with a sequential decimal multiplier that uses redundant number systems to increase the operational frequency of the multiplier. New redundant decimal division and square-root units are also proposed.
The architectures proposed in this thesis were all implemented using Hardware-Description-Language (Verilog) and synthesized using Synopsys Design Compiler. The evaluation results prove the speed improvement of the new arithmetic units over previous pertinent works. Consequently, the FFT and decimal co-processors designed in this thesis work with at least 10% higher speed than that of previous works. These architectures are meant to fulfill the demand for the high-speed co-processors required in various applications such as multimedia services and financial computations.
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"Decimal Floating-point Fused Multiply Add with Redundant Number Systems." Thesis, 2013. http://hdl.handle.net/10388/ETD-2013-05-1044.
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The IEEE standard of decimal floating-point arithmetic was officially released in 2008. The new decimal floating-point (DFP) format and arithmetic can be applied to remedy the conversion error caused by representing decimal floating-point numbers in binary floating-point format and to improve the computing performance of the decimal processing in commercial and financial applications. Nowadays, many architectures and algorithms of individual arithmetic functions for decimal floating-point numbers are proposed and investigated (e.g., addition, multiplication, division, and square root). However, because of the less efficiency of representing decimal number in binary devices, the area consumption and performance of the DFP arithmetic units are not comparable with the binary counterparts.
IBM proposed a binary fused multiply-add (FMA) function in the POWER series of processors in order to improve the performance of floating-point computations and to reduce the complexity of hardware design in reduced instruction set computing (RISC) systems. Such an instruction also has been approved to be suitable for efficiently implementing not only stand-alone addition and multiplication, but also division, square root, and other transcendental functions. Additionally, unconventional number systems including digit sets and encodings have displayed advantages on performance and area efficiency in many applications of computer arithmetic.
In this research, by analyzing the typical binary floating-point FMA designs and the design strategy of unconventional number systems, ``a high performance decimal floating-point fused multiply-add (DFMA) with redundant internal encodings" was proposed. First, the fixed-point components inside the DFMA (i.e., addition and multiplication) were studied and investigated as the basis of the FMA architecture. The specific number systems were also applied to improve the basic decimal fixed-point arithmetic. The superiority of redundant number systems in stand-alone decimal fixed-point addition and multiplication has been proved by the synthesis results. Afterwards, a new DFMA architecture which exploits the specific redundant internal operands was proposed. Overall, the specific number system improved, not only the efficiency of the fixed-point addition and multiplication inside the FMA, but also the architecture and algorithms to build up the FMA itself.
The functional division, square root, reciprocal, reciprocal square root, and many other functions, which exploit the Newton's or other similar methods, can benefit from the proposed DFMA architecture. With few necessary on-chip memory devices (e.g., Look-up tables) or even only software routines, these functions can be implemented on the basis of the hardwired FMA function. Therefore, the proposed DFMA can be implemented on chip solely as a key component to reduce the hardware cost. Additionally, our research on the decimal arithmetic with unconventional number systems expands the way of performing other high-performance decimal arithmetic (e.g., stand-alone division and square root) upon the basic binary devices (i.e., AND gate, OR gate, and binary full adder). The proposed techniques are also expected to be helpful to other non-binary based applications.
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Kushnerov, Alexander. "High-Efficiency Self-Adjusting Switched Capacitor DC-DC Converter with Binary Resolution." Phd thesis, 2010. http://tel.archives-ouvertes.fr/tel-00507494.
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Switched-Capacitor Converters (SCC) suffer from a fundamental power loss deficiency which make their use in some applications prohibitive. The power loss is due to the inherent energy dissipation when SCC operate between or outside their output target voltages. This drawback was alleviated in this work by developing two new classes of SCC providing binary and arbitrary resolution of closely spaced target voltages. Special attention is paid to SCC topologies of binary resolution. Namely, SCC systems that can be configured to have a no-load output to input voltage ratio that is equal to any binary fraction for a given number of bits. To this end, we define a new number system and develop rules to translate these numbers into SCC hardware that follows the algebraic behavior. According to this approach, the flying capacitors are automatically kept charged to binary weighted voltages and consequently the resolution of the target voltages follows a binary number representation and can be made higher by increasing the number of capacitors (bits). The ability to increase the number of target voltages reduces the spacing between them and, consequently, increases the efficiency when the input varies over a large voltage range. The thesis presents the underlining theory of the binary SCC and its extension to the general radix case. Although the major application is in step-down SCC, a simple method to utilize these SCC for step-up conversion is also described, as well as a method to reduce the output voltage ripple. In addition, the generic and unified model is strictly applied to derive the SCC equivalent resistor, which is a measure of the power loss. The theoretical predictions are verified by simulation and experimental results.
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"Energy-efficient DSP System Design based on the Redundant Binary Number System." Master's thesis, 2011. http://hdl.handle.net/2286/R.I.9463.
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abstract: Redundant Binary (RBR) number representations have been extensively used in the past for high-throughput Digital Signal Processing (DSP) systems. Data-path components based on this number system have smaller critical path delay but larger area compared to conventional two's complement systems. This work explores the use of RBR number representation for implementing high-throughput DSP systems that are also energy-efficient. Data-path components such as adders and multipliers are evaluated with respect to critical path delay, energy and Energy-Delay Product (EDP). A new design for a RBR adder with very good EDP performance has been proposed. The corresponding RBR parallel adder has a much lower critical path delay and EDP compared to two's complement carry select and carry look-ahead adder implementations. Next, several RBR multiplier architectures are investigated and their performance compared to two's complement systems. These include two new multiplier architectures: a purely RBR multiplier where both the operands are in RBR form, and a hybrid multiplier where the multiplicand is in RBR form and the other operand is represented in conventional two's complement form. Both the RBR and hybrid designs are demonstrated to have better EDP performance compared to conventional two's complement multipliers. The hybrid multiplier is also shown to have a superior EDP performance compared to the RBR multiplier, with much lower implementation area. Analysis on the effect of bit-precision is also performed, and it is shown that the performance gain of RBR systems improves for higher bit precision. Next, in order to demonstrate the efficacy of the RBR representation at the system-level, the performance of RBR and hybrid implementations of some common DSP kernels such as Discrete Cosine Transform, edge detection using Sobel operator, complex multiplication, Lifting-based Discrete Wavelet Transform (9, 7) filter, and FIR filter, is compared with two's complement systems. It is shown that for relatively large computation modules, the RBR to two's complement conversion overhead gets amortized. In case of systems with high complexity, for iso-throughput, both the hybrid and RBR implementations are demonstrated to be superior with lower average energy consumption. For low complexity systems, the conversion overhead is significant, and overpowers the EDP performance gain obtained from the RBR computation operation.Dissertation/Thesis
M.S. Electrical Engineering 2011
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Wang, Yi-Jun, and 王奕竣. "High-Speed and Low-Cost Multipliers Based on Redundant Binary Signed-Digit Number System." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/61163206701815090452.
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碩士南台科技大學
電子工程系
91
Multiplication operations play an important role in many high-speed DSP and communication systems. For many practical applications, multiplication operations require the fixed-width result so that the n least-significant bits (LSBs) of 2n-bit product must be truncated. The fixed-width property can be applied to significantly reduce the area and power of multiplier by directly omitting about half the adder cells of the conventional multiplier, but an unacceptable product error might be introduced. Many efficient error compensation methods and structures were proposed to reduce the product error. However, most of them designed the fixed-width multiplier based on the Baugh-Wooley multiplier, and none gave attention to the redundant binary signed-digit (RBSD) multiplier. In this thesis, we focus on the design of low-cost truncated RBSD multipliers reduce the area and power of multiplier as well as the whole system. Experimental results show that the proposed fixed-width RBSD multiplier has lower truncation error as compared with other proposed architectures while maintaining smaller area and lower power. Besides, we use our multiplier to realize a low-cost and high-utilization folded architecture for DCT (discrete cosine transform). The proposed VLSI architecture is described in Verilog HDL and synthesized by the Synopsys Design Compiler with 0.35um 1P4M CMOS technology. The gate count of it is 11040, and chip area is 1745×1734um2. Its operation clock frequency is about 57.8 MHz. Finally, a demo system is built by integrating an Altera FPGA chip implemented the proposed DCT with an 8051 microprocessor to verify the performance of our DCT circuit.
Books on the topic "Redundant number systems"
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Busacca, Maurizio, and Roberto Paladini. Collaboration Age. Venice: Fondazione Università Ca’ Foscari, 2020. http://dx.doi.org/10.30687/978-88-6969-424-0.
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Recently, public policies of urban regeneration have intensified and multiplied. They are being promoted with the aim to start social and economic dynamics within the local context which is subject to intervention. From the empirical analysis, we realise that such activities are mainly implemented by three subjects or by mixed coalitions (public institutions, actors of the third sector and companies). Within them, each player is moved by a multiplicity of interests and goals that go beyond their own nature – public interest, market and mutualism – and tend to redefine themselves, thus becoming hybrid forms of production of value (social, economic, cultural). By studying a number Italian and Catalan cases, this essay deals with the theory that, under specific conditions and configurations, a collaborative direction – of organization, production and design – would give life to successful procedures, even without the identification of a one-best-way. The collaboration is not simply a choice of operation, but a real production method which mobilises social resources to create hybrid solutions – between state, market and society – to complex issues that could not be faced solely with the use of the rationale of action of one among the three actors. In this framework, the systems of relations and interactions between players and shared capital become an essential condition for the success of every initiative of urban redevelopment, or failure thereof. Such initiatives are brought to life by the strategic role of individuals who foster connections as well as the dissemination of non-redundant information between social networks, and collective and individual actors which would otherwise be separated and barely able to communicate and collaborate with each other. In addition to the functions carried out by knowledge brokers, that have been extensively described in organisational studies and economic sociology, the aforementioned figures act as real social enzymes, that is to say, they handle the available information and function as catalysts of social processes of production of knowledge. Moreover, they increase the reaction speed, working on mechanisms which control the spontaneity.
Book chapters on the topic "Redundant number systems"
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Tay, Thian Fatt, and Chip-Hong Chang. "Fault-Tolerant Computing in Redundant Residue Number System." In Embedded Systems Design with Special Arithmetic and Number Systems, 65–88. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-49742-6_4.
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He, Yajuan, Jiaxing Yang, and Chip-Hong Chang. "Design and Evaluation of Booth-Encoded Multipliers in Redundant Binary Representation." In Embedded Systems Design with Special Arithmetic and Number Systems, 113–47. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-49742-6_6.
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Salehi, Mohammad, Florian Kriebel, Semeen Rehman, and Muhammad Shafique. "Power-Aware Fault-Tolerance for Embedded Systems." In Dependable Embedded Systems, 565–88. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_24.
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AbstractPower-constrained fault-tolerance has emerged as a key challenge in the deep sub-micron technology. Multi-/many-core chips can support different hardening modes considering variants of redundant multithreading (RMT). In dark silicon chips, the maximum number of cores that can simultaneously be powered-on (at the full performance level) is constrained by the thermal design power (TDP). The rest of the cores have to be power-gated (i.e., stay “dark”), or the cores have to operate at a lower performance level. It has been predicted that about 25–50% of a many-core chip can potentially be “dark.” In this chapter, a system-level power–reliability management technique is presented. The technique jointly considers multiple hardening modes at the software and hardware levels, each offering distinct power, reliability, and performance properties. Also, a framework for the system-level optimization is introduced which considers different power–reliability–performance management problems for many-core processors depending upon the target system and user constraints.
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Liew, T. H., L. L. Yang, and L. Hanzo. "Redundant Residue Number System Codes." In Turbo Coding, Turbo Equalisation and Space-Time Coding, 257–316. Chichester, UK: John Wiley & Sons, Ltd, 2004. http://dx.doi.org/10.1002/047085474x.ch8.
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Jaberipur, G. "Redundant Number System-Based Arithmetic Circuits." In Arithmetic Circuits for DSP Applications, 273–312. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2017. http://dx.doi.org/10.1002/9781119206804.ch8.
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Gapochkin, A. V. "Using Redundant Modular Codes of the Residual Number System for Error Detection and Correction." In Lecture Notes in Electrical Engineering, 653–63. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-71119-1_64.
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Leydesdorff, Loet. "Knowledge-Based Innovations and Social Coordination." In Qualitative and Quantitative Analysis of Scientific and Scholarly Communication, 1–35. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-59951-5_1.
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AbstractThree themes have been central to my research program: (1) the dynamics of science, tech-nology, and innovation; (2) the scientometric operationalization and measurement of these dynamics; and (3) the Triple Helix (TH) of university-industry-government relations. In this introductory chapter, I relate these three themes first from an autobiographical perspective to (i)) Luhmann’s sociological theory about meaning-processing in communications with (ii) information-theoretical operationalizations of the possible synergies in Triple-Helix relations, and with (iii) anticipation as a selection mechanism in cultural evolutions different from “natural selection.” Interacting selection mechanisms can drive the development of redundancy; that is, options that are available, but have not yet been used. An increasing number of options is crucial for the viability of innovation systems more than is past performance. A calculus of redundancy different from and complementary to information calculus is envisaged.
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Leydesdorff, Loet. "Evolutionary and Institutional Triple Helix Models." In Qualitative and Quantitative Analysis of Scientific and Scholarly Communication, 89–113. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-59951-5_5.
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AbstractThe institutional TH model focuses on relations of universities, industries, and governments in networks. Institutional arrangements develop over time along trajectories. The Triple-Helix metaphor of university-industry-government relations can also be elaborated into a neo-evolutionary model combining the vertical differentiation among the levels (in terms of relations, correlations, perspectives, and horizons of meaning) with the options for horizontal differentiation among the codes (e.g., markets, technologies, politics, etc., oper-ating in parallel). The neo-evolutionary model focuses on the interactions among selection mechanisms (markets, technologies, endowments) at the regime level. The historical and evolutionary dynamics feedback on each other. The relative weights of the historical versus evolutionary dynamics can be measured as a trade-off. Among three or more selection environments, synergy can be generated as redundancy on top of the aggregates of bilateral and unilateral contributions to the information flows. The number of new options available to an innovation system for realization may be as decisive for its survival more than the historical record of past performance.
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Le Bris, Arnaud, Nesrine Chehata, Xavier Briottet, and Nicolas Paparoditis. "Spectral Optimization of Airborne Multispectral Camera for Land Cover Classification: Automatic Feature Selection and Spectral Band Clustering." In Geographic Information Systems in Geospatial Intelligence. IntechOpen, 2020. http://dx.doi.org/10.5772/intechopen.88507.
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Hyperspectral imagery consists of hundreds of contiguous spectral bands. However, most of them are redundant. Thus a subset of well-chosen bands is generally sufficient for a specific problem, enabling to design adapted superspectral sensors dedicated to specific land cover classification. Related both to feature selection and extraction, spectral optimization identifies the most relevant band subset for specific applications, involving a band subset relevance score as well as a method to optimize it. This study first focuses on the choice of such relevance score. Several criteria are compared through both quantitative and qualitative analyses. To have a fair comparison, all tested criteria are compared to classic hyperspectral data sets using the same optimization heuristics: an incremental one to assess the impact of the number of selected bands and a stochastic one to obtain several possible good band subsets and to derive band importance measures out of intermediate good band subsets. Last, a specific approach is proposed to cope with the optimization of bandwidth. It consists in building a hierarchy of groups of adjacent bands, according to a score to decide which adjacent bands must be merged, before band selection is performed at the different levels of this hierarchy.
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Martinez-Garcia, Edgar Alonso, and José A. Aguilera. "Dynamic Modelling and Control of an Underactuated Quasi-Omnidireccional Hexapod." In Handbook of Research on Advanced Mechatronic Systems and Intelligent Robotics, 377–400. IGI Global, 2020. http://dx.doi.org/10.4018/978-1-7998-0137-5.ch016.
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This chapter presents the mechanical design, dynamic model, and walking control law of an insect-like, asymmetric hexapod robot. The proposed model is an original walking mechanism designed with three actuators to provide quasi-omnidirectionality. One of the motivational aims is to reduce the number of actuators preserving similar holonomy as compared to popular 18-servo redundant hexapods with three servos per leg. This work includes the Klann mechanism as limb, two-drive differential robot's control, one per lateral triplet of legs. The legs of a triplet are synchronized in speed with different rotary angles phase. In addition, the six limbs are synchronized with bidirectional yaw motion. The proposed mechanical design has one servo for limbs yawing, one for the right limbs triplet and one motor for the left triplet. Thus, quasi-omnidirectional mobility is achieved. Furthermore, a dynamic control law that governs the robot's mechanisms motion is deduced, with an Euler-Lagrange approach. Kinematic and dynamic results are validated through numerical simulations using a tripod gait.
Conference papers on the topic "Redundant number systems"
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Motha, Jason, Andrew Bainbridge-Smith, and Steve Weddell. "Cryptographic techniques in redundant number systems." In 2015 International Conference on Field Programmable Technology (FPT). IEEE, 2015. http://dx.doi.org/10.1109/fpt.2015.7393156.
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Phalakarn, Kittiphop, and Athasit Surarerks. "Alternative Redundant Residue Number System Construction with Redundant Residue Representations." In 2018 3rd International Conference on Computer and Communication Systems (ICCCS). IEEE, 2018. http://dx.doi.org/10.1109/ccoms.2018.8463305.
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Kaivani, Amir, and Seokbum Ko. "High-speed FFT processors based on redundant number systems." In 2014 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2014. http://dx.doi.org/10.1109/iscas.2014.6865615.
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Timarchi, Somayeh, Negar Akbarzadeh, and Amir Abbas Hamidi. "Maximally redundant high-radix Signed-Digit Residue Number System." In 2015 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS). IEEE, 2015. http://dx.doi.org/10.1109/cads.2015.7377785.
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Krishna, H., and KuoYu Lin. "New algorithms for correcting errors in redundant residue number systems." In Twenty-Third Asilomar Conference on Signals, Systems and Computers, 1989. IEEE, 1989. http://dx.doi.org/10.1109/acssc.1989.1200979.
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Jaberipur, G., B. Parhami, and M. Ghodsi. "A class of stored-transfer representations for redundant number systems." In Conference Record. Thirty-Fifth Asilomar Conference on Signals, Systems and Computers. IEEE, 2001. http://dx.doi.org/10.1109/acssc.2001.987701.
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Shugang Wei. "A new residue adder with redundant binary number representation." In 2008 Joint International IEEE Northeast Workshop on Circuits and Systems (NEWCAS) and TAISA Conference (NEWCAS-TAISA). IEEE, 2008. http://dx.doi.org/10.1109/newcas.2008.4606345.
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Cherukuri, Ravindrnath C., and Sos S. Agaian. "New normalized expansions for redundant number systems: adaptive data hiding techniques." In IS&T/SPIE Electronic Imaging, edited by Reiner Creutzburg and David Akopian. SPIE, 2010. http://dx.doi.org/10.1117/12.838916.
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Yatskiv, Vasyl, Serhii Kulyna, Pavlo Bykovyy, Taras Maksymyuk, and Anatoliy Sachenko. "Method of Reliable Data Storage Based on Redundant Residue Number System." In 2020 IEEE 5th International Symposium on Smart and Wireless Systems within the Conferences on Intelligent Data Acquisition and Advanced Computing Systems (IDAACS-SWS). IEEE, 2020. http://dx.doi.org/10.1109/idaacs-sws50031.2020.9297052.
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Sasao, Tsutomu, and Yukihiro Iguchi. "On the Complexity of Error Detection Functions for Redundant Residue Number Systems." In 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools. IEEE, 2008. http://dx.doi.org/10.1109/dsd.2008.25.
Full textReports on the topic "Redundant number systems"
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Butler, Jon T., and Tsutomu Sasao. Redundant Multiple-Valued Number Systems. Fort Belvoir, VA: Defense Technical Information Center, July 1997. http://dx.doi.org/10.21236/ada599946.
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