Relevant bibliographies by topics / Reference spur

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Reference spur'

Author: Grafiati
Published: 4 June 2021
Last updated: 3 February 2022

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Journal articles on the topic "Reference spur"

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Hirst, Peter M., and David C. Ferree. "Rootstock Effects on the Flowering of `Delicious' Apple. II. Nutritional Effects with Specific Reference to Phosphorus." Journal of the American Society for Horticultural Science 120, no. 6 (November 1995): 1018–24. http://dx.doi.org/10.21273/jashs.120.6.1018.

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In each of 3 years, vegetative spurs were sampled from l-year-old wood of `Starkspur Supreme Delicious' apple trees (Malus domestica Borkh.) growing on B.9, M.26 EMLA, M.7 EMLA, P.18, and seedling rootstocks. Mineral concentrations of spur leaves and bud apical meristems were determined, and related to spur bud development. The spur leaf P concentration decreased during the growing season each year, hut was unaffected by rootstock. Spur leaves of trees on B.9 rootstock had 30% higher Ca concentrations than trees on M.26 EMLA or seedling rootstocks. In each year, trees growing on M.26 EMLA rootstocks had the highest leaf Mg concentrations. Mineral concentrations were generally unrelated to spur leaf number, leaf area, leaf dry weight, or specific leaf weight. Phosphorus concentrations in spur bud apical meristems declined during two of the three growing seasons of the study and were unaffected by rootstock. Bud P concentration was weakly negatively related to bud diameter and bud appendage number in one year of the study. More vigorous spurs (as indicated by higher spur leaf number, leaf area, and leaf dry weight) had higher bud K levels during each year. No relationships between bud development and either spur leaf mineral concentration or bud apical meristem mineral levels were evident, suggesting that a direct role of mineral nutrition influenced by rootstock at the site of flower formation was unlikely.
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Jahangirzadeh, Sakineh, Amir Amirabadi, and Ali Farrokhi. "Low spur frequency synthesiser using randomly shifted reference spur to higher frequencies." International Journal of Electronics 107, no. 12 (May 27, 2020): 2044–67. http://dx.doi.org/10.1080/00207217.2020.1756448.

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Mandal, Debashis, Pradip Mandal, and Tarun Kanti Bhattacharyya. "Prediction of reference spur in frequency synthesisers." IET Circuits, Devices & Systems 9, no. 2 (March 2015): 131–39. http://dx.doi.org/10.1049/iet-cds.2014.0019.

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Wang, Xin Jie, and Tadeusz Kwasniewski. "A reduced reference spur multiplying delay-locked loop." International Journal of Circuit Theory and Applications 44, no. 8 (November 20, 2015): 1620–27. http://dx.doi.org/10.1002/cta.2176.

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Choi, Hyun-Woo, and Young-Shig Choi. "A Reference Spur Suppressed PLL with Two-Symmetrical Loops." Journal of the Institute of Electronics and Information Engineers 51, no. 5 (May 25, 2014): 99–105. http://dx.doi.org/10.5573/ieie.2014.51.5.099.

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Ko, Han-Gon, Woorham Bae, Gyu-Seob Jeong, and Deog-Kyoon Jeong. "Reference Spur Reduction Techniques for a Phase-Locked Loop." IEEE Access 7 (2019): 38035–43. http://dx.doi.org/10.1109/access.2019.2905767.

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Kamal, N., S. F. Al‐Sarawi, and D. Abbott. "Reference spur suppression technique using ratioed current charge pump." Electronics Letters 49, no. 12 (June 2013): 746–47. http://dx.doi.org/10.1049/el.2013.1010.

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Yu, Tao, Ping Yi Wang, Cheng Yu Yang, Gui Jing Gao, and Ji Sheng Zhang. "Experimental Study of Water Force Acting on Spur Dike." Advanced Materials Research 255-260 (May 2011): 3558–62. http://dx.doi.org/10.4028/www.scientific.net/amr.255-260.3558.

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The water forces acting on spur dike were systematically analyzed under the different influenced factors (flow discharge, water depth, bottom slope, length of spur dike). The results indicate that : ①the total pressure decreases with increasing flow, increases along with the water depth basically assumes the linearity to increase; ②the fluctuation pressure decreases along with the water depth and dike length increases, increases along with the discharge increases on each sampling points. The research results may not only be of great significance in understanding spur dike scour and destruction mechanism, but also provide a valuable reference for the design of spur dike.
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Elsayed, Mohamed M., Mohammed Abdul-Latif, and Edgar Sanchez-Sinencio. "A Spur-Frequency-Boosting PLL With a −74 dBc Reference-Spur Suppression in 90 nm Digital CMOS." IEEE Journal of Solid-State Circuits 48, no. 9 (September 2013): 2104–17. http://dx.doi.org/10.1109/jssc.2013.2266865.

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Li, Qian, Yi Bian, Zhi Ping Zhong, Gui Hua Liu, and Ying Chen. "Study on the Large Module Spur Gear Cold Forming Process by Means of Numerical Simulation." Advanced Materials Research 189-193 (February 2011): 2642–46. http://dx.doi.org/10.4028/www.scientific.net/amr.189-193.2642.

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The cold forging process of large module spur gear with four modules and 59mm breadth is performed by means of numerical simulation method. Two processes to forming such spur gears were compared by the simulation method, one is with the closed-die performing and extrusion in the finish-forging, the other is with divided-flow method in the finish-forging. Especially, the divided-flow method is analyzed in detail. The necessary reference and basis to realize practical cold precision forging process of spur gear with large modulus is provided eventually.
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Dissertations / Theses on the topic "Reference spur"

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Moon, Sung Tae. "Design of high performance frequency synthesizers in communication systems." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2329.

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Frequency synthesizer is a key building block of fully-integrated wireless communication systems. Design of a frequency synthesizer requires the understanding of not only the circuit-level but also of the transceiver system-level considerations. This dissertation presents a full cycle of the synthesizer design procedure starting from the interpretation of standards to the testing and measurement results. A new methodology of interpreting communication standards into low level circuit specifications is developed to clarify how the requirements are calculated. A detailed procedure to determine important design variables is presented incorporating the fundamental theory and non-ideal effects such as phase noise and reference spurs. The design procedure can be easily adopted for different applications. A BiCMOS frequency synthesizer compliant for both wireless local area network (WLAN) 802.11a and 802.11b standards is presented as a design example. The two standards are carefully studied according to the proposed standard interpretation method. In order to satisfy stringent requirements due to the multi-standard architecture, an improved adaptive dual-loop phase-locked loop (PLL) architecture is proposed. The proposed improvements include a new loop filter topology with an active capacitance multiplier and a tunable dead zone circuit. These improvements are crucial for monolithic integration of the synthesizer with no off-chip components. The proposed architecture extends the operation limit of conventional integerN type synthesizers by providing better reference spur rejection and settling time performance while making it more suitable for monolithic integration. It opens a new possibility of using an integer-N architecture for various other communication standards, while maintaining the benefit of the integer-N architecture; an optimal performance in area and power consumption.
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Hsiao, Sen-Wen. "Built-in test for performance characterization and calibration of phase-locked loops." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51790.

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The objective of this dissertation is to propose circuit architectures and techniques for built-in test and calibration of phase-locked loops. The design of phase-locked loops is first investigated to achieve a robust performance over process, temperature, voltage corners with minimum overhead. Different design techniques including adding loop programmability, increasing area efficiency, reducing noise immunity, and increasing frequency coverage are discussed. Secondly, built-in testing of phase-lock loops using sensors are proposed for loop dynamic parameters and reference spur. An integrator is designed to extract the subtle response from the system so that target parameters can be predicted. Different testing methodologies are applied different specification testing as well. Finally, an on chip phase-locked loop design is implemented for reference spur calibration. The phase-locked loop is designed with a programmable reference spur range. A static phase offset detector is included to identify the optimal setting of reference spur in the feedback system. The integrated jitter performance is improved by the calibration mechanism. The results of this thesis serve as an on-chip built-in self-test and self-calibration solution for embedded phase-locked loops in a high integration system.
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Pu, Xiao. "A bandwidth-enhanced fractional-N PLL through reference multiplication." Thesis, 2011. http://hdl.handle.net/2152/ETD-UT-2011-08-4149.

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The loop bandwidth of a fractional-N PLL is a desirable parameter for many applications. A wide bandwidth allows a significant attenuation of phase noise arising from the VCO. A good VCO typically requires a high Q LC oscillator. It is difficult to build an on-chip inductor with a high Q factor. In addition, a good VCO also requires a lot of power. Both these design challenges are relaxed with a wide loop bandwidth PLL. However a wide loop bandwidth reduces the effective oversampling ratio (OSR) between the update rate and loop bandwidth and makes quantization noise from the ΔΣ modulator a much bigger noise contributor. A wide band loop also makes the noise and linearity performance of the phase detector more significant. The key to successful implementation of a wideband fractional-N synthesizer is in managing jitter and spurious performance. In this dissertation we present a new PLL architecture for bandwidth extension or phase noise reduction. By using clock squaring buffers with built-in offsets, multiple clock edges are extracted from a single cycle of a sinusoidal reference and used for phase updates, effectively forming a reference frequency multiplier. A higher update rate enables a higher OSR which allows for better quantization noise shaping and makes a wideband fractional-N PLL possible. However since the proposed reference multiplier utilizes the magnitude information from a sinusoidal reference to obtain phases, the derived new edges tend to cluster around the zero-crossings and form an irregular clock. This presents a challenge in lock acquisition. We have demonstrated for the first time that an irregular clock can be used to lock a PLL. The irregularity of the reference clock is taken into account in the divider by adding a cyclic divide pattern along with the ΔΣ control bits, this forces the loop to locally match the incoming patterns and achieve lock. Theoretically this new architecture allows for a 6x increase in loop BW or a 24dB improvement in phase noise. One potential issue associated with the proposed approach is the degraded spurious performance due to PVT variations, which lead to unintended mismatches between the irregular period and the divider pattern. A calibration scheme was invented to overcome this issue. In simulation, the calibration scheme was shown to lower the spurs down to inherent spurs level, of which the total energy is much less than the integrated phase noise. A test chip for proof of concept is presented and measurements are carefully analyzed.
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Liao, Te-Wen, and 廖德文. "Low Reference-Spur and Low Phase-Noise Frequency Synthesizers for Wireless Communication Systems." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/86dfh4.

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博士
國立交通大學
電信工程研究所
101
Spur reduction and low phase noise techniques are proposed that allow integer-N frequency synthesizers to achieve high closed loop bandwidth and low output phase noise simultaneously. Three integer-N synthesizers are presented. These circuits are targeted for analog TV (ATV) and mobile WIMAX applications. Synthesizer design still remains one of the most challenge issues in the RF system because it must meet very stringent requirements, such as settling time, phase noise, reference feedthrough, etc. Several trade-offs exist in the synthesizer design. First, the settling time is largely determined by the loop bandwidth which is limited to approximately 1/10 of the reference frequency for the loop stability consideration. Second, the phase noise of the oscillator is reduced by the feedback loop only within the loop bandwidth. Finally, in order to suppress the reference spur, a small loop bandwidth is required. To solve all these trade-offs, we have proposed several new architectures adopting random pulsewidth matching, sub-sampling charge-pump, and randomly selected PFD to achieve low reference spur and low phase noise PLLs. The first one is the Random pulsewidth matching frequency synthesizer with sub-sampling charge pump. Measurement results of a prototype TSMC 90nm CMOS synthesizer show that the reference spur is suppressed by 35dB. These represent a new analysis technique that is useful in the characterization of integer-N frequency synthesizers. The other is a spur-reduction frequency synthesizer exploiting randomly selected PFD. The oscillator frequency is tunable between 2500~2700 MHz, phase noise is -105dBc/Hz @1 MHz offset, and the spurious tone is -72dBc. Finally, a low phase-noise ring VCO based frequency synthesizer with multi-phase over-sampling charge-pump is implemented. To achieve good phase noise performance with a simple design, the multi-phase over-sampling charge-pump and one-shot circuits to reduce ripples on the control voltage of the VCO provide a smooth spectrum. Measured results from a prototype by TSMC 0.18um CMOS technology show the phase noise below–100 dBc/Hz from 15 Hz to 100 KHz and–108 dBc/Hz with 1 MHz offset.
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Wang, Shun Min, and 王舜民. "Digital MDLL-based clock generator using random code to achieve low reference spur." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/02130033451681210929.

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Fu, Chu-Hao, and 傅祖晧. "A 5.2-GHz All-Digital Frequency Synthesizer Chip Design with Reference Spur Reduction Technique." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/51003733798257168482.

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碩士
國立臺灣科技大學
電子工程系
103
Because of the rapid development of wireless communication systems, PLL-based frequency synthesizers are widely used for the past few years. With the promotion in integrated circuit technology, advanced fabrication processes are very favorable for digital design. In an all-digital phase-locked loop, the analog charge pump circuit and loop filter are replaced by a digital loop filter. This proposed study not only reduces the chip area but also avoids the effect of process shrinks. Besides, a digital design is scalable, easy to redesign with process changes, and has the advantage of noise immunity. Nowadays, the market demand trends towards low power supply and small chip area design, and that further promotes development of all-digital designs. This thesis adopts TSMC 0.18 um CMOS processing to realize an all-digital 5.2 GHz frequency synthesizer with reference spur reduction technique. The proposed architecture adopts a phase detector which only transfers phase error information when phase error is detected and can reduce the updating frequency for DCO control code and achieves lower reference spur. The proposed frequency synthesizer operates with 1.8 V supply voltage for both analog and digital circuits. The measuring results show that when output frequency is 5.22 GHz, the output signal power is -8.03 dBm. After locking, the phase noise is -110.74 dBc/Hz@1 MHz and the power consumption is 16.2 mW, while the chip area is 0.901 × 0.935 mm2.
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Yang, Jia-lun, and 楊佳倫. "A 1-V 2.4-GHz Fractional-N Frequency Synthesizer Chip Design with Reference Spur Reduction Techniques." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/yty4mt.

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碩士
國立臺灣科技大學
電子工程系
102
In recent year, with the rapid growing of the wireless communication system, many of PLL architectures are created. Normally, the loop filter of a conventional PLL are using continuous-time passive loop filter, it needs a large capacitance to meet system requirements. And the control node of the VCO is directly connected to the loop filter that will introduce ripples. Usually deals with a tradeoff between the settling time and the magnitude of the reference sideband that appears at the PLL output. The first chip, we introduce a 2.4 GHz fractional-N frequency synthesizer architecture with a reference spur reduction technique. It adopts a sample-hold-reset loop filter to isolate the charge pump output node and the VCO control node, which has a better linearity of PFD and CP. It achieves low spur and low phase noise performance, and save the capacitance area while a narrow loop bandwidth is used. The proposed frequency synthesizer operates with 1 V supply voltage is fabricated in TSMC 0.18-μm CMOS process. Measured results shows a wide tuning range from 2.21 GHz to 2.52 GHz corresponding to a frequency tuning range of 13.1%, a phase noise of -117.1 dBc/Hz at 1 MHz offset from 2.4 GHz, a reference spur of -65 dBc, a power consumption of 15.2 mW and the with pads chip area is only 1.06 mm2. The second chip, we adopt a sub-sampling charge pump (SSCP) circuit and a randomly selected PFD to reduce reference spur. The frequency synthesizer randomizes the periodic ripples on the control voltage of the voltage controlled oscillator to reduce the reference spur at the output of the phase-locked loop. The SSCP circuit is also utilized to reduce ripples on the control voltage to achieve low spur level. The proposed frequency synthesizer operates with 1 V supply voltage is fabricated in TSMC 0.18-μm CMOS process. Measured results shows a wide tuning range from 2.235 GHz to 2.579 GHz corresponding to a frequency tuning range of 14.3%, a phase noise of -113.17 dBc/Hz at 1 MHz offset from 2.41 GHz, a reference spur of -70.4 dBc, a power consumption of 9 mW and the with pads chip area is only 0.695 mm2.
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Books on the topic "Reference spur"

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Dark places: The haunted house in film. London: Reaktion Books, 2008.

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Book chapters on the topic "Reference spur"

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Singh, Radhika, K. K. Abdul Majeed, and Umakanta Nanda. "Transmission Gate Based PFD Free of Glitches for Fast Locking PLL with Reduced Reference Spur." In Communications in Computer and Information Science, 404–14. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-5048-2_32.

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Wilson, D. M. "Spun (Slurry and Sol–Gel) Ceramic Fibers." In Reference Module in Materials Science and Materials Engineering. Elsevier, 2016. http://dx.doi.org/10.1016/b978-0-12-803581-8.02326-2.

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Cui, Dafu, Xing Chen, and Yujie Wang. "Detection of SARS-CoV Antigen via SPR Analytical Systems with Reference." In Biosensors. InTech, 2010. http://dx.doi.org/10.5772/7209.

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Apostolidis, Paul. "Desperate Responsibility." In The Fight For Time, 73–114. Oxford University Press, 2019. http://dx.doi.org/10.1093/oso/9780190459338.003.0003.

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The temporally inflected theme of “desperate responsibility” predominates when day laborers describe their incessant work searches and arbitrary treatment by employers. For day laborers, temporal uniformity fostered by anxiety about insufficient work mingles with extreme temporal discontinuity whenever jobs and employers’ demands shift. In a contradictory response, day laborers affirm a time-conscious work ethic of personal responsibility even while their self-avowed desperation precludes independent choice. This predicament reflects migrant workers’ exceptional exposure to neoliberal crises and the deportation regime. Yet desperate responsibility also references contradictions experienced by working people in general due to the postindustrial work ethic, affective labor, and digital work. As work bleeds into every waking moment while undergoing severe temporal fragmentation, workers are pressed to embrace responsibility freely under conditions that undermine capacities for free action. This critical-popular investigation thus spurs militant demands to end deportation and to reject the self-destructive temporalities of our contemporary work culture.
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"Island in the Stream: Oceanography and Fisheries of the Charleston Bump." In Island in the Stream: Oceanography and Fisheries of the Charleston Bump, edited by Douglas S. Vaughan, Charles S. Manooch III, and Jennifer C. Potts. American Fisheries Society, 2001. http://dx.doi.org/10.47886/9781888569230.ch6.

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<em> Abstract.</em>—The status of the wreckfish <em> Polyprion americanus </em>stock caught on the Blake Plateau in the southeastern United States Atlantic was analyzed by calibrated virtual population analysis (VPA) to estimate trends in fishing mortality and population (or stock) biomass. Calibration of the FADAPT VPA program was to fishery-dependent catch-per-unit effort (CPUE) for a range in assumed values for natural mortality (M). Age-length keys were developed from two aging studies of wreckfish (1988– 1992 and 1995–1998). Keys were developed annually (pooled across seasons to create three “annual” age-length keys to represent 1988–1990, 1991–1993, and 1994–1998) and seasonally (pooled across years to create three seasonal age-length keys to represent April–June, July–September, and October to end of fishing year on 15 January). Analyses based on both annual and seasonal catch matrices showed similar patterns and values, with the seasonal catch matrix producing slightly lower estimates of fishing mortality rates (F) and higher estimates of biological reference points based on F. Fishing mortality rates peaked in 1989, as did the maximum annual U.S. landings (4.2 million pounds). Subsequently, both landings and fishing mortality rates have generally declined. Although stock biomass has generally declined over the study period, recruitment at age 7 has risen since about 1994. Meanwhile, annual estimates of static spawning potential ratio (SPR), which are inversely related to F, have risen since 1994. Fishing mortality rates from recent low landings are at or near the South Atlantic Fishery Management Council’s threshold definition of overfishing (static SPR of 30%), while the process of rebuilding with improving recruitment appears to be underway. Concern persists because the assessment is based on the underlying assumption that wreckfish from the Blake Plateau form a single stock separate from the eastern North Atlantic and genetic evidence suggests the stock encompasses the entire North Atlantic.
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Wells, D. A. "LC Automation☆☆Change History: May 2014. DA Wells updated website URL links and updated manufacturer name changes – Varian was acquired by Agilent; MicroLiter Analytical, Inc., was sold and the sample preparation group was spun off as ITSP Solutions, Inc.; Merck KGaA acquired Millipore to become EMD Millipore. The source of the BioTrap 500 LC column was updated to Chrom Tech, USA." In Reference Module in Chemistry, Molecular Sciences and Chemical Engineering. Elsevier, 2014. http://dx.doi.org/10.1016/b978-0-12-409547-2.11051-0.

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Harding, Dennis. "Defining Issues." In Iron Age Hillforts in Britain and Beyond. Oxford University Press, 2012. http://dx.doi.org/10.1093/oso/9780199695249.003.0005.

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‘Hillfort’ is a term of convenience. It is widely recognized that the monuments in question are not restricted topographically to hills, and that their role may not have been primarily, and certainly not exclusively, for military defence. Nor are they restricted chronologically to the Iron Age, though during that period they are particularly prominent. The term came into general currency following the publication in 1931 of Christopher Hawkes’ paper, simply entitled ‘Hillforts’, in Antiquity, which also established their predominantly Iron Age date in Britain. Prior to that, Christison (1898) in Scotland had discussed ‘fortifications’, and Hadrian Allcroft (1908) for England had classified ‘earthwork’, both extending their studies into the Medieval period. But ‘hillfort’ for all its limitations has remained in general usage in Britain. Chronologically, this study is concerned with the ‘long Iron Age’; that is, including the post-Roman Iron Age in northern Britain especially, and with later Bronze Age antecedents. Geographically it is concerned with regional groups throughout Britain, but with further reference to Ireland, and in the wider context of relevant sites and developments in continental Europe. The key element of the sites under consideration is enclosure, physically or conceptually demarcating an area to which access is restricted or controlled. This may be achieved by rampart and ditch, stockade or fence, or by the incorporation of topographical and natural features such as cliff-edge or marsh. The scale of enclosing works may range from a relatively modest barrier to massive earthworks that reshape the landscape, and in structural morphology, from single palisade or bank to multiple lines, variously disposed. Topographically they may be located around hilltop contours, on cliffedge, ridge, or promontory, on spurs or hill slopes, in wetlands or spanning river bends, or across variable terrain. In area enclosed they may range from well under a hectare to 20 ha and more, with the territorial or terrain oppida of the late pre-Roman Iron Age attaining 300 ha or more. From size alone, therefore, we may infer a great diversity in the practical, social, and symbolic purposes that they may have served. At the smaller end of the scale, the distinction between hillforts and other enclosed settlements is sometimes a matter of subjective assessment, but otherwise their size and scale suggests that they were community sites, serving a social unit larger than a single family or household.
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Conference papers on the topic "Reference spur"

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Kamal, Noorfazila, Said Al-Sarawi, and Derek Abbott. "Accurate Reference Spur Estimation Using Behavioural Modelling." In 2012 3rd International Conference on Intelligent Systems, Modelling and Simulation (ISMS). IEEE, 2012. http://dx.doi.org/10.1109/isms.2012.105.

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Akhmetov, Denis B., and Alexander S. Korotkov. "The reference spur reduction technique for frequency synthesizers." In 2018 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus). IEEE, 2018. http://dx.doi.org/10.1109/eiconrus.2018.8317055.

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Kim, Hyojun, Jinwoo Sang, Hyunik Kim, Youngwoo Jo, Taeik Kim, Hojin Park, and Seong Hwan Cho. "14.4 A 5GHz −95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS." In 2015 IEEE International Solid- State Circuits Conference - (ISSCC). IEEE, 2015. http://dx.doi.org/10.1109/isscc.2015.7063024.

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Elsayed, Mohamed, Mohammed Abdul-Latif, and Edgar Sanchez-Sinencio. "A Spur-Frequency-Boosting PLL with a −74dBc reference-spur rejection in 90nm digital CMOS." In 2011 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE, 2011. http://dx.doi.org/10.1109/rfic.2011.5940706.

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Wang, Bo, Jinhai Zhang, and Edouard Ngoya. "A reference spur estimation method for integer-N PLLs." In 2013 IEEE 10th International Conference on ASIC (ASICON 2013). IEEE, 2013. http://dx.doi.org/10.1109/asicon.2013.6811884.

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Kamal, Noorfazila, Said Al-Sarawi, Neil H. E. Weste, and Derek Abbott. "A Phase-Locked Loop reference spur modelling using Simulink." In 2010 International Conference on Electronic Devices, Systems and Applications (ICEDSA). IEEE, 2010. http://dx.doi.org/10.1109/icedsa.2010.5503058.

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Ho, Cheng-Ru, and Mike Shuo-Wei Chen. "10.5 A digital PLL with feedforward multi-tone spur cancelation loop achieving −73dBc fractional spur and −110dBc Reference Spur in 65nm CMOS." In 2016 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2016. http://dx.doi.org/10.1109/isscc.2016.7417971.

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Abedi, Mostafa, and Javad Yavand Hasani. "A Fast Locking Phase-Locked Loop with Low Reference Spur." In 2018 Iranian Conference on Electrical Engineering (ICEE). IEEE, 2018. http://dx.doi.org/10.1109/icee.2018.8472594.

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Ali, Tamer A., Amr A. Hafez, Robert Drost, Ronald Ho, and Chih-Kong Ken Yang. "A 4.6GHz MDLL with −46dBc reference spur and aperture position tuning." In 2011 IEEE International Solid- State Circuits Conference - (ISSCC). IEEE, 2011. http://dx.doi.org/10.1109/isscc.2011.5746400.

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Seol, Ji-Hwan, Dennis Sylvester, David Blaauw, and Taekwang Jang. "A Reference Oversampling Digital Phase-Locked Loop with -240 dB FOM and -80 dBc Reference Spur." In 2019 Symposium on VLSI Circuits. IEEE, 2019. http://dx.doi.org/10.23919/vlsic.2019.8778010.

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