Relevant bibliographies by topics / Register Transfer Level Design

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  3. Books
  4. Book chapters
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Academic literature on the topic 'Register Transfer Level Design'

Author: Grafiati
Published: 4 June 2021
Last updated: 10 February 2022

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Journal articles on the topic "Register Transfer Level Design"

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Gupta, Rajesh, and Melvin A. Breuer. "Partial scan design of register-transfer level circuits." Journal of Electronic Testing 7, no. 1-2 (1995): 25–46. http://dx.doi.org/10.1007/bf00993312.

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Park, Nohbyung, and Fadi J. Kurdahi. "Register-Transfer Synthesis of Pipelined Data Paths." VLSI Design 2, no. 1 (January 1, 1994): 17–32. http://dx.doi.org/10.1155/1994/43564.

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We present a new approach to the problem of register-transfer level design optimization of pipelined data paths. The output of high level synthesis procedures, such as Sehwa, consists of a schedule of operations into time steps, and a fixed set of hardware operators. In order to obtain a register-transfer level design, we must assign operations to specific operators, values to registers, and finish the interconnections. We first perform module assignment with the goal of minimizing the interconnect requirements between RT-level components as a preprocessing procedure to the RT-level design. This will result in a smaller netlist which makes the design more compact and the design process more efficient. In addition to reducing the total number of interconnects, this approach will also reduce the total number of multiplexors in the design by eliminating unnecessary multiplexing at the inputs of shared modules. The interconnect sharing task is modeled as a constrained clique partitioning problem. We developed a fast and efficient polynomial time heuristic procedure to solve this problem. This procedure is 30–50 times faster than other existing heuristics while still producing better results for our purposes. Using this procedure, we can produce near optimal interconnect sharing schemes in a few seconds for most practical size pipelined designs. This efficient approach will enable designers to explore a larger portion of the design space and trade off various design parameters effectively.
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CHOO, Hau Sim, Chia Yee OOI, Michiko INOUE, Nordinah ISMAIL, Mehrdad MOGHBEL, and Chee Hoo KOK. "Register-Transfer-Level Features for Machine-Learning-Based Hardware Trojan Detection." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E103.A, no. 2 (February 1, 2020): 502–9. http://dx.doi.org/10.1587/transfun.2019eap1044.

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Viswanath, Vinod, and Jacob A. Abraham. "Automatic and Correct Register Transfer Level Annotations for Low Power Microprocessor Design." Journal of Low Power Electronics 8, no. 4 (August 1, 2012): 424–39. http://dx.doi.org/10.1166/jolpe.2012.1204.

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Choi, Jung Yun, Young Hwan Kim, and Kyoung-Rok Cho. "Backward Propagated Capacitance Model for Register Transfer Level Power Estimation." VLSI Design 12, no. 2 (January 1, 2001): 221–31. http://dx.doi.org/10.1155/2001/78456.

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We present a new approach to the power modeling of functional modules, referred to as the backward propagated capacitance model, for estimating the power consumption of VLSI systems that are described at the register transfer level (RTL). To construct the proposed model, we investigate the effect of the module's internal capacitance on power consumption at the gate level. Then, we store the effect in a library in terms of the equivalent input capacitance of the module. The equivalent input capacitance is used to compute the module's power without the lower level elaboration during the power analysis of the RTL system. In the experiment using benchmark functional modules, the proposed model showed the absolute modeling error of 1.39% on average. For the benchmark RTL systems, the proposed model exhibited the absolute error of 3.04% in power estimation on average. If signal characteristics deviate from the modeling condition, the modeling error may increase. Experimental results show that the modeling accuracy can be improved greatly by using a simple compensation method.
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Lingappan, Loganathan, and Niraj K. Jha. "Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, no. 7 (July 2007): 1339–45. http://dx.doi.org/10.1109/tcad.2006.888268.

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Kaijie Wu and R. Karri. "Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 3 (March 2006): 413–22. http://dx.doi.org/10.1109/tcad.2005.853694.

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Bucci, M., R. Luzzi, F. Menichelli, R. Menicocci, M. Olivieri, and A. Trifiletti. "Testing power-analysis attack susceptibility in register-transfer level designs." IET Information Security 1, no. 3 (2007): 128. http://dx.doi.org/10.1049/iet-ifs:20060112.

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Katkoori, Srinivas, and Ranga Vemuri. "Architectural Power Estimation Based on Behavior Level Profiling." VLSI Design 7, no. 3 (January 1, 1998): 255–70. http://dx.doi.org/10.1155/1998/93106.

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High level synthesis is the process of generating register transfer (RT) level designs from behavioral specifications. High level synthesis systems have traditionally taken into account such constraints as area, clock period and throughput time. Many high level synthesis systems [1] permit generation of many alternative RT level designs meeting these constraints in a relatively short time. If it is possible to accurately estimate the power consumption of RT level designs, then a low power design from among these alternatives can be selected.In this paper, we present an accurate power estimation technique for register transfer level designs generated by high level synthesis systems. The technique has four main aspects: (1) Each RT level component used in high level synthesis is characterized for average switched capacitance per input vector. This data is stored in the RT level component library. (2) Using user-specified stimuli, the given behavioral description is simulated and event activities of various operators and carriers are measured. Then, the behavioral specification is submitted to the synthesis system and a number of alternative RTL designs meeting speed, space and throughput rate constraints are generated. (3) Event activity of each component in an RT level design is estimated using the event activities measured at the time of behavior level profiling and the structure of the RTL design itself. (4) The event activities so obtained are then used to modulate the average switched capacitances of the respective RT level components to obtain an estimate the total switched capacitance of each component.Detailed power estimation procedures for the three different parts of RTL designs, namely, data path, controller and interconnect are presented. Experimental results obtained from a variety of designs show that the power estimates are within 3%–10% of the actual power measured by simulating the transistor level designs extracted from mask layouts.
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Ghosh, I., A. Raghunathan, and N. K. Jha. "A design-for-testability technique for register-transfer level circuits using control/data flow extraction." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17, no. 8 (1998): 706–23. http://dx.doi.org/10.1109/43.712102.

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Dissertations / Theses on the topic "Register Transfer Level Design"

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Niu, Xinwei. "System-on-a-Chip (SoC) based Hardware Acceleration in Register Transfer Level (RTL) Design." FIU Digital Commons, 2012. http://digitalcommons.fiu.edu/etd/888.

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Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools. Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. The contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods – central bus design and co-processor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced. Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs. Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption.
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Hämäläinen, J. (Joona). "Register-transfer-level power profiling for system-on-chip power distribution network design and signoff." Master's thesis, University of Oulu, 2019. http://jultika.oulu.fi/Record/nbnfioulu-201905141744.

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Abstract. This thesis is a study of how register-transfer-level (RTL) power profiling can help the design and signoff of power distribution network in digital integrated circuits. RTL power profiling is a method which collects RTL power estimation results to a single power profile which then can be analysed in order to find interesting time windows for specifying power distribution network design and signoff. The thesis starts with theory part. Complementary metal-oxide semiconductor (CMOS) inverter power dissipation is studied at first. Next, power distribution network structure and voltage drop problems are introduced. Voltage drop is demonstrated by using power distribution network impedance figures. Common on-chip power distribution network structure is introduced, and power distribution network design flow is outlined. Finally, decoupling capacitors function and impact on power distribution network impedance are thoroughly explained. The practical part of the thesis contains RTL power profiling flow details and power profiling flow results for one simulation case in one design block. Also, some methods of improving RTL power estimation accuracy are discussed and calibration with extracted parasitic is then used to get new set of power profiling time windows. After the results are presented, overall RTL power estimation accuracy is analysed and resulted time windows are compared to reference gate-level time windows. RTL power profiling result analysis shows that resulted time windows match the theory and RTL power profiling seems to be a promising method for finding time windows for power distribution network design and signoff.Rekisterisiirtotason tehoprofilointi järjestelmäpiirin tehonsiirtoverkon suunnittelussa ja verifioinnissa. Tiivistelmä. Tässä työssä tutkitaan, miten rekisterisiirtotason (RTL) tehoprofilointi voi auttaa digitaalisten integroitujen piirien tehonsiirtoverkon suunnittelussa ja verifioinnissa. RTL-tehoprofilointi on menetelmä, joka analysoi RTL-tehoestimoinnista saadusta tehokäyrästä hyödyllisiä aikaikkunoita tehonsiirtoverkon suunnitteluun ja verifiointiin. Työ alkaa teoriaosuudella, jonka aluksi selitetään, miten CMOS-invertteri kuluttaa tehoa. Seuravaksi esitellään tehonsiirtoverkon rakenne ja pahimmat tehonsiirtoverkon jännitehäviön aiheuttajat. Jännitehäviötä havainnollistetaan myös piirikaavioiden ja impedanssikäyrien avustuksella. Lisäksi integroidun piirin tehonsiirtoverkon suunnitteluvuo ja yleisin rakenne on esitelty. Lopuksi teoriaosuus käsittelee yksityiskohtaisesti ohituskondensaattoreiden toiminnan ja vaikutuksen tehonsiirtoverkon kokonaisimpedanssiin. Työn kokeellisessa osuudessa esitellään ensin tehoprofiloinnin vuo ja sen jälkeen vuon tulokset yhdelle esimerkkilohkolle yhdessä simulaatioajossa. Lisäksi tässä osiossa käsitellään RTL-tehoestimoinnin tarkkuutta ja tehdään RTL-tehoprofilointi loisimpedansseilla kalibroidulle RTL-mallille. Lopuksi RTL-tehoestimoinnin tuloksia ja saatuja RTL-tehoprofiloinnin aikaikkunoita analysoidaan ja verrataan porttitason mallin tuloksiin. RTL-tehoprofiloinnin tulosten analysointi osoittaa, että saatavat aikaikkunat vastaavat teoriaa ja että RTL-tehoprofilointi näyttää lupaavalta menetelmältä tehosiirtoverkon analysoinnin ja verifioinnin aikaikkunoiden löytämiseen.
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Makris, Georgios. "Transparency-based hierarchical testability analysis and test generation for register transfer level designs /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2001. http://wwwlib.umi.com/cr/ucsd/fullcit?p9997571.

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MANSOURI, NAZANIN. "AUTOMATED CORRECTNESS CONDITION GENERATION FOR FORMAL VERIFICATION OF SYNTHESIZED RTL DESIGNS." University of Cincinnati / OhioLINK, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=ucin982064542.

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Beckwith, Luke Parkhurst. "An Investigation of Methods to Improve Area and Performance of Hardware Implementations of a Lattice Based Cryptosystem." Thesis, Virginia Tech, 2020. http://hdl.handle.net/10919/100798.

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With continuing research into quantum computing, current public key cryptographic algorithms such as RSA and ECC will become insecure. These algorithms are based on the difficulty of integer factorization or discrete logarithm problems, which are difficult to solve on classical computers but become easy with quantum computers. Because of this threat, government and industry are investigating new public key standards, based on mathematical assumptions that remain secure under quantum computing. This paper investigates methods of improving the area and performance of one of the proposed algorithms for key exchanges, "NewHope." We describe a pipelined FPGA implementation of NewHope512cpa which dramatically increases the throughput for a similar design area. Our pipelined encryption implementation achieves 652.2 Mbps and a 0.088 Mbps/LUT throughput-to-area (TPA) ratio, which are the best known results to date, and achieves an energy efficiency of 0.94 nJ/bit. This represents TPA and energy efficiency improvements of 10.05× and 8.58×, respectively, over a non-pipelined approach. Additionally, we investigate replacing the large SHAKE XOF (hash) function with a lightweight Trivium based PRNG, which reduces the area by 32% and improves energy efficiency by 30% for the pipelined encryption implementation, and which could be considered for future cipher specifications.
Master of Science
Cryptography is prevalent in almost every aspect of our lives. It is used to protect communication, banking information, and online transactions. Current cryptographic protections are built specifically upon public key encryption, which allows two people who have never communicated before to setup a secure communication channel. However, due to the nature of current cryptographic algorithms, the development of quantum computers will make it possible to break the algorithms that secure our communications. Because of this threat, new algorithms based on principles that stand up to quantum computing are being investigated to find a suitable alternative to secure our systems. These algorithms will need to be efficient in order to keep up with the demands of the ever growing internet. This paper investigates four hardware implementations of a proposed quantum-secure algorithm to explore ways to make designs more efficient. The improvements are valuable for high throughput applications, such as a server which must handle a large number of connections at once.
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Makni, Mariem. "Un framework haut niveau pour l'estimation du temps d'exécution, des ressources matérielles et de la consommation d'énergie dans les accélérateurs à base de FPGA." Thesis, Valenciennes, 2018. http://www.theses.fr/2018VALE0042.

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Les systèmes embarqués sur puce (SoC: Systems-on-Chip) sont devenus de plus en plus complexes grâce à l’évolution de la technologie des circuits intégrés. Les applications récentes nécessitent des systèmes à haute performances. Les FPGAs (Field Programmable Gate Arrays) peuvent répondre à ces besoins. On retrouve ces FPGA dans de nombreux domaines d’application : systèmes embarqués, télécommunications, traitement du signal et des images, serveurs de calcul HPC, etc. De nombreux défis sont rencontrés par les concepteurs de ces applications, parmi lesquels : le développement des applications complexes, la vérification du code, la nécessité d’automatiser le processus de conception pour augmenter la productivité et satisfaire la contrainte du « time-to-market ». Récemment, la synthèse de haut niveau (ou HLS) est considérée comme une solution efficace pour résoudre ces défis en utilisant un niveau d’abstraction plus élevé. En effet, cette technique permet de transformer automatiquement une spécification du système en C, C++, systemC en une implémentation au niveau transfert de registre (ou RTL pour Register Transfer Level). Les outils de HLS offrent un espace de solutions avec un grand nombre d’optimisations possibles au niveau du code comme l’utilisation du dépliage de boucles, le flot de données et partitionnement des tableaux, etc. Le concepteur doit explorer toutes ces alternatives et mesurer les performances obtenues en termes de temps d’exécution, de ressources matérielles, et de consommation d’´energie. Dans ce travail de thèse, nous avons utilisé les accélérateurs matériels à base de FPGAs et nous avons développé l’outil HAPE. Ce dernier permet d’aider les concepteurs à estimer la performance, la surface et l’énergie pour diverses configurations au niveau du code source. L’approche proposée comprend quatre contributions principales : (i) Nous avons proposé un modèle analytique de haut niveau pour estimer le temps de communications et le temps d’exécution total (ii) nous avons proposé un modèle analytique pour estimer les différentes ressources du FPGAs (DSPs, LUTs, FFs, BRAMs), (iii) nous avons proposé un modèle analytique pour estimer la consommation d’énergie basé sur l’utilisation du matériel (BRAMs, FFs, LUTs, etc) en explorant l’espace de solutions pour les différentes optimisations, (iv) Nous avons enfin proposé un environnement de conception (HAPE) permettant l’exploration des 3 critères : temps, ressources matérielles et consommation de puissance. L’approche proposée dans cette thèse est basée sur une analyse dynamique du code exécutée pour extraire les dépendances des données. Cette approche augmente la précision dans l’estimation du : temps de communication, de la consommation des ressources matérielles et de la consommation d’énergie dans les accélérateurs à base de FPGA. HAPE permet d’estimer ces paramètres avec une erreur inférieure à 5% par rapport aux implémentations RTL
In recent years, the complexity of system-on-chip (SoC) designs has been dramatically increased. As a result, the increased demands for high performance and minimal power/area costs for embedded streaming applications need to find new emerged architectures. The trend towards FPGA-based accelerators is giving a great potential of computational power and performance required for diverse applications. The advantages of such architectures result from many sources. The most important advantage stems from more efficient adaptation to the various application needs. In fact, many compute-intensive applications demand different levels of processing capabilities and energy consumption trade-offs which may be satisfied by using FPGA-based accelerators. Current researches in performance, area and power analysis rely on register-transfer level (RTL) based synthesis flows to produce accurate estimates. However, complex hardware programming model (Verilog or VHDL) makes FPGA development a time-consuming process even as the time-to-market constraints continue to tighten. Such techniques not only require advanced hardware expertise and time but are also difficult to use, making large design space exploration and time-to-market costly. High-Level Synthesis (HLS) technology has been emerged in the last few years as a solution to address these problems and managing design complexity at a more abstract level. This technique aims to bridge the gap between the traditional RTL design process and the ever-increasing complexity of applications. The important advantage of HLS tools is the ability to automatically generate RTL implementations from high-level specifications (e.g., C/C++/SystemC). The HLS tools provide various optimization pragmas such as loop unrolling, loop pipelining, dataflow, array partitioning, etc. Unfortunately, the large design space resulting from the various combinations of pragmas makes exhaustive design space exploration prohibitively time-consuming with HLS tools. In addition, to thoroughly evaluate such architectures, designers must perform large design space exploration to understand the tradeoffs across the entire system, which is currently infeasible due to the lack of a fast simulation infrastructure for FPGA-based accelerators. Hence, there is a clear need for a pre-RTL and high-level framework to enable rapid design space exploration for FPGA-based accelerators
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Gent, Kelson Andrew. "High Quality Test Generation at the Register Transfer Level." Diss., Virginia Tech, 2016. http://hdl.handle.net/10919/73544.

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Integrated circuits, from general purpose microprocessors to application specific designs (ASICs), have become ubiquitous in modern technology. As our applications have become more complex, so too have the circuits used to drive them. Moore's law predicts that the number of transistors on a chip doubles every 18-24 months. This explosion in circuit size has also lead to significant growth in testing effort required to verify the design. In order to cope with the required effort, the testing problem must be approached from several different design levels. In particular, exploiting the Register Transfer Level for test generation allows for the use of relational information unavailable at the structural level. This dissertation demonstrates several novel methods for generating tests applicable for both structural and functional tests. These testing methods allow for significantly faster test generation for functional tests as well as providing high levels of fault coverage during structural test, typically outperforming previous state of the art methods. First, a semi-formal method for functional verification is presented. The approach utilizes a SMT-based bounded model checker in combination with an ant colony optimization based search engine to generate tests with high branch coverage. Additionally, the method is utilized to identify unreachable code paths within the RTL. Compared to previous methods, the experimental results show increased levels of coverage and improved performance. Then, an ant colony optimization algorithm is used to generate high quality tests for fault coverage. By utilizing co-simulation at the RTL and gate level, tests are generated for both levels simultaneously. This method is shown to reach previously unseen levels of fault coverage with significantly lower computational effort. Additionally, the engine was also shown to be effective for behavioral level test generation. Next, an abstraction method for functional test generation is presented utilizing program slicing and data mining. The abstraction allows us to generate high quality test vectors that navigate extremely narrow paths in the state space. The method reaches previously unseen levels of coverage and is able to justify very difficult to reach control states within the circuit. Then, a new method of fault grading test vectors is introduced based on the concept of operator coverage. Operator coverage measures the behavioral coverage in each synthesizable statement in the RTL by creating a set of coverage points for each arithmetic and logical operator. The metric shows a strong relationship with fault coverage for coverage forecasting and vector comparison. Additionally, it provides significant reductions in computation time compared to other vector grading methods. Finally, the prior metric is utilized for creating a framework of automatic test pattern generation for defect coverage at the RTL. This framework provides the unique ability to automatically generate high quality test vectors for functional and defect level testing at the RTL without the need for synthesis. In summary, We present a set of tools for the analysis and test of circuits at the RTL. By leveraging information available at HDL, we can generate tests to exercise particular properties that are extremely difficult to extract at the gate level.
Ph. D.
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Blumer, Aric David. "Register Transfer Level Simulation Acceleration via Hardware/Software Process Migration." Diss., Virginia Tech, 2007. http://hdl.handle.net/10919/29380.

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The run-time reconfiguration of Field Programmable Gate Arrays (FPGAs) opens new avenues to hardware reuse. Through the use of process migration between hardware and software, an FPGA provides a parallel execution cache. Busy processes can be migrated into hardware-based, parallel processors, and idle processes can be migrated out increasing the utilization of the hardware. The application of hardware/software process migration to the acceleration of Register Transfer Level (RTL) circuit simulation is developed and analyzed. RTL code can exhibit a form of locality of reference such that executing processes tend to be executed again. This property is termed executive temporal locality, and it can be exploited by migration systems to accelerate RTL simulation. In this dissertation, process migration is first formally modeled using Finite State Machines (FSMs). Upon FSMs are built programs, processes, migration realms, and the migration of process state within a realm. From this model, a taxonomy of migration realms is developed. Second, process migration is applied to the RTL simulation of digital circuits. The canonical form of an RTL process is defined, and transformations of HDL code are justified and demonstrated. These transformations allow a simulator to identify basic active units within the simulation and combine them to balance the load across a set of processors. Through the use of input monitors, executive locality of reference is identified and demonstrated on a set of six RTL designs. Finally, the implementation of a migration system is described which utilizes Virtual Machines (VMs) and Real Machines (RMs) in existing FPGAs. Empirical and algorithmic models are developed from the data collected from the implementation to evaluate the effect of optimizations and migration algorithms.
Ph. D.
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Hernandez, Anna C. "Implementing and Comparing Image Convolution Methods on an FPGA at the Register-Transfer Level." Digital WPI, 2019. https://digitalcommons.wpi.edu/etd-theses/1340.

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Whether it's capturing a car's license plate on the highway or detecting someone's facial features to tag friends, computer vision and image processing have found their way into many facets of our lives. Image and video processing algorithms ultimately tailor towards one of two goals: to analyze data and produce output in as close to real-time as possible, or to take in and operate on large swaths of information offline. Image convolution is a mathematical method with which we can filter an image to highlight or make clearer desired information. The most popular uses of image convolution accentuate edges, corners, and facial features for analysis. The goal of this project was to investigate various image convolution algorithms and compare them in terms of hardware usage, power utilization, and ability to handle substantial amounts of data in a reasonable amount of time. The algorithms were designed, simulated, and synthesized for the Zynq-7000 FPGA, selected both for its flexibility and low power consumption.
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Haataja, M. (Miikka). "Register-transfer level power estimation and reduction methodologies of digital system-on-chip building blocks." Master's thesis, University of Oulu, 2016. http://urn.fi/URN:NBN:fi:oulu-201603231342.

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This thesis is a study of register-transfer level power estimation and reduction methodologies for digital system-on-chip building blocks. In the theory section, the components of power dissipation for current circuit technology are explained in details, the commonly implemented register-transfer level power estimation methodologies are classified and explained, and finally, commonly used power reduction methods used in system-on-chip development are presented. In the implementation part of this thesis, register-transfer level power estimation and power reduction methodologies with a state-of-the-art commercial register-transfer level power tool are presented. Results obtained with these methodologies are analyzed for three different system-on-chip building blocks. The experimental results of power estimation accuracy and power saving estimates are presented. The average deviation between register-transfer level and gate-level power estimation were 11%, and potential total power saving estimates were between 10% and 29%
Tässä työssä tutkitaan rekisterinsiirtotason tehonkulutuksen arviointi- ja vähennysmenetelmiä digitaalisille järjestelmäpiirilohkoille. Teoriaosuudessa esitetään tehonkulutuksen eri komponentit nykyiselle piiriteknologialle, luokitellaan yleisimmät rekisterinsiirtotasolla käytettävät tehonkulutuksen arviointimenetelmät sekä kuvataan yleisesti digitaalisten järjestelmäpiirien suunnittelussa käytettyjä tehonvähennysmenetelmiä. Kokeellisessa osassa kuvataan rekisterinsiirtotason tehonkulutuksen arviointi- ja vähennysmenetelmä käyttäen kaupallista rekisterinsiirtotason tehotyökalua. Menetelmiä testataan kolmella digitaalisella järjestelmäpiirilohkolla ja saatuja tuloksia analysoidaan tehonkulutuksen arvion tarkkuuden ja tehonvähennyksen arvioiden kannalta. Näiden kolmen järjestelmäpiirilohkon tulokset tehonkulutuksen ja tehonvähennyksen arviosta on esitetty. Rekisterisiirtotason tehonarviointi poikkesi keskimäärin 11 % porttitason vertailuarviosta, ja potentiaaliset tehonvähennysarviot olivat väliltä 10–29 %
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Books on the topic "Register Transfer Level Design"

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Register transfer level (RTL) hardware design using VHDL. Hoboken, NJ: J. Wiley & Sons, 2006.

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Thomas, D. E. Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench. Boston, MA: Springer US, 1990.

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Nelson, Victor P. 74AS-EVM-16: A microprogramming approach to application-specific instruction set processor design : register-transfer level design : laboratory manual no. 1. Dallas, TX: Texas Instruments, 1987.

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Nelson, Victor P. 74AS-EVM-16: A microprogramming approach to application-specific instruction set processor design : register-transfer level design : laboratory manual no. 1. Dallas, TX: Texas Instruments, 1987.

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Thomas, D. E., E. D. Lagnese, R. A. Walker, J. A. Nestor, J. V. Rajan, and R. L. Blackburn. Algorithmic and Register-Transfer Level Synthesis: The System Architect’s Workbench. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-1519-3.

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1951-, Thomas D. E., ed. Algorithmic and register-transfer level synthesis: The system architect's workbench. Boston: Kluwer Academic Publishers, 1990.

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Thomas, Donald E., Elizabeth D. Lagnese, Robert A. Walker, Jayanth V. Rajan, John A. Nestor, and Robert L. Blackburn. Algorithmic and Register-Transfer Level Synthesis: The System Architect's Workbench (The International Series in Engineering and Computer Science). Springer, 1989.

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Standard for VHDL Register Transfer Level (Rtl) Synthesis. Institute of Electrical & Electronics Enginee, 2000.

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IEEE Standard for Verilog Register Transfer Level Synthesis. [S.l.]: [s.n.], 2002.

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Standard for VHDL Register Transfer Level (Rtl) Synthesis. Institute of Electrical & Electronics Enginee, 2000.

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Book chapters on the topic "Register Transfer Level Design"

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Vollmer, Harald, and Norbert Wehn. "Register-Transfer Level Synthesis." In The Synthesis Approach to Digital System Design, 87–114. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3632-1_5.

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Singh, Dilip, and Rajeevan Chandel. "Register-Transfer-Level Design for Application-Specific Integrated Circuits." In Energy Systems in Electrical Engineering, 295–319. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-7937-0_15.

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Salmani, Hassan. "Design Techniques for Hardware Trojans Prevention and Detection at the Register-Transfer Level." In Trusted Digital Circuits, 31–38. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-79081-7_3.

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Herdt, Vladimir, Daniel Große, and Rolf Drechsler. "Register-Transfer Level Correspondence Analysis." In Enhanced Virtual Prototyping, 205–29. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-54828-5_8.

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Sambamurthy, Sriram, Jacob A. Abraham, and Raghuram S. Tupuri. "Delay Constrained Register Transfer Level Dynamic Power Estimation." In Lecture Notes in Computer Science, 36–46. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11847083_4.

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Stamelos, I., and C. Halatsis. "Efficient Test Generation for Register Transfer Level Descriptions." In Fehlertolerierende Rechensysteme / Fault-Tolerant Computing Systems, 141–52. Berlin, Heidelberg: Springer Berlin Heidelberg, 1987. http://dx.doi.org/10.1007/978-3-642-45628-2_13.

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Salmani, Hassan. "Circuit Vulnerabilities to Hardware Trojans at the Register-Transfer Level." In Trusted Digital Circuits, 13–29. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-79081-7_2.

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Pandita, Bupesh. "Architectural-Level Design of the Experimental ΔΣ Modulator." In Oversampling A/D Converters with Improved Signal Transfer Functions, 87–123. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4614-0275-6_4.

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Reimer, Axel, Lars Kosmann, Daniel Lorenz, and Wolfgang Nebel. "Fast Propagation of Hamming and Signal Distances for Register-Transfer Level Datapaths." In Lecture Notes in Computer Science, 62–71. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-36157-9_7.

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Machado, Felipe, Teresa Riesgo, and Yago Torroja. "Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level." In Lecture Notes in Computer Science, 399–408. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-540-95948-9_40.

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Conference papers on the topic "Register Transfer Level Design"

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Muttreja, Anish, Srivaths Ravi, and Niraj K. Jha. "Variability-Tolerant Register-Transfer Level Synthesis." In 21st International Conference on VLSI Design (VLSID 2008). IEEE, 2008. http://dx.doi.org/10.1109/vlsi.2008.114.

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Karfa, Chandan, Ramanuj Chouksey, Christian Pilato, Siddharth Garg, and Ramesh Karri. "Is Register Transfer Level Locking Secure?" In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2020. http://dx.doi.org/10.23919/date48585.2020.9116261.

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Navarro, Hector, Saeid Nooshabadi, Juan A. Montiel-Nelson, V. Navarro, J. Sosa, and Jose C. Garcia. "A geometric approach to register transfer level satisfiability." In 2009 10th International Symposium on Quality of Electronic Design (ISQED). IEEE, 2009. http://dx.doi.org/10.1109/isqed.2009.4810306.

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Raghavan, N., V. Akella, and S. Bakshi. "Automatic insertion of gated clocks at register transfer level." In Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013). IEEE, 1999. http://dx.doi.org/10.1109/icvd.1999.745123.

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Chih-Neng Chung, Chia-Wei Chang, Kai-Hui Chang, and Sy-Yen Kuo. "Formal reset recovery slack calculation at the register transfer level." In 2011 Design, Automation & Test in Europe. IEEE, 2011. http://dx.doi.org/10.1109/date.2011.5763286.

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Pawlovsky, A. P., and S. Naito. "Verification of register transfer level (RTL) designs." In Proceedings Pacific Rim International Symposium on Fault Tolerant Systems. IEEE, 1991. http://dx.doi.org/10.1109/rfts.1991.212969.

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Zhang, Jie, and Qiang Xu. "On hardware Trojan design and implementation at register-transfer level." In 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST). IEEE, 2013. http://dx.doi.org/10.1109/hst.2013.6581574.

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Motohara, Akira, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, and Michiaki Muraoka. "Design for testability using register-transfer level partial scan selection." In the 1995 conference. New York, New York, USA: ACM Press, 1995. http://dx.doi.org/10.1145/224818.224900.

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R, Aarthi, Aishwarya C, Akash M. U, Krupasankar P, Yadukrishnan G, and Anita J. P. "Property Driven Design based Verification for Register Transfer Level Hardware." In 2021 6th International Conference on Communication and Electronics Systems (ICCES). IEEE, 2021. http://dx.doi.org/10.1109/icces51350.2021.9489148.

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Iwata, Hiroyuki, Tomokazu Yoneda, and Hideo Fujiwara. "A DFT Method for Time Expansion Model at Register Transfer Level." In 2007 44th ACM/IEEE Design Automation Conference. IEEE, 2007. http://dx.doi.org/10.1109/dac.2007.375251.

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Reports on the topic "Register Transfer Level Design"

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Adams, Sunny E., Megan W. Tooker, and Adam D. Smith. Fort McCoy, Wisconsin WWII buildings and landscapes. Engineer Research and Development Center (U.S.), November 2020. http://dx.doi.org/10.21079/11681/38679.

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Abstract:
The U.S. Congress codified the National Historic Preservation Act of 1966 (NHPA) mostly through the National Register of Historic Places (NRHP), which requires federal agencies to address their cultural resources. Section 110 of the NHPA requires federal agencies to inventory and evaluate their cultural resources, and Section 106 requires them to determine the effect of federal undertakings on those potentially eligible for the NRHP. This report provides a World War II development history and analysis of 786 buildings, and determinations of eligibility for those buildings, on Fort McCoy, Wisconsin. Evaluation of the WWII buildings and landscape concluded that there are too few buildings with integrity to form a cohesive historic district. While the circulation patterns and roads are still intact, the buildings with integrity are scattered throughout the cantonment affecting the historic character of the landscape. Only Building 100 (post headquarters), Building 656 (dental clinic), and Building 550 (fire station) are ELIGIBLE for listing on the NRHP at the national level under Criterion A for their association with World War II temporary building construction (1942-1946) and under Criterion C for their design, construction, and technological innovation.
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Design assessment for Melton Valley liquid low-level waste collection and transfer system upgrade project at Oak Ridge National Laboratory, Oak Ridge, Tennessee. Office of Scientific and Technical Information (OSTI), October 1994. http://dx.doi.org/10.2172/10107777.

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Design/Installation and Structural Integrity Assessment of Bethel Valley Low-Level Waste Collection and transfer system upgrade for Building 2649 (Transported Waste Receiving Facility) at Oak Ridge National Laboratory. Office of Scientific and Technical Information (OSTI), January 1995. http://dx.doi.org/10.2172/30459.

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Design/installation and structural integrity assessment of Bethel Valley low-level waste collection and transfer system upgrade for Building 3092 (Central Off-Gas Scrubber Facility) at Oak Ridge National Laboratory. Office of Scientific and Technical Information (OSTI), January 1995. http://dx.doi.org/10.2172/34316.

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Design/Installation and Structural Integrity Assessment of Bethel Valley Low-Level Waste collection and transfer system upgrade for Building 3092 (central off-gas scrubber facility) at Oak Ridge National Laboratory. Office of Scientific and Technical Information (OSTI), October 1994. http://dx.doi.org/10.2172/10192712.

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Design/installation and structural integrity assessment under the Federal Facility Agreement for Bethel Valley low-level waste collection and transfer system upgrade for Building 2026 (High Radiation Level Analytical Laboratory) and Building 2099 (Monitoring and Control Station) at Oak Ridge National Laboratory. Office of Scientific and Technical Information (OSTI), November 1994. http://dx.doi.org/10.2172/10107787.

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Design/installation and structural integrity assessment under the Federal Facility Agreement for Bethel Valley Low-Level Waste Collection and Transfer System upgrade for Building 2026 (High Radiation Level Analytical Laboratory) and Building 2099 (Monitoring and Control Station) at Oak Ridge National Laboratory. Office of Scientific and Technical Information (OSTI), October 1994. http://dx.doi.org/10.2172/10191015.

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Design/Installation and Structural Integrity Assessment of the Bethel Valley Low-Level Waste Collection and Transfer System Upgrade for Building 3544 (Process Waste Treatment Plant) at Oak Ridge National Laboratory, Oak Ridge, Tennessee. Office of Scientific and Technical Information (OSTI), December 1996. http://dx.doi.org/10.2172/481381.

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