Journal articles: 'Register Transfer Level Design'

1

Gupta, Rajesh, and Melvin A. Breuer. "Partial scan design of register-transfer level circuits." Journal of Electronic Testing 7, no. 1-2 (1995): 25–46. http://dx.doi.org/10.1007/bf00993312.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Park, Nohbyung, and Fadi J. Kurdahi. "Register-Transfer Synthesis of Pipelined Data Paths." VLSI Design 2, no. 1 (January 1, 1994): 17–32. http://dx.doi.org/10.1155/1994/43564.

Full text

Abstract:

We present a new approach to the problem of register-transfer level design optimization of pipelined data paths. The output of high level synthesis procedures, such as Sehwa, consists of a schedule of operations into time steps, and a fixed set of hardware operators. In order to obtain a register-transfer level design, we must assign operations to specific operators, values to registers, and finish the interconnections. We first perform module assignment with the goal of minimizing the interconnect requirements between RT-level components as a preprocessing procedure to the RT-level design. This will result in a smaller netlist which makes the design more compact and the design process more efficient. In addition to reducing the total number of interconnects, this approach will also reduce the total number of multiplexors in the design by eliminating unnecessary multiplexing at the inputs of shared modules. The interconnect sharing task is modeled as a constrained clique partitioning problem. We developed a fast and efficient polynomial time heuristic procedure to solve this problem. This procedure is 30–50 times faster than other existing heuristics while still producing better results for our purposes. Using this procedure, we can produce near optimal interconnect sharing schemes in a few seconds for most practical size pipelined designs. This efficient approach will enable designers to explore a larger portion of the design space and trade off various design parameters effectively.

APA, Harvard, Vancouver, ISO, and other styles

3

CHOO, Hau Sim, Chia Yee OOI, Michiko INOUE, Nordinah ISMAIL, Mehrdad MOGHBEL, and Chee Hoo KOK. "Register-Transfer-Level Features for Machine-Learning-Based Hardware Trojan Detection." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E103.A, no. 2 (February 1, 2020): 502–9. http://dx.doi.org/10.1587/transfun.2019eap1044.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

Viswanath, Vinod, and Jacob A. Abraham. "Automatic and Correct Register Transfer Level Annotations for Low Power Microprocessor Design." Journal of Low Power Electronics 8, no. 4 (August 1, 2012): 424–39. http://dx.doi.org/10.1166/jolpe.2012.1204.

Full text

APA, Harvard, Vancouver, ISO, and other styles

5

Choi, Jung Yun, Young Hwan Kim, and Kyoung-Rok Cho. "Backward Propagated Capacitance Model for Register Transfer Level Power Estimation." VLSI Design 12, no. 2 (January 1, 2001): 221–31. http://dx.doi.org/10.1155/2001/78456.

Full text

Abstract:

We present a new approach to the power modeling of functional modules, referred to as the backward propagated capacitance model, for estimating the power consumption of VLSI systems that are described at the register transfer level (RTL). To construct the proposed model, we investigate the effect of the module's internal capacitance on power consumption at the gate level. Then, we store the effect in a library in terms of the equivalent input capacitance of the module. The equivalent input capacitance is used to compute the module's power without the lower level elaboration during the power analysis of the RTL system. In the experiment using benchmark functional modules, the proposed model showed the absolute modeling error of 1.39% on average. For the benchmark RTL systems, the proposed model exhibited the absolute error of 3.04% in power estimation on average. If signal characteristics deviate from the modeling condition, the modeling error may increase. Experimental results show that the modeling accuracy can be improved greatly by using a simple compensation method.

APA, Harvard, Vancouver, ISO, and other styles

6

Lingappan, Loganathan, and Niraj K. Jha. "Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, no. 7 (July 2007): 1339–45. http://dx.doi.org/10.1109/tcad.2006.888268.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

Kaijie Wu and R. Karri. "Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 3 (March 2006): 413–22. http://dx.doi.org/10.1109/tcad.2005.853694.

Full text

APA, Harvard, Vancouver, ISO, and other styles

8

Bucci, M., R. Luzzi, F. Menichelli, R. Menicocci, M. Olivieri, and A. Trifiletti. "Testing power-analysis attack susceptibility in register-transfer level designs." IET Information Security 1, no. 3 (2007): 128. http://dx.doi.org/10.1049/iet-ifs:20060112.

Full text

APA, Harvard, Vancouver, ISO, and other styles

9

Katkoori, Srinivas, and Ranga Vemuri. "Architectural Power Estimation Based on Behavior Level Profiling." VLSI Design 7, no. 3 (January 1, 1998): 255–70. http://dx.doi.org/10.1155/1998/93106.

Full text

Abstract:

High level synthesis is the process of generating register transfer (RT) level designs from behavioral specifications. High level synthesis systems have traditionally taken into account such constraints as area, clock period and throughput time. Many high level synthesis systems [1] permit generation of many alternative RT level designs meeting these constraints in a relatively short time. If it is possible to accurately estimate the power consumption of RT level designs, then a low power design from among these alternatives can be selected.In this paper, we present an accurate power estimation technique for register transfer level designs generated by high level synthesis systems. The technique has four main aspects: (1) Each RT level component used in high level synthesis is characterized for average switched capacitance per input vector. This data is stored in the RT level component library. (2) Using user-specified stimuli, the given behavioral description is simulated and event activities of various operators and carriers are measured. Then, the behavioral specification is submitted to the synthesis system and a number of alternative RTL designs meeting speed, space and throughput rate constraints are generated. (3) Event activity of each component in an RT level design is estimated using the event activities measured at the time of behavior level profiling and the structure of the RTL design itself. (4) The event activities so obtained are then used to modulate the average switched capacitances of the respective RT level components to obtain an estimate the total switched capacitance of each component.Detailed power estimation procedures for the three different parts of RTL designs, namely, data path, controller and interconnect are presented. Experimental results obtained from a variety of designs show that the power estimates are within 3%–10% of the actual power measured by simulating the transistor level designs extracted from mask layouts.

APA, Harvard, Vancouver, ISO, and other styles

10

Ghosh, I., A. Raghunathan, and N. K. Jha. "A design-for-testability technique for register-transfer level circuits using control/data flow extraction." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17, no. 8 (1998): 706–23. http://dx.doi.org/10.1109/43.712102.

Full text

APA, Harvard, Vancouver, ISO, and other styles

11

Thaker, P. A., V. D. Agrawal, and M. E. Zaghloul. "A test evaluation technique for vlsi circuits using register-transfer level fault modeling." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22, no. 8 (August 2003): 1104–13. http://dx.doi.org/10.1109/tcad.2003.814958.

Full text

APA, Harvard, Vancouver, ISO, and other styles

12

Rajmohan, V., and O. Uma Maheswari. "Improved Baugh Wooley Multiplier Using Cadence Register Transfer Level Logic for Power Consumption." Journal of Computational and Theoretical Nanoscience 14, no. 1 (January 1, 2017): 277–83. http://dx.doi.org/10.1166/jctn.2017.6317.

Full text

Abstract:

In modern days of VLSI design, speedy operations and low-power consumption is a key requirement for any circuits. When it comes to multipliers, the power efficient multiplier plays an important role. The main aim of this work is to develop the system with faster and less power multiplier for an efficient process by using Baugh-Wooley multipliers. The optimized Baugh-Wooley multiplier consumes least power, area and produces less delay. The proposed architecture is 193× times faster than Conventional array multiplier in the practical applications and 213× times faster than a conventional Baugh-Wooley multiplier. The Improved Baugh-Wooley multiplier consumes the power of 09.02 mW and area of 52426 μm2.

APA, Harvard, Vancouver, ISO, and other styles

13

Pattunnarajam, P., and Beulah Jackson. "Analysis of 32 × 32-Bit Parallel Pipeline Multiplier Using In-Built Register Transfer Level Testing Approach." Journal of Computational and Theoretical Nanoscience 17, no. 4 (April 1, 2020): 1804–11. http://dx.doi.org/10.1166/jctn.2020.8444.

Full text

Abstract:

This paper presents a design and implementation of Fixed Point Ultra High Throughput Multiplier (UHTM) using parallel pipeline architecture for both signed and unsigned numbers to improve the throughput of the VLSI SoC design. Here backend issues are addressed in the front end RTL design itself hence this reduces the testing time by detecting all possible defects. In this paper RTL coding style is realized with respect to FPGA design. In an FPGA design inbuilt DSP blocks is used for arithmetic (multiplication) operations which will achieve the higher frequency of operation. In addition power and timing optimization techniques are also addressed to reduce dynamic power. The multiplier hardware design of 32×32 bit UHTM is synthesized in FPGA and compared with the previous works. As a result of this, 32×32 multiplier achieves the throughput of 15552 Mbps at 243 MHz, 64 bits per clock cycle output in FPGA and 32 Gbps at 1.2 GHz, 64 bits per clock cycle in ASIC, obtains the best hardware efficiency in terms of area in the FPGA area utilization of 1264 ALUTs, 2811 FFs in the Cyclone V5CSXFC6D6F3117 device with First in First out latency of ten clock cycles at the rate of 243 MHz clock frequency. The Structural realization and analysis pertaining to timing, area and power are implemented in Cyclone V 5CSXFC6D6F3117 FPGA and ASIC 28 nm technology.

APA, Harvard, Vancouver, ISO, and other styles

14

Sabur, Fatmawati, and Ucok Sinaga. "Design Trainer Analysis Spectrum Analyzer Based on Raspberry Python and Register Transfer Level - Software Defined Radio." Airman: Jurnal Teknik dan Keselamatan Transportasi 3, no. 2 (February 4, 2021): 1–8. http://dx.doi.org/10.46509/ajtkt.v3i2.69.

Full text

Abstract:

communication network. However, the high purchase price of a Spectrum Analyzer means that not everyone can afford it. One solution to overcome this problem is to make a piece of hardware capable of performing the same performance as a Spectrum Analyzer but at a relatively cheaper price. Prototype Spectrum Analyzer to be implemented is a device capable of displaying the spectrum of a signal in a certain frequency range. This engineering was carried out from July to October 2020 at the Makassar Aviation Polytechnic Campus and testing tools with a comparison tool was carried out at Otban Region V Makassar. The technique or method used in data collection is the library method by collecting some written data from books, literature, and tutorials on the internet, as reference material and then analyzing solutions that can be taken in solving problems. From the results of tests carried out by using RTL-SDR on the Single Board Computer (SBC), Raspberry pi can display the frequency spectrum whether it is done singly or applied to the network so that it can be used as a learning medium for wireless technology practice or other materials that measure frequency From sergi, the performance of the trainer spectrum analyzer with the use of raspberry pi as a device for processing radio / wireless signals is quite good at utilization with CLI mode (command line interface) but is relatively slow when used on the desktop as a portable spectrum analyzer that can be used as a learning medium

APA, Harvard, Vancouver, ISO, and other styles

15

Dutt, Nikil D., and Pradip K. Jha. "RT Component Sets for High-Level Design Applications." VLSI Design 5, no. 2 (January 1, 1997): 155–65. http://dx.doi.org/10.1155/1997/35614.

Full text

Abstract:

The system-level design process typically involves refining a design specification down to the point where each of the system's components is described as a block diagram or netlist of abstract Register-Transfer (RT) level components. In this paper, we motivate the need for such a standard RT component set, and describe a library environment that supports automatic model generation, design reuse, and synthesis with technology-specific estimators. We demonstrate the efficacy of the standard RT-component set approach with experiments performed on the HLSW92 benchmarks. Our preliminary results indicate only a small overhead of about 10% in using these standard, generic components. We then describe an automatic model generation and technology projection scheme that uses fast (on-line) estimators for predicting the area and delay of generic RT components tuned to a particular technology library with an accuracy of 10%. These model generators and estimators have been integrated with a high-level synthesis system at U.C. Irvine.

APA, Harvard, Vancouver, ISO, and other styles

16

Zhang, Peng Fei. "Formal Specification of RTL-Level Digital System Using Projection Temporal Logic." Applied Mechanics and Materials 719-720 (January 2015): 949–55. http://dx.doi.org/10.4028/www.scientific.net/amm.719-720.949.

Full text

Abstract:

An approach to specify a RTL-level system using Projection Temporal Logic (PTL) is proposed in this paper. With this approach, a digital system described with Register Transfer Language can be translated into PTL formulae, and properties of the system can be specified by PTL either. Then MSVL(Modeling, Simulation and Verification Language) can be used for detecting the error of the design formally.

APA, Harvard, Vancouver, ISO, and other styles

17

Fujiwara, Hideo, Hiroyuki Iwata, Tomokazu Yoneda, and Chia Yee Ooi. "A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27, no. 9 (September 2008): 1535–44. http://dx.doi.org/10.1109/tcad.2008.927757.

Full text

APA, Harvard, Vancouver, ISO, and other styles

18

Bravo, Ignacio, César Vázquez, Alfredo Gardel, José L. Lázaro, and Esther Palomar. "High Level Synthesis FPGA Implementation of the Jacobi Algorithm to Solve the Eigen Problem." Mathematical Problems in Engineering 2015 (2015): 1–11. http://dx.doi.org/10.1155/2015/870569.

Full text

Abstract:

We present a hardware implementation of the Jacobi algorithm to compute the eigenvalue decomposition (EVD). The computation of eigenvalues and eigenvectors has many applications where real time processing is required, and thus hardware implementations are often mandatory. Some of these implementations have been carried out with field programmable gate array (FPGA) devices using low level register transfer level (RTL) languages. In the present study, we used the Xilinx Vivado HLS tool to develop a high level synthesis (HLS) design and evaluated different hardware architectures. After analyzing the design for different input matrix sizes and various hardware configurations, we compared it with the results of other studies reported in the literature, concluding that although resource usage may be higher when HLS tools are used, the design performance is equal to or better than low level hardware designs.

APA, Harvard, Vancouver, ISO, and other styles

19

Varga, László, Gábor Hosszú, and Ferenc Kovács. "Design Procedure Based on VHDL Language Transformations." VLSI Design 14, no. 4 (January 1, 2002): 349–54. http://dx.doi.org/10.1080/10655140290011159.

Full text

Abstract:

One of the major problems within the VHDL based behavioral synthesis is to start the design on higher abstraction level than the register transfer level (RTL). VHDL semantics was designed strictly for simulation, therefore it was not considered as high-level synthesis language. A novel synthesis procedure was developed, which uses the methodology of high level synthesis. It starts from an abstract VHDL model and produces an RTL VHDL description through successive language transformations while preserving the VHDL standard simulation semantics. The steps of the synthesis do not use graph representation or other meta-language, but apply the standard VHDL only. This VHDL representation is simulatable and accessible, functional verification can be performed by simulation at any time, and the simulation results can be used to guide the synthesis process. The output VHDL format is suitable to continue the design flow with RTL based synthesis tools.

APA, Harvard, Vancouver, ISO, and other styles

20

Moon, Sangook, and Jongsu Park. "System Level Design of Reconfigurable Server Farms Using Elliptic Curve Cryptography Processor Engines." Journal of Applied Mathematics 2014 (2014): 1–8. http://dx.doi.org/10.1155/2014/390176.

Full text

Abstract:

As today’s hardware architecture becomes more and more complicated, it is getting harder to modify or improve the microarchitecture of a design in register transfer level (RTL). Consequently, traditional methods we have used to develop a design are not capable of coping with complex designs. In this paper, we suggest a way of designing complex digital logic circuits with a soft and advanced type of SystemVerilog at an electronic system level. We apply the concept of design-and-reuse with a high level of abstraction to implement elliptic curve crypto-processor server farms. With the concept of the superior level of abstraction to the RTL used with the traditional HDL design, we successfully achieved the soft implementation of the crypto-processor server farms as well as robust test bench code with trivial effort in the same simulation environment. Otherwise, it could have required error-prone Verilog simulations for the hardware IPs and other time-consuming jobs such as C/SystemC verification for the software, sacrificing more time and effort. In the design of the elliptic curve cryptography processor engine, we propose a 3X faster GF(2m) serial multiplication architecture.

APA, Harvard, Vancouver, ISO, and other styles

21

Tatas, K., K. Siozios, A. Bartzas, C. Kyriacou, and D. Soudris. "A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC." International Journal of Adaptive, Resilient and Autonomic Systems 4, no. 3 (July 2013): 1–24. http://dx.doi.org/10.4018/jaras.2013070101.

Full text

Abstract:

This paper presents a framework for high-level exploration, Register Transfer-Level (RTL) design and rapid prototyping of Network-on-Chip (NoC) architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking testbenches for the verification of the RTL and architecture files for the semi-automatic implementation of the system in Xilinx EDK are also generated, significantly reducing design and verification time, and therefore Non-Recurring Engineering (NRE) cost. Simulation and FPGA implementation results are given for four case studies multimedia applications, proving the validity of the proposed approach.

APA, Harvard, Vancouver, ISO, and other styles

22

SINHA, SHARAD, UDIT DHAWAN, and THAMBIPILLAI SRIKANTHAN. "EXTENDED COMPATIBILITY PATH BASED HARDWARE BINDING: AN ADAPTIVE ALGORITHM FOR HIGH LEVEL SYNTHESIS OF AREA-TIME EFFICIENT DESIGNS." Journal of Circuits, Systems and Computers 23, no. 09 (August 25, 2014): 1450131. http://dx.doi.org/10.1142/s021812661450131x.

Full text

Abstract:

Hardware binding is an important step in high level synthesis (HLS). The quality of hardware binding affects the area-time efficiency of a design. The goal of a synthesis process is to produce a design which meets the area-time requirements. In this paper, we present a new hardware binding algorithm with focus on area reduction. It is called extended compatibility path-based (ECPB) hardware binding and extends the compatibility path-based (CPB) hardware binding method by exploiting inter-operation flow dependencies, non-overlapping lifetimes of variables and modifying the weight relation in order to make it application aware and thus adaptive in nature. The presented methodology also takes into account bit width of functional units (FUs) and multi mode FUs. It performs simultaneous FU and register binding. Implemented within a C to register transfer level (RTL) framework, it produces binding results which are better than those produced by weighted bipartite matching (WBM) and CPB algorithms. The use of ECPB algorithm results in an average reduction of 34% and 17.44% in area-time product over WBM and CPB methods, respectively.

APA, Harvard, Vancouver, ISO, and other styles

23

Huang, Lan, Teng Gao, Dalin Li, Zihao Wang, and Kangping Wang. "A Highly Configurable High-Level Synthesis Functional Pattern Library." Electronics 10, no. 5 (February 25, 2021): 532. http://dx.doi.org/10.3390/electronics10050532.

Full text

Abstract:

FPGA has recently played an increasingly important role in heterogeneous computing, but Register Transfer Level design flows are not only inefficient in design, but also require designers to be familiar with the circuit architecture. High-level synthesis (HLS) allows developers to design FPGA circuits more efficiently with a more familiar programming language, a higher level of abstraction, and automatic adaptation of timing constraints. When using HLS tools, such as Xilinx Vivado HLS, specific design patterns and techniques are required in order to create high-performance circuits. Moreover, designing efficient concurrency and data flow structures requires a deep understanding of the hardware, imposing more learning costs on programmers. In this paper, we propose a set of functional patterns libraries based on the MapReduce model, implemented by C++ templates, which can quickly implement high-performance parallel pipelined computing models on FPGA with specified simple parameters. The usage of this pattern library allows flexible adaptation of parallel and flow structures in algorithms, which greatly improves the coding efficiency. The contributions of this paper are as follows. (1) Four standard functional operators suitable for hardware parallel computing are defined. (2) Functional concurrent programming patterns are described based on C++ templates and Xilinx HLS. (3) The efficiency of this programming paradigm is verified with two algorithms with different complexity.

APA, Harvard, Vancouver, ISO, and other styles

24

Kung, Ying Shieh, Nguyen Phan Thanh, and Hsin Hung Chou. "Design and Implementation of a Microprocessor-Based PI Controller for PMSM Drives." Applied Mechanics and Materials 764-765 (May 2015): 496–500. http://dx.doi.org/10.4028/www.scientific.net/amm.764-765.496.

Full text

Abstract:

This work presents a hardware implementation of a simple microprocessor; then uses this microprocessor to design a PI controller for PMSM (Permanent Magnet Synchronous Motor) drives. In this paper, firstly, the mathematical model of PMSM drives is illustrated. Secondly, the architecture of a simple microprocessor based on RTL (Register Transfer Level) method is proposed and the VHDL (Very high speed IC Hardware Description Language) is adopted to describe the behavior of the simple microprocessor. Thirdly, a machine code of PI controller based on the proposed simple microprocessor is designed. Finally, a co-simulation by Simulink/ModelSim is applied and verified the performance of the microprocessor-based PI controller.

APA, Harvard, Vancouver, ISO, and other styles

25

Gray, Michael A. "An intelligent design machine: architecture and search strategies." Artificial Intelligence for Engineering Design, Analysis and Manufacturing 2, no. 2 (May 1988): 105–22. http://dx.doi.org/10.1017/s0890060400000597.

Full text

Abstract:

In this report the architecture of an intelligent design machine capable of performing routine design in different design domains is described. This machine is crafted to operate as a part of a larger system driven by a human designer. Notable features are its use of best-first search strategies for problem-solving control and its ability to adjust problem-solving control strategies, perform automated redesign following specification changes, and resolve constraint violations using domain knowledge. The claims made for this machine are analyzed and it is argued that these claims are founded on established principles of design for intelligent systems. An implementation of this architecture in a rule-based system named Proteus is discussed and its operation is examined using as an example the domain of register-transfer-level computer design.

APA, Harvard, Vancouver, ISO, and other styles

26

Silveira, George Sobral, Alisson V. Brito, Helder F. de A. Oliveira, and Elmar U. K. Melcher. "Open SystemC Simulator with Support for Power Gating Design." International Journal of Reconfigurable Computing 2012 (2012): 1–8. http://dx.doi.org/10.1155/2012/793190.

Full text

Abstract:

Power gating is one of the most efficient power consumption reduction techniques. However, when applied in several different parts of a complex design, functional verification becomes a challenge. Lately, the verification process of this technique has been executed in a Register-Transfer Level (RTL) abstraction, based on the Common Power Format (CPF) and the Unified Power Format (UPF). The purpose of this paper is to present an OSCI SystemC simulator with support to the power gating design. This simulator is an alternative to assist the functional verification accomplishment of systems modeled in RTL. The possibility of controlling the retention and isolation of power gated functional block (PGFB) is presented in this work, turning the simulations more stable and accurate. Two case studies are presented to demonstrate the new features of that simulator.

APA, Harvard, Vancouver, ISO, and other styles

27

CHIANG, TSUNG-HSI, and LAN-RONG DUNG. "VERIFICATION OF DATAFLOW SCHEDULING." International Journal of Software Engineering and Knowledge Engineering 18, no. 06 (September 2008): 737–58. http://dx.doi.org/10.1142/s0218194008003891.

Full text

Abstract:

This paper presents the formal verification method for high-level synthesis (HLS) to detect design errors of dataflow algorithms by using Petri Net (PN) and symbolic-model-verifier (SMV) techniques. Formal verification in high-level design means architecture verification, which is different from functional verification in register transfer level (RTL). Generally, dataflow algorithms need algorithmic transformations to achieve optimal goals and also need design scheduling to allocate processor resources before mapping on a silicon. However, algorithmic transformations and design scheduling are error-prone. In order to detect high-level faults, high-level verification is applied to verify the synthesis results in HLS. Instead of applying Boolean algebra in traditional verification, this paper adopts both Petri Net theory and SMV model checker to verify the correctness of the synthesis results of the high-level dataflow designs. In the proposed hybrid verification method, a high-level design or DUV (design-under-verification) is first transformed into a Petri Net model. Then, Petri Net theory is applied to check the correctness of its algorithmic transformations of HLS, and the SMV model checker is used to verify the correctness of the design scheduling. We presented two approaches to realize the proposed verification method and concluded the best one who outperforms the other in terms of processing speed and resource usage.

APA, Harvard, Vancouver, ISO, and other styles

28

Ameur, Noura Ben, Nouri Masmoudi, and Mourad Loulou. "FPGA-Based Design Δ–Σ Audio D/A Converter with a Resolution Clock Generator Enhancement Circuit." Journal of Circuits, Systems and Computers 24, no. 03 (February 10, 2015): 1550037. http://dx.doi.org/10.1142/s0218126615500371.

Full text

Abstract:

This paper, focus on synthesis design of a Δ–Σ digital-to-analog converter (DAC) algorithm intended for professional digital audio. A rapid register-transfer-level (RTL) using a top-down design method with VHSIC hardware description language (VHDL) is practiced. All the RTL design simulation, VHDL implementation and field programmable gate array (FPGA) verification are rapidly and systematically performed through the methodology. A distributed pipelining, streaming and resource sharing design are considered for area and speed optimization while maintaining the original precision of the audio DAC. The features of the design are high-precision, fast processing and low-cost. The related work is done with the MATLAB & QUARTUS II simulators.

APA, Harvard, Vancouver, ISO, and other styles

29

Pogra, Vivek, Amandeep Singh, Santosh Kumar Vishvakarma, and Balwinder Raj. "Design and Performance Analysis of Application Specific Integrated Circuit for Internet of Things Applications." Sensor Letters 18, no. 9 (September 1, 2020): 700–705. http://dx.doi.org/10.1166/sl.2020.4239.

Full text

Abstract:

This paper proposes a novel design of application specific integrated circuit (ASIC) which is capable of connecting sensor network and other electronic systems to the internet. The transfer of data between different networks and electronic systems is controlled by internet of things (IoT) platform with the help of instruction sent to ASIC. ASIC will act as serial peripheral interface (SPI) master to all connected networks and data will be transferred serially between them. The different ASIC modules are SPI module, control module, memory module and data/instruction decoder with additional modules built-in self-test (BIST) and direct memory access (DMA). The proposed ASIC will consume less power as compared to conventional microcontroller/microprocessor due to SPI feature along with DMA on ASIC for IoT applications. It is described in very high speed integrated circuit hardware description language (VHDL) at register transfer level (RTL) and simulation is done on the Vivado 2016.2.

APA, Harvard, Vancouver, ISO, and other styles

30

Obert, James, and Tom J. Mannos. "ASIC STA Path Verification Using Semi-Supervised Learning." International Journal of Semantic Computing 13, no. 02 (June 2019): 229–44. http://dx.doi.org/10.1142/s1793351x19400105.

Full text

Abstract:

To counter manufacturing irregularities and ensure ASIC design integrity, it is essential that robust design verification methods are employed. It is possible to ensure such integrity using ASIC static timing analysis (STA) and machine learning. In this research, uniquely devised machine and statistical learning methods which quantify anomalous variations in Register Transfer Level (RTL) or Graphic Design System II (GDSII) format are discussed. To measure the variations in ASIC analysis data, the timing delays in relation to path electrical characteristics are explored. It is shown that semi-supervised learning techniques are powerful tools in characterizing variations within STA path data and have much potential for identifying anomalies in ASIC RTL and GDSII design data.

APA, Harvard, Vancouver, ISO, and other styles

31

Reyes Fernandez de Bulnes, Darian, Yazmin Maldonado, and Leonardo Trujillo. "Development of Multiobjective High-Level Synthesis for FPGAs." Scientific Programming 2020 (June 29, 2020): 1–25. http://dx.doi.org/10.1155/2020/7095048.

Full text

Abstract:

Traditionally, the High-Level Synthesis (HLS) for Field Programmable Gate Array (FPGA) devices is a methodology that transforms a behavioral description, as the timing-independent specification, to an abstraction level that is synthesizable, like the Register Transfer Level. This process can be performed under a framework that is known as Design Space Exploration (DSE), which helps to determine the best design by addressing scheduling, allocation, and binding problems, all three of which are NP-hard problems. In this manner, and due to the increased complexity of modern digital circuit designs and concerns regarding the capacity of the FPGAs, designers are proposing novel HLS techniques capable of performing automatic optimization. HLS has several conflicting metrics or objective functions, such as delay, area, power, wire length, digital noise, reliability, and security. For this reason, it is suitable to apply Multiobjective Optimization Algorithms (MOAs), which can handle the different trade-offs among the objective functions. During the last two decades, several MOAs have been applied to solve this problem. This paper introduces a comprehensive analysis of different MOAs that are suitable to perform HLS for FPGA devices. We highlight significant aspects of MOAs, namely, optimization methods, intermediate structures where the optimizations are performed, HLS techniques that are addressed, and benchmarks and performance assessments employed for experimentation. In addition, we show the analysis of how multiple objectives are optimized currently in the algorithms and which are the objective functions that are optimized. Finally, we provide insights and suggestions to contribute to the solution of major research challenges in this area.

APA, Harvard, Vancouver, ISO, and other styles

32

Sato, Tomoaki, Sorawat Chivapreecha, Phichet Moungnoul, and Kohji Higuchi. "RCA on FPGAs Designed by RTL Design Methodology and Wave-Pipelined Operation." ECTI Transactions on Computer and Information Technology (ECTI-CIT) 11, no. 1 (May 9, 2017): 10–19. http://dx.doi.org/10.37936/ecti-cit.2017111.65680.

Full text

Abstract:

Field-programmable gate arrays (FPGAs) are used in various systems with reconfigurable functions. Conventional FPGAs have been developed using a transistor level description for minimizing routing delay. Although FPGAs developed with a register transfer level (RTL) design methodology provide various benefits to the designers of a system-on-a-chip (SoC), they have not been realized. Therefore, the authors advanced their development. They should be shown to operate with practical throughput. For this purpose, circuits on these device need to be designed and evaluated. In this paper, a ripple-carry adder (RCA) was designed and the throughput of the RCA was evaluated. The resulting throughput was applicable to network processors. Additionally, a wave-pipelined operation without changing the RCA revealed that the problem of routing delay in FPGA developed by RTL methodology was mitigated. The contributions of this paper are to clarify that a 4-bit adder can be implemented on FPGAs and their throughput can be improved by wave-pipelined operations.

APA, Harvard, Vancouver, ISO, and other styles

33

Haririan, Parham. "DVFS and Its Architectural Simulation Models for Improving Energy Efficiency of Complex Embedded Systems in Early Design Phase." Computers 9, no. 1 (January 7, 2020): 2. http://dx.doi.org/10.3390/computers9010002.

Full text

Abstract:

Dealing with resource constraints is an inevitable feature of embedded systems. Power and performance are the main concerns beside others. Pre-silicon analysis of power and performance in today’s complex embedded designs is a big challenge. Although RTL (Register-Transfer Level) models are more precise and reliable, system-level modeling enables the power and performance analysis of complex and dense designs in the early design phase. Virtual prototypes of systems prepared through architectural simulation provide a means of evaluating non-existing systems with more flexibility and minimum cost. Efficient interplay between power and performance is a key feature within virtual platforms. This article focuses on dynamic voltage and frequency scaling (DVFS), which is a well-known system-level low-power design technique together with its more efficient implementations modeled through architectural simulation. With advent of new computing paradigms and modern application domains with strict resource demands, DVFS and its efficient hardware-managed solutions get even more highlighted. This is mainly because they can react faster to resource demands and thus reduce induced overhead. To that end, they entail an effective collaboration between software and hardware. A case review in the end wraps up the discussed topics.

APA, Harvard, Vancouver, ISO, and other styles

34

Huang, May, Raymond Kwok, and Shu-park Chan. "An Empirical Algorithm for Power Analysis in Deep Submicron Electronic Designs." VLSI Design 14, no. 2 (January 1, 2002): 219–27. http://dx.doi.org/10.1080/10655140290010123.

Full text

Abstract:

An empirical algorithm applied to logic level power analysis in deep submicron VLSI designs is introduced in the paper. The method explores a static analysis strategy using unit functions to represent signal transitions. It can be extended to the use of a Register Transfer Level (RTL) power analysis after RTL codes are translated to Boolean equations. A new method for representing state-dependent power models is also introduced in the paper to reduce the complexity of power modeling and to improve the performance of power analysis. The modeling method supports not only the empirical power analysis, but also general simulation-based power analysis methods.

APA, Harvard, Vancouver, ISO, and other styles

35

Fan, Quan Run, and Feng Pan. "Technology Mapping for Heterogeneous FPGA in Different EDA Stages." Applied Mechanics and Materials 229-231 (November 2012): 1866–69. http://dx.doi.org/10.4028/www.scientific.net/amm.229-231.1866.

Full text

Abstract:

In traditional EDA flow, Technology mapping is performed after logic synthesis. Besides programmable logic blocks, heterogeneous FPGAs also have some hard blocks, such as memory block and multiplier, built in it. After logic synthesis, it will be difficult for technology mapping to find sub-circuits that can be implemented in hard blocks. In this paper, a systematic technology mapping approach is proposed. In the design phase, with the support of CAD tools, a module based design approach is used to map some design block to large hard blocks. During register transfer level synthesis, some functions that are suitable to be implemented in small hard blocks are identified. Other logic functions are mapped into lookup tables with different input size.

APA, Harvard, Vancouver, ISO, and other styles

36

BEKIARIS, DIMITRIS, SOTIRIOS XYDIS, and GEORGE ECONOMAKOS. "SYSTEMATIC DESIGN AND EVALUATION OF RECONFIGURABLE ARITHMETIC COMPONENTS IN THE DEEP SUBMICRON DOMAIN." Journal of Circuits, Systems and Computers 23, no. 10 (October 14, 2014): 1450140. http://dx.doi.org/10.1142/s0218126614501400.

Full text

Abstract:

In the era of deep submicron integration, digital design complexity is increasing with rates that are hard to follow. On one hand, market demand for newer, faster and reliable applications never stops. On the other hand, fabrication technology can not cover this demand with frequency increase and dimension shrinking only, as it has been done in the past. Reconfigurable computing is a new design paradigm that takes advantage of idle components or shared functionality between different algorithms, to maximize utilization and improve performance, based on efficient circuit switching interconnections. However, dense and fast switching interconnections bring power dissipation problems, which are more clear in the deep submicron domain. This paper, presents a systematic design methodology, handling performance, area and both dynamic and static power reduction optimizations in the ASIC domain, for a class of reconfigurable arithmetic components, which can be used as IPs in register-transfer level (RTL) and above RTL synthesis methodologies (electronic system level — ESL, high-level synthesis — HLS, IP-based). Both operand bitwidth and technology scaling are explored, showing that the overall proposed architecture offers clear advantages as device dimensions shrink.

APA, Harvard, Vancouver, ISO, and other styles

37

Tamir, Azwad, Milad Salem, Jie Lin, Qutaiba Alasad, and Jiann-shiun Yuan. "Multi-Tier 3D IC Physical Design with Analytical Quadratic Partitioning Algorithm Using 2D P&R Tool." Electronics 10, no. 16 (August 11, 2021): 1930. http://dx.doi.org/10.3390/electronics10161930.

Full text

Abstract:

In this study, we developed a complete flow for the design of monolithic 3D ICs. We have taken the register-transfer level netlist of a circuit as the input and synthesized it to construct the gate-level netlist. Next, we partitioned the circuit using custom-made partitioning algorithms and implemented the place and route flow of the entire 3D IC by repurposing 2D electronic design automation tools. We implemented two different partitioning algorithms, namely the min-cut and the analytical quadratic (AQ) algorithms, to assign the cells in different tiers. We applied our flow on three different benchmark circuits and compared the total power dissipation of the 3D designs with their 2D counterparts. We also compared our results with that of similar works and obtained significantly better performance. Our two-tier 3D flow with AQ partitioner obtained 37.69%, 35.06%, and 12.15% power reduction compared to its 2D counterparts on the advanced encryption standard, floating-point unit, and fast Fourier transform benchmark circuits, respectively. Finally, we analyzed the type of circuits that are more applicable for a 3D layout and the impact of increasing the number of tiers of the 3D design on total power dissipation.

APA, Harvard, Vancouver, ISO, and other styles

38

Cagliari, Bruna Casagranda, Paulo Francisco Butzen, and Raphael Martins Brum. "Design Considerations of a Nonvolatile Accumulator Based 8-bit Processor." Journal of Integrated Circuits and Systems 16, no. 1 (April 23, 2021): 1–10. http://dx.doi.org/10.29292/jics.v16i1.247.

Full text

Abstract:

The rise of the Internet of Things (IoT) and the constant growth of portable electronics have leveraged the concern with energy consumption due to the use of batteries in these devices. The nonvolatile memory (NVM) emerged as a solution to mitigate the problem due to its ability to retain data on sleep mode without a power supply. Nonvolatile processors (NVPs), in turn, may further improve energy saving, by making use of nonvolatile flip-flops (NVFFs) that store system state in parallel, allowing the device to be turned off when idle and resume execution instantly after power-on. This work describes the initial steps to implement a nonvolatile version of Neander, a hypothetical processor created for educational purposes. First, we implemented Neander in Register Transfer Level (RTL), separating the combinational logic from the sequential elements. Then, the latter were replaced by transistor-level descriptions ofvolatile flip-flops. We then validated this implementation by employing a mixed-signal simulation over a set of benchmarks. Results shown the expected behavior for the whole instruction set. Then, we implemented MTJ-based non-volatile flip-flops in circuit-level, using an open-source MTJ model. These elements were exhaustive validated using electrical simulations. With these results, we intend to carry on the implementation and fully equip our processor with nonvolatile features such as instant wake up.

APA, Harvard, Vancouver, ISO, and other styles

39

Curreri, John, Greg Stitt, and Alan D. George. "High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis." International Journal of Reconfigurable Computing 2011 (2011): 1–17. http://dx.doi.org/10.1155/2011/406857.

Full text

Abstract:

Despite significant performance and power advantages compared to microprocessors, widespread usage of FPGAs has been limited by increased design complexity. High-level synthesis (HLS) tools have reduced design complexity but provide limited support for verification, debugging, and timing analysis. Such tools generally rely on inaccurate software simulation or lengthy register-transfer-level simulations, which are unattractive to software developers. In this paper, we introduce HLS techniques that allow application designers to efficiently synthesize commonly used ANSI-C assertions into FPGA circuits, enabling verification and debugging of circuits generated from HLS tools, while executing in the actual FPGA environment. To verify that HLS-generated circuits meet execution timing constraints, we extend the in-circuit assertion support for testing of elapsed time for arbitrary regions of code. Furthermore, we generalize timing assertions to transparently provide hang detection that back annotates hang occurrences to source code. The presented techniques enable software developers to rapidly verify, debug, and analyze timing for FPGA applications, while reducing frequency by less than 3% and increasing FPGA resource utilization by 0.7% or less for several application case studies on the Altera Stratix-II EP2S180 and Stratix-III EP3SE260 using Impulse-C. The presented techniques reduced area overhead by as much as 3x and improved assertion performance by as much as 100% compared to unoptimized in-circuit assertions.

APA, Harvard, Vancouver, ISO, and other styles

40

Ameur, Noura Ben. "A Low-Phase Noise ADPLL Based on a PRBS-Dithered DDS Enhancement Circuit." Journal of Circuits, Systems and Computers 26, no. 05 (February 8, 2017): 1750076. http://dx.doi.org/10.1142/s0218126617500761.

Full text

Abstract:

This paper aims to design an all-digital phase-locked loop (ADPLL) intended for professional digital audio data conversion applications. The method used for designing is based on an analogy between analog PLL and ADPLL. Managing a low-jitter effect, a comparative study between discrete voltage-controlled oscillator (DVCO) and direct digital synthesis (DDS) based on a pseudorandom binary sequence (PRBS) generator is performed. The features of the design in this work are high-precision and low harmonic distortion DDS which is combined with ADPLL. For model-based design validation, a rapid register transfer level (RTL) with VHSIC hardware description language (VHDL) is practiced and the dynamic performance result indicates a significant improvement in total harmonic distortion (THD) ([Formula: see text][Formula: see text]dB) and a better resolution of 18.97[Formula: see text]bits for audio applications based on the aid of phase dithering DDS enhancement circuit.

APA, Harvard, Vancouver, ISO, and other styles

41

Narendran, S., and J. Selvakumar. "Digital Simulation of Superconductive Memory System Based on Hardware Description Language Modeling." Advances in Condensed Matter Physics 2018 (May 27, 2018): 1–5. http://dx.doi.org/10.1155/2018/2683723.

Full text

Abstract:

We have modeled a memory system using Josephson Junction to attain low power consumption using low input voltage compared to conventional Complementary Metal Oxide Semiconductor-Static Random Access Memory (CMOS-SRAM). We attained the low power by connecting a shared/common bit line and using a 1-bit memory cell. Through our design we may attain 2.5–3.5 microwatts of power using lower input voltage of 0.6 millivolts. Comparative study has been made to find which memory system will attain low power consumption. Conventional SRAM techniques consume power in the range of milliwatts with the supply input in the range of 0-10 volts. Using HDL language, we made a memory logic design of RAM cells using Josephson Junction in FreeHDL software which is dedicated only for Josephson Junction based design. With use of XILINX, we have calculated the power consumption and equivalent Register Transfer Level (RTL) schematic is drawn.

APA, Harvard, Vancouver, ISO, and other styles

42

Aamali, Kaoutar, Abdelhakim Alali, Mohamed Sadik, and Zineb El Hariti. "A Review of the Different Levels of Abstraction for Systems-on-Chip (SoC)." E3S Web of Conferences 229 (2021): 01025. http://dx.doi.org/10.1051/e3sconf/202122901025.

Full text

Abstract:

Simulating systems on a chip (SoC) even before starting its productivity makes it possible to validate the correct functioning of the systems, also avoiding the manufacture of defective chips. However, low-level design and system complexity makes verification and simulation more complicated and time consuming. The classification of the different levels of abstraction from lowest to highest generally depends on the estimation accuracy of the system performance and the speed of simulation. The RTL (Register Transfer Level) abstraction level allows efficient description at gate level with good precision. Therefore, RTL program are slowly simulated. Simulation speed usually depends on the size of the platform used, which is not the case for transaction level modeling (TLM) to achieve simulation speed based on the exchange of transactions between system modules. This work aims to give a detailed description of the different levels of abstraction with the main advantages, and disadvantages on the performances estimation side such as, energy consumption, precision, and speed. Furthermore, an overview of the most adequate memory architectures and interconnection networks, to aim the most suitable virtual platforms of simulation for SoC.

APA, Harvard, Vancouver, ISO, and other styles

43

Ashenden, Peter J., Henry Detmold, and Wayne S. McKeen. "Execution of VHDL Models Using Parallel Discrete Event Simulation Algorithms." VLSI Design 2, no. 1 (January 1, 1994): 1–16. http://dx.doi.org/10.1155/1994/86178.

Full text

Abstract:

In this paper, we discuss the use of parallel discrete event simulation (PDES) algorithms for execution of hardware models written in VHDL. We survey central event queue, conservative distributed and optimistic distributed PDES algorithms, and discuss aspects of the semantics of VHDL and VHDL-92 that affect the use of these algorithms in a VHDL simulator. Next, we describe an experiment performed as part of the Vsim Project at the University of Adelaide, in which a simulation kernel using the central event queue algorithm was developed. We present measurements taken from this kernel simulating some benchmark models. It appears that this technique, which is relatively simple to implement, is suitable for use on small scale multiprocessors (such as current desktop multiprocessor workstations), simulating behavioral and register transfer level models. However, the degree of useful parallelism achievable on gate level models with this technique appears to be limited.

APA, Harvard, Vancouver, ISO, and other styles

44

Alekhin, V. A. "Designing Electronic Systems Using SystemC and SystemC–AMS." Russian Technological Journal 8, no. 4 (August 6, 2020): 79–95. http://dx.doi.org/10.32362/2500-316x-2020-8-4-79-95.

Full text

Abstract:

Current trends in the design of electronic systems is the use of embedded systems based on systems on a chip (System-on-Chip (SoC)) or (VLSI SoC). The paper discusses the design features of electronic systems on a chip using the SystemC design and verification language. For the joint design and simulation of digital systems hardware and software, seven modeling levels are presented and discussed: executable specification, disabled functional model, temporary functional model, transaction-level model, behavioral hardware model, accurate hardware model, register transfer model. The SystemC design methodology with functional verification is presented, which reduces development time.The architecture of the SystemC language and its main components are shown. The expansion of SystemC–AMS for analog and mixed analog-digital signals and its use cases in the design of electronic systems are considered. Computing models are discussed: temporary data stream (TDF), linear signal stream (LSF) and electric linear networks (ELN). The architecture of the SystemC–AMS language standard is shown and examples of its application are given. It is shown that the design languages SystemC and SystemC–AMS are widely used by leading developers of computer-aided design systems for electronic devices.

APA, Harvard, Vancouver, ISO, and other styles

45

Giorgi, Roberto, Farnam Khalili, and Marco Procaccini. "Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise—Designing a Computer Architecture via HLS)." International Journal of Reconfigurable Computing 2019 (November 3, 2019): 1–18. http://dx.doi.org/10.1155/2019/2624938.

Full text

Abstract:

Translating a system requirement into a low-level representation (e.g., register transfer level or RTL) is the typical goal of the design of FPGA-based systems. However, the Design Space Exploration (DSE) needed to identify the final architecture may be time consuming, even when using high-level synthesis (HLS) tools. In this article, we illustrate our hybrid methodology, which uses a frontend for HLS so that the DSE is performed more rapidly by using a higher level abstraction, but without losing accuracy, thanks to the HP-Labs COTSon simulation infrastructure in combination with our DSE tools (MYDSE tools). In particular, this proposed methodology proved useful to achieve an appropriate design of a whole system in a shorter time than trying to design everything directly in HLS. Our motivating problem was to deploy a novel execution model called data-flow threads (DF-Threads) running on yet-to-be-designed hardware. For that goal, directly using the HLS was too premature in the design cycle. Therefore, a key point of our methodology consists in defining the first prototype in our simulation framework and gradually migrating the design into the Xilinx HLS after validating the key performance metrics of our novel system in the simulator. To explain this workflow, we first use a simple driving example consisting in the modelling of a two-way associative cache. Then, we explain how we generalized this methodology and describe the types of results that we were able to analyze in the AXIOM project, which helped us reduce the development time from months/weeks to days/hours.

APA, Harvard, Vancouver, ISO, and other styles

46

Kammler, David, Ernst Martin Witte, Anupam Chattopadhyay, Bastian Bauwens, Gerd Ascheid, Rainer Leupers, and Heinrich Meyr. "Automatic Generation of Memory Interfaces for ASIPs." International Journal of Embedded and Real-Time Communication Systems 1, no. 3 (July 2010): 1–23. http://dx.doi.org/10.4018/jertcs.2010070101.

Full text

Abstract:

With the growing market for multi-processor system-on-chip (MPSoC) solutions, application-specific instruction-set processors (ASIPs) gain importance as they allow for a wide tradeoff between flexibility and efficiency in such a system. Their development is aided by architecture description languages (ADLs) supporting the automatic generation of architecture-specific tool sets as well as synthesizable register transfer level (RTL) implementations from a single architecture model. However, these generated implementations have to be manually adapted to the interfaces of dedicated memories or memory controllers, slowing down the design-space exploration regarding the memory architecture. To overcome this drawback, the authors extend RTL code generation from ADL models with the automatic generation of memory interfaces. This is accomplished by introducing a new abstract and versatile description format for memory interfaces and their timing protocols. The feasibility of this approach is demonstrated in real-life case studies, including a design space exploration for a banked memory system.

APA, Harvard, Vancouver, ISO, and other styles

47

Kim, Youngbae, Heekyung Kim, Nandakishor Yadav, Shuai Li, and Kyuwon Ken Choi. "Low-Power RTL Code Generation for Advanced CNN Algorithms toward Object Detection in Autonomous Vehicles." Electronics 9, no. 3 (March 14, 2020): 478. http://dx.doi.org/10.3390/electronics9030478.

Full text

Abstract:

In the implementation process of a convolution neural network (CNN)-based object detection system, the primary issues are power dissipation and limited throughput. Even though we utilize ultra-low power dissipation devices, the dynamic power dissipation issue will be difficult to resolve. During the operation of the CNN algorithm, there are several factors such as the heating problem generated from the massive computational complexity, the bottleneck generated in data transformation and by the limited bandwidth, and the power dissipation generated from redundant data access. This article proposes the low-power techniques, applies them to the CNN accelerator on the FPGA and ASIC design flow, and evaluates them on the Xilinx ZCU-102 FPGA SoC hardware platform and 45 nm technology for ASIC, respectively. Our proposed low-power techniques are applied at the register-transfer-level (RT-level), targeting FPGA and ASIC. In this article, we achieve up to a 53.21% power reduction in the ASIC implementation and saved 32.72% of the dynamic power dissipation in the FPGA implementation. This shows that our RTL low-power schemes have a powerful possibility of dynamic power reduction when applied to the FPGA design flow and ASIC design flow for the implementation of the CNN-based object detection system.

APA, Harvard, Vancouver, ISO, and other styles

48

Chiolino, N., A. M. Francis, J. Holmes, and M. Barlow. "Digital Logic Synthesis for 470 Celsius Silicon Carbide Electronics." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2018, HiTEC (May 1, 2018): 000064–70. http://dx.doi.org/10.4071/2380-4491-2018-hiten-000064.

Full text

Abstract:

Abstract Advancements in Silicon Carbide (SiC) digital integrated circuit (IC) design have enabled the ability to design complex, dense, digital blocks. Because of the large number of transistors, these complex digital designs make the time and risk of hand-crafted digital design, which has been the norm for SiC, too costly and risky. For large scale integrated digital circuits, computer aided design (CAD) tools are necessary, specifically the use of automatic synthesis, rule-based placement and signal routing software. The tools are used in progression as a design flow and are necessary for the timely and accurate creation of high-density digital designs. Application of an automated digital design flow to high-temperature SiC processes presents new challenges, such as extraction of timing characteristics at high temperatures, specifically above 400°C, as well as managing the complexity of synthesis, optimization of cell placement, verification of timing enclosure, and identifying routing constraints. These activities all require a willingness to extend and enhance the CAD software. Presented is a high temperature SiC digital synthesis flow. This flow is fully integrated with the characterization of a standard cell library that considers the variation of voltage, temperature, and process characteristics. A digital controller for a 10,000-pixel UV focal plan array (FPA) in a SiC CMOS process was designed using this high temperature digital flow. The controller is comprised of a finite state machine (FSM), that monitors several counters, shift registers and combinational logic feedback signals. The FSM is configured to optimize the FPA for different applications and exposures. The Register-Transfer Level (RTL) design of the FSM produces between 900 and 1,000 gates, depending on the temperature-dependent time closure with a total footprint of 14mm2. Typical SiC processes present a non-monotonic clock speed over temperature. The advantage of this digital design flow is that it allows the designer to target a temperature corner for the netlist design but verify its operation over a > 400°C operating range. This flow is currently being enhanced for use with NASA's SiC JFET-R process to create a high temperature communication protocol interface.

APA, Harvard, Vancouver, ISO, and other styles

49

Laurent, J., C. Deleuze, F. Pebay-Peyroula, and V. Beroulle. "Bridging the Gap between RTL and Software Fault Injection." ACM Journal on Emerging Technologies in Computing Systems 17, no. 3 (May 11, 2021): 1–24. http://dx.doi.org/10.1145/3446214.

Full text

Abstract:

Protecting programs against hardware fault injection requires accurate software fault models. However, typical models, such as the instruction skip, do not take into account the microarchitecture specificities of a processor. We propose in this article an approach to study the relation between faults at the Register Transfer Level (RTL) and faults at the software level. The goal is twofold: accurately model RTL faults at the software level and materialize software fault models to actual RTL injections. These goals lead to a better understanding of a system's security against hardware fault injection, which is important to design effective and cost-efficient countermeasures. Our approach is based on the comparison between results from RTL simulations and software injections (using a program mutation tool). Various analyses are included in this article to give insight on the relevance of software fault models, such as the computation of a coverage and fidelity metric, and to link software fault models to hardware RTL descriptions. These analyses are applied on various single-bit and multiple-bit injection campaigns to study the faulty behaviors of a RISC-V processor.

APA, Harvard, Vancouver, ISO, and other styles

50

Gao, Zhenyi, Bin Zhou, Chao Li, Bo Hou, Haobo Sun, Qi Wei, and Rong Zhang. "Design and Implementation of a System-on-Chip for Self-Calibration of an Angular Position Sensor." Applied Sciences 9, no. 22 (November 8, 2019): 4772. http://dx.doi.org/10.3390/app9224772.

Full text

Abstract:

In this study, a novel signal processing algorithm and hardware processing circuit for the self-calibration of angular position sensors is proposed. To calibrate error components commonly found in angular position sensors, a parameter identification algorithm based on the least mean square error demodulation is developed. A processor to run programs and a coprocessor based on the above algorithm are used and designed to form a System-on-Chip, which can calibrate signals as well as implement parameter configuration and control algorithm applications. In order to verify the theoretical validity of the design, analysis and simulation verification of the scheme are carried out, and the maximum absolute error value in the algorithm simulation is reduced to 0.003 %. The circuit’s Register-Transfer Level simulation shows that the maximum absolute value of the angular error is reduced to 0.03%. Simulation results verify the calibration performance with and without quantization and rounding error, respectively. The entire system is prototyped on a Field Programmable Gate Array and tested on a Capacitive Angular Position Sensor. The proposed scheme can reduce the absolute value of angular error to 4.36%, compared to 7.68% from the experimental results of a different calibration scheme.

APA, Harvard, Vancouver, ISO, and other styles

Journal articles on the topic 'Register Transfer Level Design'

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles