Academic literature on the topic 'Resistive Defects'

Diese Arbeit beschäftigt sich mit den elektrischen Eigenschaften der resistiven Schaltmaterialien SrTiO3 und NbO2. Im ersten Teil werden NbO2 (001)-Dünnschichten untersucht. Bisher sind die für NbO2-Dünnschichten in der isolierenden Phase gemessenen spezifische Widerstände um einen Faktor von 200 niedriger als der in NbO2-Einkristallen gemessene 10 kΩ cm Widerstand. In dieser Arbeit wird der spezifische Widerstand von NbO2-Dünnschichten auf 945 Ω cm erhöht. Es wird gezeigt, dass leitfähige Perkolationspfade entlang der Korngrenzen für die Abnahme des spezifischen Widerstandes verantwortlich sind. Durch temperaturabhängige Leitfähigkeitsmessungen wurden Defektzustände identifiziert, die für die Verringerung des spezifischen Widerstandes gegenüber dem theoretischen Wert verantwortlich sind. Im zweiten Teil wird der Einfluss des Ti-Antisite Defekts auf das resistive Schalten in SrTiO3 Dünnschichten untersucht, welche mit metallorganischer Dampfphasenepitaxie gezüchtet wurden. Dabei werden sowohl stoichiometrische als auch Strontium defizitäre Schichten untersucht. Es wird über temperaturabhängige Permittivitätsmessungen gezeigt, dass durch Kristalldefekte die weiche Phononenmode gestört wird und bei stark strontiumverarmten Schichten polare Nanoregionen gebildet werden, was auf die Bildung des TiSr Defekts zurückgeführt wurde. Darüber hinaus wird gezeigt, dass stark strontiumdefiziente SrTiO3 -Schichten ein stabiles resistives Schalten mit einem Ein-Aus-Verhältnis von 2e7 bei 10 K aufweisen, während stöchiometrische Dünnschichten kein stabiles Schalten zeigen. Es wird ein diodenartiger Transportmechanismus, der im hochohmigen Zustand auf Schottkyemission beruht und ihm niederohmigen Zustand durch defektassistierten Tunnelstrom dominiert wird, identifiziert. Daraus wurde ein neues Modell für das resistive Schalten, basierend auf dem TiSr Defekt und der induzierten Ferroelektrizität, entwickelt.<br>In this work, the impact of crystal defects on the resistive switching materials SrTiO3 and NbO2 is investigated. The work is divided into two parts. In the first part, NbO2 (001) thin films are studied. So far, resistivities measured for NbO2 thin films in the insulating phase are by a factor of 200 lower than the 10 kΩ cm resistivity measured in NbO2 single crystals. To make this material applicable for resistive switching, the resistivity in the insulating phase has to be increased to effectively block the current in the high resistive state. Throughout the investigations presented in this work, the resistivity of NbO2 thin films is increased to 945 Ω cm. It is shown that conductive percolation paths along the grain boundaries are responsible for the decrease in resistivity. Temperature-dependent conductivity measurements identified defect states responsible for the reduction in resistivity from the theoretical value. In the second part of this work, the influence of the Ti anti-site defect on resistive switching in SrTiO3 thin films grown by metal-organic vapor phase epitaxy is studied. Both stoichiometric and strontium deficient thin films are studied. It is shown via temperature-dependent permittivity measurements that crystal defects harden the soft phonon mode and polar nano regions are formed in highly strontium deficient films, which was attributed to the formation of Ti antisite defects. In addition, highly strontium deficient SrTiO3 films are shown to exhibit stable resistive switching with an on-off ratio of 2e7 at 10 K, whereas stoichiometric thin-films do not show stable switching. A diode-like transport mechanism based on Schottky emission in the high-resistance state and dominated by defect-assisted tunneling current in the low-resistance state is identified. From this, a new model for resistive switching based on the Ti antisite defect and the induced ferroelectricity is developed.

La mémoire NAND Flash représente une part importante dans le marché des circuits intégrés et a bénéficié de la traditionnelle miniaturisation de l’industrie des sémiconducteurs lui permettant un niveau d’intégration élevé. Toutefois, cette miniaturisation semble poser des sérieux problèmes au-delà du noeud 22 nm. Dans un souci de dépasser cette limite, des solutions mémoires alternatives sont proposées parmi lesquelles la mémoire résistive (RRAM) se pose comme un sérieux candidat pour le remplacement de NAND Flash. Ainsi, dans cette thèse nous essayons de répondre à des nombreuses questions ouvertes sur les dispositifs RRAM à base d’oxyde d’hafnium (HfO2) en particulier en adressant le manque de compréhension physique détaillée sur leur fonctionnement et leur fiabilité. L’impact de la réduction de taille des RRAM, le rôle des électrodes et le processus de formation et de diffusion des défauts sont étudiés. L’impact de l’alliage/dopage de HfO2 avec d’autres matériaux pour l’optimisation des RRAM est aussi abordé. Enfin, notre étude tente de donner quelques réponses sur la formation du filament conducteur, sa stabilité et sa possible composition<br>Among non-volatile memory technologies, NAND Flash represents a significant portion in the IC market and has benefitted from the traditional scaling of semiconductor industry allowing its high density integration. However, this scaling seems to be problematic beyond the 22 nm node. In an effort to go beyond this scaling limitation, alternative memory solutions are proposed among which Resistive RAM (RRAM) stands out as a serious candidate for NAND Flash replacement. Hence, in this PhD thesis we try to respond to many open questions about RRAM devices based on hafnium oxide (HfO2), in particular, by addressing the lack of detailed physical comprehension about their operation and reliability. The impact of scaling, the role of electrodes, the process of defects formation and diffusion are investigated. The impact of alloying/doping HfO2 with other materials for improved RRAM performance is also studied. Finally, our study attempts to provide some answers on the conductive filament formation, its stability and possible composition

Defects in the functional oxides play an important role in electronic devices like metal oxide semiconductor field effect transistors (MOSFETs) and resistive random-access memories (ReRAMs). The continuous scaling of CMOS has brought the Si MOSFET to its physical technology limit and the replacement of Si channel with Ge channel is required. However, the performance of Ge MOSFETs suffers from Ge/oxide interface quality and reliability problems, which originates from the charge traps and defect states in the oxide or at the Ge/oxide interface. The sub-oxide layers composed of GeII states at the Ge/GeO2 interface seems unavoidable with normal passivation methods like hydrogen treatment, which has poor electrical properties and is related to the reliability problem. On the other hand, ReRAM works by formation and rupture of O vacancy conducting filaments, while how this process happens in atomic scale remains unclear. In this thesis, density functional theory is applied to investigate the defect behaviours in oxides to address existing issues in these electronic devices. In chapter 3, the amorphous atomic structure of doped GeO2 and Ge/GeO2 interface networks are investigated to explain the improved MOSFET reliability observed in experiments. The reliability improvement has been attributed to the passivation of valence alternation pair (VAP) type O deficiency defects by doped rare earth metals. In chapter 4, the oxidation mechanism of GeO2 is investigated by transition state simulation of the intrinsic defect diffusion in the network. It is proposed that GeO2 is oxidized from the Ge substrate through lattice O interstitial diffusion, which is different from SiO2 which is oxidized by O2 molecule diffusion. This new mechanism fully explains the strange isotope tracer experimental results in the literature. In chapter 5, the Fermi level pinning effect is explored for metal semiconductor electrical contacts in Ge MOSFETs. It is found that germanides show much weaker Fermi level pinning than normal metal on top of Ge, which is well explained by the interfacial dangling bond states. These results are important to tune Schottky barrier heights (SBHs) for n-type contacts on Ge for use on Ge high mobility substrates in future CMOS devices. In chapter 6, we investigate the surface and subsurface O vacancy defects in three kinds of stable TiO2 surfaces. The low formation energy under O poor conditions and the +2 charge state being the most stable O vacancy are beneficial to the formation and rupture of conducting filament in ReRAM, which makes TiO2 a good candidate for ReRAM materials. In chapter 7, we investigate hydrogen behaviour in amorphous ZnO. It is found that hydrogen exists as hydrogen pairs trapped at oxygen vacancies and forms Zn-H bonds. This is different from that in c-ZnO, where H acts as shallow donors. The O vacancy/2H complex defect has got defect states in the lower gap region, which is proposed to be the origin of the negative bias light induced stress instability.

Submitted by PPG Engenharia El?trica (engenharia.pg.eletrica@pucrs.br) on 2017-10-03T14:30:54Z No. of bitstreams: 1 dissertacao_Marco_tulio.pdf: 5515221 bytes, checksum: 0531f41d66bffa4a34ad4958a41c2d61 (MD5)<br>Approved for entry into archive by Caroline Xavier (caroline.xavier@pucrs.br) on 2017-10-04T13:10:44Z (GMT) No. of bitstreams: 1 dissertacao_Marco_tulio.pdf: 5515221 bytes, checksum: 0531f41d66bffa4a34ad4958a41c2d61 (MD5)<br>Made available in DSpace on 2017-10-04T13:17:57Z (GMT). No. of bitstreams: 1 dissertacao_Marco_tulio.pdf: 5515221 bytes, checksum: 0531f41d66bffa4a34ad4958a41c2d61 (MD5) Previous issue date: 2016-05-27<br>With advances in technology and miniaturization of CMOS, reliability during the life cycle of Integrated Circuit (IC) becomes a complex concern for critical applications. Miniaturization brings many benefits as high performance, power consumption and increase number of functions inside of IC. However, alongside with these, the benefits for increase of interconnections and density of such SoCs create new challenges for the industry. Moreover, a chip needs to store more and more information, resulting in the fact that SRAM occupy the greatest part of SoCs. Consequently, technology advances need to increase the transistor?s density, turnning them a critical concern for testing and reliability to be analysed after manufacturing, since it creates new types of defects. Defects during manufacture process, as well as Negative Bias Temperature Instability (NBTI), Hot Carrier Injection (HCI) and Electromagnetic Interference (EMI) phenomena represent important challenges that must be addressed at an early stages and over the IC?s life-time. In this context, understanding these phenomena and how they affect technologies below 65nm is essential to ensure reliability required for critical applications. In addition, another source of defects is related to process variations during manufacture. Such defects, like resistive-open and resistive-bridge, appear as the most incident. These defects occur due to small geometric changes in the cell, resulting in static and dynamic failures. Depending on the size of defect they can be considered as weak-defects, which do not result in faulty behaviour at logic level and are not sensitized in conventional manufacturing tests. Note that dynamic faults are considered most responsible for testescapes during manufacturing test. Another important phenomena that affects the reliability of ICs over time is NBTI, causing the aging of SRAMs. In this context, this work proposes to analyze the impact of NBTI in SRAM cells with weak resistive-open and resistive-bridge defects that can escape manufacturing tests due to their dynamic behaviour but, with aging, may become dynamic faults over time.<br>Com o avan?o tecnol?gico e a miniaturiza??o da tecnologia CMOS, garantir a confiabilidade durante a vida ?til de Circuitos Integrados (CI) tem se tornado um ponto extremamente complexo e importante para aplica??es consideradas cr?ticas. Muitos s?o os benef?cios que esses avan?os trouxeram, como aumento do desempenho, frequ?ncia de opera??o, CIs com capacidade para novas e mais complexas funcionalidades entre outros. Entretanto, com o aumento do n?mero de interconex?es e densidade dos System-on-chip (SoC) novos desafios surgiram e necessitam ser solucionados para que estes avan?os possam continuar. Avan?os tecnol?gicos possibilitaram a fabrica??o de componentes com uma maior densidade de transistores em uma pequena ?rea de sil?cio, tornando-se um ponto cr?tico para o teste e an?lise da confiabilidade ap?s sua fabrica??o, uma vez que esse processo de fabrica??o gera novos tipos de defeitos. Neste sentido, defeitos do tipo resistive-open e resistive-bridge aparecem como os mais prov?veis. Esses defeitos ocorrem devido a pequenas mudan?as geom?tricas das c?lulas e podem causar falhas est?ticas, bem como falhas din?micas. Da mesma forma, fen?menos como Negative Bias Temperature Instability (NBTI), Positive Bias Temperature Instability (PBTI), Hot Carrier Injection (HCI) e Electromagnetic Interference (EMI) representam importantes desafios que obrigatoriamente devem ser tratados desde a fase inicial de projeto de CIs, bem como durante toda a sua vida ?til. Assim, compreender esses fen?menos e como os mesmos afetam tecnologias abaixo de 65nm ? considerado fundamental a fim de garantir a confiabilidade exigida para aplica??es consideradas cr?ticas. Neste contexto, esse trabalho visa avaliar o impacto de defeitos resistivos do tipo resistiveopen e resistive-bridge nas c?lulas de mem?ria do tipo 6T, que passaram nos testes de manufatura, mas que, ao longo dos anos manifestaram falha devido a presen?a do fen?meno de NBTI. Esses defeitos foram modelados atrav?s da inser??o de resist?ncias em determinados pontos da c?lula de mem?ria. Foi observado que defeitos do tipo resistive-open e resistive-bridge quando presentes entre os inversores de uma c?lula de mem?ria e n?o detectados durante os testes de manufatura, resultaram em falha nas opera??es de leitura da c?lula ao longo dos anos quando na presen?a de NBTI. Essa falha apresenta-se inicialmente com um comportamento din?mico e, de acordo com o envelhecimento da c?lula, passa a comporta-se como est?tica. Essa situa??o compromete a confiabilidade da c?lula, uma vez que o tempo de vida estimado da c?lula ser? inferior ao projetado.

Made available in DSpace on 2013-08-07T18:53:24Z (GMT). No. of bitstreams: 1 000443096-Texto+Completo-0.pdf: 6133830 bytes, checksum: 908c7fe6bab5b7e729af71ec9803c982 (MD5) Previous issue date: 2012<br>The world we live today is very dependent of the technology advance and the Systemson- Chip (SoC) are one of the most important actors of this advance. As a consequence, the Moore's law has been outperformed due to this strong demand on the SoCs for growth, so that new silicon technologies has emerged along with new fault models that decreased the reliability of these devices. SoCs built using Very Deep Sub-Micron technology have a great number of interconnections, increasing the occurrence of Resistive-Open defects that occur on these interconnections up to the point where Resistive-Open defects have become the most important responsible for defective SoCs escaping the manufacturing tests. According to SIA Roadmap's projection, the area consumed by the SRAM on the SoC will be around 95% of the available area, knowing these memory have a great number of interconnections there is also a great probability of occurring Resistive-Open defects on the SRAM circuits which will compromise the overall SoC reliability. When found on SRAMs cells, these defects are able to cause dynamic and static functional faults according to its size, where static faults are sensitized by performing only one operation at the SRAM cell, while dynamic are sensitized by two or more operations. The most common manufacturing tests used to detect defective SoCs are today unable to detect dynamic faults caused by weak Resistive-Open defects. March test performs access on the memory with the intention of sensitizing the faults and detect them as consequence. Due to the higher number of operations necessary to sensitize dynamics faults, this test is not able to detect them properly. Another test is the Iddq test, which is able to detect the presence of defects by monitoring the overall current consumption of a SoC while it's being excited by a known vector of data on its inputs. The consumed current is compared to thresholds or to another similar device that is being excited on the same way. Iddq test is not able to distinguish the variations on current caused by process variations or defects presence. There is an other type of test using On-Chip Current Sensors (OCCS) with March tests that performs current monitoring on the circuits of the SoC and compare them with a threshold in order to set a ag when the monitored current gets higher or lower than a con gured thresholds. Because the mentioned test uses threshold, it is not able to detect Resistive-Open defects that could happen in any node, with any size, in the SRAM cell performing any operation. In this scenario the current consumption could be higher or lower than the defectless current consumption of a cell, making impossible to detect defects using thresholds. By all that, the objective of this dissertation is to propose a defect detection technique able to overcome the three mentioned limitations of preview explained tests. For that, OCCS are along with March test, but a Neighborhood Comparator Logic (NCL) has been included with the objective to perform the detections itself, removing from the OCCS the mission of nding defects. Now the OCCS is only responsible in converting the monitored current consumption signal to a one bit PWM digital signal. In this form, no threshold will be required because the NCL will obtain the reference of the correct current consumption (behavior reference) within the SRAM circuits, by comparing the neighboring cells and adopting the most common behavior as the reference one, so that it will detect those cells that behave di erently from the reference as defective ones. The neighborhood's cells are excited in a parallel form by the test processor, which performs a March test algorithm. The NCL, the OCCS and the March test, together, compose the proposed Resistive-Open detection technique, which has been validated on this work. As result, the proposed technique has shown being able to detect all of the 10 million defective cells of a 1Gbit SRAM containing the hardest defect to detect (small ones). No defective cell has escaped the simulated test and there was only 294,890 good cells being wasted, which represents 0. 029% of the simulated SRAM cells. All of that, by costing only the equivalent to the area of 56 SRAM cells per monitored column and a manufacturing test that performs 5 operations per line of the SRAM.<br>O mundo de hoje é cada vez mais dependente dos avanços tecnológicos sendo os sistemas em chip (SoC, do inglês System-on-Chip) um dos principais alicerces desse avanço. Para tanto que a lei de Moore, que previu que a capacidade computacional dos SoCs dobraria a cada ano, já foi ultrapassada. Devido a essa forte demanda por crescimento novas tecnologias surgiram e junto novos modelos de falhas passaram a afetar a con abilidade dos SoCs. Os SoCs produzidos nas tecnologias mais avançadas (VDSM - Very Deep Sub-Micron), devido a sua alta integração de transistores em uma área pequena, passaram a apresentar um grande número de interconexões fazendo com que os defeitos do tipo Resistive-Open, que ocorrem nessas interconexões, se tornassem os maiores responsáveis por SoCs com defeitos escaparem os testes de manufaturas. Ainda, segundo projeções da SIA Roadmap, a área consumida pela SRAM será em torno de 95% da área utilizada por um SoC. E sabendo que essas memórias possuem inúmeras interconexões, existe uma grande probabilidade de ocorrer defeitos do tipo Resistive-Open em seus circuitos. Esses defeitos são capazes de causar falhas funcionais do tipo estáticas ou dinâmicas, de acordo com a sua intensidade. As falhas estáticas são sensibilizadas com apenas uma operação e as dinâmicas necessitam de duas ou mais operações para que sejam sensibilizadas. Os testes de manufatura mais utilizados para aferir a saúde dos SoCs durante o processo de manufatura são hoje ine cientes frente aos defeitos do tipo Resistive-Open. O mais comum deles é o March Test, que efetua operações de escrita e leitura na memória com o objetivo de sensibilizar falhas e por m detectá-las, entretanto é ine ciente para detectar as falhas do tipo dinâmicas porque é necessário efetuar mais operações que o tempo disponível permite para que essas falhas sejam sensibilizadas. Outro teste utilizado durante a manufatura chama-se teste de corrente quiescente (teste de Iddq), este monitora a corrente consumida do SoC como um todo durante a injeção de vetores nos sinais de entrada, o consumo de corrente do chip é comparado com limiares ou outro chip idêntico sob o mesmo teste para detectar defeitos, entretanto não é possível distinguir entre variações inseridas, nos sinais monitorados, pelos defeitos ou pelos corners, que são variações nas características dos transistores fruto do processo de manufatura. E, por m, o último teste que é apresentado é uma mistura dos dois testes anteriores, utiliza sensores de correntes e algoritmos de operações como em March Test onde que o defeito é detectado pelos sensores de corrente embutidos quando a corrente monitorada ultrapassa dado limiar, embora esse teste tenha condições de detectar defeitos que causam falhas dinâmicas e de não sofrerem in uência dos corners, ele é ine caz ao detectar defeitos do tipo Resistive-Open que possam ocorrer em qualquer local, com qualquer tamanho de impedância em uma SRAM executando qualquer operação, porque os defeitos do tipo Resistive-Open ora aumentam o consumo de corrente e ora o diminui de acordo com essas três características citadas. Comparações por limiares não têm condições de contornar esta di culdade .Com tudo isso, o objetivo desta dissertação de mestrado é propor uma técnica de detec ção de defeitos que seja capaz de vencer as três limitações dos testes convencionais de manufatura apontadas. Para a tarefa, sensores de corrente são utilizados associadamente com March Test, entretanto com o acréscimo de uma Lógica Comparadora de Vizinhança (LCV) que tomará para si a função de detectar defeitos, deixando os sensores apenas encarregados em transformar a corrente analógica em um sinal digital e que tem a capacidade de eliminar a necessidade do uso de limiares, junto com as demais limitações apontadas. A LCV monitora o comportamento de uma vizinhança células e, comparando-os entre si, acusa aquela ou aquelas células que se comportarem diferentemente das suas vizinhas como defeituosas, desta maneira a referência de comportamento correto é obtida da pró- pria vizinhança durante a execução do teste de manufatura, eliminando a necessidade de conhecimento prévio do tipo de distúrbio causado pelos defeitos do tipo Resistive-Open, trazendo facilidade na hora de projetar o sistema de detecção de defeitos e adicionado o poder de detectar qualquer defeito que gere alterações no sinal de corrente consumida das células da SRAM. Neste contexto, o sensor de corrente tem apenas a função de gerar o sinal digital, que é de 1 bit para cada sinal monitorado (V dd e Gnd) e modulado em largura de pulso (PWM), assim a LCV também tem sua complexidade diminuída, pois é constituída por apenas portas lógicas.A LCV e os sensores de corrente são utilizados durante o teste de manufatura, as comparações que ocorrem na vizinhança são efetuadas paralelamente nas células da mem ória, então o teste de manufatura necessita efetuar operações de acesso para excitar semelhantemente todas as células que participam da mesma vizinhança. O March Test é um teste que efetua operações desta natureza e, portanto, é utilizado para controlar a execução do teste e recolher os dados proveniente da LCV, que contém o resultado da detecção efetuada em cada vizinhança. A LCV, o sensor de corrente e o March Test juntos compõem a técnica de detecção de defeitos proposta nesta dissertação, e foram validados quanto as suas funções para comprovar que operam como projetados. Por m, a técnica proposta se mostrou capaz de detectar as 10 milhões de células defeituosas (com o defeito mais difícil de detectar que causa falha funcional dinâmica) em uma SRAM de 1Gbit, sem deixar passar nenhuma célula defeituosa pelo teste de manufatura, junto a isso, 294. 890 células boas foram desperdiçadas, isto-é, foram dadas como defeituosas enquanto não tinham defeitos, o que representa apenas 0,029% de desperdício. Tudo isso, ao custo de área equivalente a área consumida por 56 células de memória, por coluna monitorada, e ao custo de um teste de manufatura que executa apenas 5 operações em cada linha da SRAM.