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Journal articles on the topic 'REVERSE CARRY PROPAGATE ADDER'

Author: Grafiati

Published: 11 September 2023

Last updated: 31 July 2025

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1

Pashaeifar, Masoud, Mehdi Kamal, Ali Afzali-Kusha, and Massoud Pedram. "Approximate Reverse Carry Propagate Adder for Energy-Efficient DSP Applications." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26, no. 11 (2018): 2530–41. http://dx.doi.org/10.1109/tvlsi.2018.2859939.

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2

Arulkarthick, V. J., and Abinaya Rathinaswamy. "Delay and area efficient approximate multiplier using reverse carry propagate full adder." Microprocessors and Microsystems 74 (April 2020): 103009. http://dx.doi.org/10.1016/j.micpro.2020.103009.

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3

Laxmi, Kumre1 Ajay Somkuwar2 and Ganga Agnihotri3. "POWER EFFICIENT CARRY PROPAGATE ADDER." International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013 4, no. 3 (2019): 01–10. https://doi.org/10.5281/zenodo.3364247.

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Here we describe the design details and performance of proposed Carry Propagate Adder based on GDI technique. GDI technique is power efficient technique for designing digital circuit that consumes less power as compare to most commonly used CMOS technique. GDI also has an advantage of minimum propagation delay, minimum area required and less complexity for designing any digital circuit. We designed Carry Propagate Adder using GDI technique and compared its performance with CMOS technique in terms of area, delay and power dissipation. Circuit designed using CADENCE EDA tool and simulated using

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4

Kumre, Laxmi, Ajay Somkuwar, and Ganga Agnihotri. "Power Efficient Carry Propagate Adder." International Journal of VLSI Design & Communication Systems 4, no. 3 (2013): 125–34. http://dx.doi.org/10.5121/vlsic.2013.4312.

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5

Lin, Yu Shen, and Damu Radhakrishnan. "Delay Efficient 32-Bit Carry-Skip Adder." VLSI Design 2008 (April 2, 2008): 1–8. http://dx.doi.org/10.1155/2008/218565.

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The design of a 32-bit carry-skip adder to achieve minimum delay is presented in this paper. A fast carry look-ahead logic using group generate and group propagate functions is used to speed up the performance of multiple stages of ripple carry adders. The group generate and group propagate functions are generated in parallel with the carry generation for each block. The optimum block sizes are decided by considering the critical path into account. The new architecture delivers the sum and carry outputs in lesser unit delays than existing carry-skip adders. The adder is implemented in 0.25 m C

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Sanduri, Akshitha, P. Navitha Mrs., and D. Mamatha Mrs. "Fast Modular Multiplication using Parallel Prefix Adder." International Journal of Trend in Scientific Research and Development 2, no. 5 (2018): 1770–74. https://doi.org/10.31142/ijtsrd18170.

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Public key cryptography applications involve use of large integer arithmetic operations which are compute intensive in term of power, delay and area. Modular multiplication, which is frequently, used most resource hungry block. Generally, last stage of modular multiplication is implemented by using carry propagate adder whose long carry chain takes more time. In this paper, modulo multiplication architectures using Carry Save and Kogge Stone parallel prefix adder are presented to reduce this problem. Proposed implementations are faster as compared to conventional carry save adder and carry pro

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7

Escribá, J., and J. A. Carrasco. "Self-timed Manchester chain carry propagate adder." Electronics Letters 32, no. 8 (1996): 708. http://dx.doi.org/10.1049/el:19960512.

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8

Keerthan, Chilagani, and Bathini Trinay. "High-Speed Area-Efficient VLSI Architecture of Three Operand Binary Adder." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 09, no. 04 (2025): 1–9. https://doi.org/10.55041/ijsrem44578.

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This paper proposes a novel high-speed three-operand binary adder architecture, namely the Han-Carlson adder, which mitigates the inherent limitations of traditional Carry Save Adders (CSAs). The CSA's drawbacks, including slow carry propagation and increased power consumption, are alleviated by the Han-Carlson adder's innovative prefix computation and carry lookahead architecture.The Han-Carlson adder's design exploits the benefits of prefix computation to generate the carry signals in parallel, thereby reducing the critical path delay. Furthermore, the carry lookahead mechanism enables the a

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9

Sandi, Anuradha. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (2020): 40–50. http://dx.doi.org/10.29121/ijetmr.v6.i6.2019.392.

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In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increas

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10

Dr., Anuradha M. Sandi. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (2019): 40–50. https://doi.org/10.5281/zenodo.3245207.

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In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increas

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11

Saini, Vikas K., Shamim Akhter, and Tanuj Chauhan. "Implementation, Test Pattern Generation, and Comparative Analysis of Different Adder Circuits." VLSI Design 2016 (June 8, 2016): 1–8. http://dx.doi.org/10.1155/2016/1260879.

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Addition usually affects the overall performance of digital systems and an arithmetic function. Adders are most widely used in applications like multipliers, DSP (i.e., FFT, FIR, and IIR). In digital adders, the speed of addition is constrained by the time required to propagate a carry through the adder. Various techniques have been proposed to design fast adders. We have derived architectures for carry-select adder (CSA), Common Boolean Logic (CBL) based adders, ripple carry adder (RCA), and Carry Look-Ahead Adder (CLA) for 8-, 16-, 32-, and 64-bit length. In this work we have done comparativ

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12

Gurusamy, L., Muhammad Kashif, and Norhuzaimin Julai. "Design and Implementation of an Efficient Hybrid Parallel-Prefix Ling Adder Using 0.18micron CMOS Technology in Standard Cell Library." Applied Mechanics and Materials 833 (April 2016): 149–56. http://dx.doi.org/10.4028/www.scientific.net/amm.833.149.

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This This paper addresses a novel technique in implementing hybrid parallel-prefix adder (HPA) incorporating prefix-tree structure with Carry Select Adder (CSEA). Ling’s algorithm is used to optimise the pre-processing blocks (white nodes) and intermediate Generate-Propagate blocks (Black nodes) of the prefix tree to minimise the congestion of wires which contributes to reduction in chip size and to improve performance. The resulting prefix-tree arrangement is then merged into a sequence of modified CSEA. Experimental results show that HPA has speed improvement of 62% and 13% power reduction i

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13

Hossain, Muhammad Saddam, and Farhadur Arifin. "Design and Evaluation of a 32-bit Carry Select Adder using 4-bit Hybrid CLA Adder." AIUB Journal of Science and Engineering (AJSE) 20, no. 2 (2021): 1–7. http://dx.doi.org/10.53799/ajse.v20i2.119.

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Adder circuits play a remarkable role in modern microprocessor. Adders are widely used in critical paths of arithmetic operation such as multiplication and subtraction. A Carry Select Adder (CSA) design methodology using a modified 4-bit Carry Look-Ahead (CLA) Adder has been proposed in this research. The proposed 4-bit CLA used hybrid logic style based logic circuits for Carry Generate (Gi) and Carry Propagate (Pi) functions in order to improve performance and reduce the number of transistor used. The modified 4-bit CLA is used as the basic unit for implementation of 32-bit CSA. The proposed

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14

Anitha, M., J. Princy Joice, and Rexlin Sheeba.I. "A New-High Speed-Low Power-Carry Select Adder Using Modified GDI Technique." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 3 (2015): 173. http://dx.doi.org/10.11591/ijres.v4.i3.pp173-177.

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Adders are of fundamental importance in a wide variety of digital systems. This paper presents a novel bit block structure which computes propagate signals as carry strength. Power consumption is one of the most significant parameters of carry select adder.The proposed method aims on GDI(Gate Diffusion Input) Technique. Modified GDI is a novel technique for low power digital circuits design further to reduce the swing degradation problem. This techniques allows reduction in power consumption, carry propagation delay and transistor count of the carry select adder.This technique can be used to r

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15

Jaiswal, Ritesh Kumar, Raj Kumar, and Ram Awadh Mishra. "Area Efficient Memoryless Reverse Converter for New Four Moduli Set {2n−1,2n−1,2n+1,22n+1−1}." Journal of Circuits, Systems and Computers 27, no. 05 (2018): 1850075. http://dx.doi.org/10.1142/s0218126618500755.

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The efficiency of residue number system depends on the reverse converter due to several modulo operations like addition, subtraction and multiplication. In this paper, a design of new four moduli set [Formula: see text], reverse converter is presented. The moduli set have moduli with length ranging from ([Formula: see text]) to ([Formula: see text])-bits. The reverse conversion for moduli set [Formula: see text] has been optimized in existing state of art. Thus, proposed converter is based on two new moduli set [Formula: see text] and utilizes the mixed radix conversion. This converter is memo

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16

Mohan, Shoba, and Nakkeeran Rangaswamy. "An improved implementation of hierarchy array multiplier using CslA adder and full swing GDI logic." Electronics ETF 21, no. 1 (2017): 38. http://dx.doi.org/10.7251/els1721038m.

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In this paper, an efficient implementation of a 16 bit array hierarchy multiplier using full swing Gate Diffusion Input (GDI) logic is discussed. Hierarchy multiplier is attractive because of its ability to carry the multiplication operation withi one clock cycle. The existing hierarchical multipliers occupy more area and suffer from accumulation delay of base multiplier output bits. These issues can be addressed by incorporating carry select adder based addition and the multiplier implementation using full swing GDI logic. The basic computation blocks involved in the multiplier are AND gate a

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17

Bahadori, Milad, Mehdi Kamal, Ali Afzali-Kusha, Yasmin Afsharnezhad, and Elham Zahraie Salehi. "CL-CPA: A hybrid carry-lookahead/carry-propagate adder for low-power or high-performance operation mode." Integration 57 (March 2017): 62–68. http://dx.doi.org/10.1016/j.vlsi.2016.11.009.

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18

Balasubramanian, Padmanabhan, and Douglas L. Maskell. "Monotonic Asynchronous Two-Bit Full Adder." Electronics 13, no. 9 (2024): 1717. http://dx.doi.org/10.3390/electronics13091717.

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Monotonic circuits are a class of input–output mode (IOM) asynchronous circuits that are relaxed compared to quasi-delay-insensitive (QDI) IOM asynchronous circuits in terms of signaling the completion of internal processing. Some recent works have demonstrated the superiority of monotonic logic over QDI logic for arithmetic circuits such as adders and multipliers. This paper presents a new monotonic asynchronous two-bit full adder (TFA) that can be duplicated and cascaded to form a ripple-carry adder (RCA). While an RCA is a slow adder with respect to synchronous design, with respect to IOM a

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19

Vallem, Dr Sharmila, G. Tejaswi, Hrithik Sidharth, and Shilpa Reddy. "High Performance, Low Power Wallace Tree Multiplier." International Journal of Recent Technology and Engineering (IJRTE) 12, no. 2 (2023): 20–25. http://dx.doi.org/10.35940/ijrte.b7685.0712223.

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An area-efficient high Wallace tree multiplier using adders is presented in this paper. The proposed Wallace tree multiplier is designed using logic gates and adders. The design is implemented in Cadence Virtuoso using a 45-nm technology library. The proposed design offers reduced delay and higher performance than conventional multipliers using carry-save adders with majority-based gate adder logic. The design also offers a reduced transistor count of 12, which is minimal compared to that of the conventional design. One of the fundamental building blocks of many VLSI applications is multiplier

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20

Dr., Sharmila Vallem, Tejaswi G., Sidharth Hrithik, and Reddy Shilpa. "High Performance, Low Power Wallace Tree Multiplier." International Journal of Recent Technology and Engineering (IJRTE) 12, no. 2 (2023): 20–25. https://doi.org/10.35940/ijrte.B7685.0712223.

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<strong>Abstract: </strong>An area-efficient high Wallace tree multiplier using adders is presented in this paper. The proposed Wallace tree multiplier is designed using logic gates and adders. The design is implemented in Cadence Virtuoso using a 45-nm technology library. The proposed design offers reduced delay and higher performance than conventional multipliers using carry-save adders with majority-based gate adder logic. The design also offers a reduced transistor count of 12, which is minimal compared to that of the conventional design. One of the fundamental building blocks of many VLSI

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21

Hasan, Mehedi, Moumita Sadia Islam, and Muhtasim Rafid Ahmed. "Performance Improvement of 4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits for Carry Propagate and Generate Terms." Science Journal of Circuits, Systems and Signal Processing 8, no. 2 (2019): 76. http://dx.doi.org/10.11648/j.cssp.20190802.16.

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22

Robertsson, Johan O. A., Fredrik Andersson, and René-Édouard Plessix. "Efficient snapshot-free reverse time migration and computation of multiparameter gradients in full-waveform inversion." GEOPHYSICS 86, no. 5 (2021): T305—T320. http://dx.doi.org/10.1190/geo2020-0606.1.

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Computing images in reverse time migration and model parameter gradients from adjoint wavefields in full-waveform inversion (FWI) requires the correlation of a forward-propagated wavefield with another reverse-propagated wavefield. Although in theory only two wavefield propagations are required, one forward propagation and one reverse propagation, it requires storing the forward-propagated wavefield as a function of time to carry out the correlations, which is associated with significant input/output (I/O) cost. Alternatively, three wavefield propagations can be carried out to reverse propagat

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23

Bentipalli Sekhar, G Appala Naidu, and K. Babulu. "Optimised Implementation of Adaptive Rns Using Power-Aware CRT." International Journal of Maritime Engineering 1, no. 1 (2024): 499–508. http://dx.doi.org/10.5750/ijme.v1i1.1380.

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In order to get an efficient comprehensive analysis on Doppler estimation in RADAR; need an enhanced arithmetic formulation procedure for density, power and latency optimisations. Modular adders and multipliers are very crucial components in the performance of residue number system-based applications. The Residue Number System (RNS) is a non-positional number system that allows parallel computations without transfers between digits. However, some operations in RNS require knowledge of the positional characteristic of a number. Among these operations is the conversion from RNS to the positional

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24

Uoosefian, Hamidreza, Keivan Navi, Reza Faghih Mirzaee, and Mahdi Hosseinzadeh. "High-Performance CML approximate full adders for image processing application of laplace transform." Circuit World 46, no. 4 (2020): 285–99. http://dx.doi.org/10.1108/cw-12-2018-0106.

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Purpose The high demand for fast, energy-efficient, compact computational blocks in digital electronics has led the researchers to use approximate computing in applications where inaccuracy of outputs is tolerable. The purpose of this paper is to present two ultra-high-speed current-mode approximate full adders (FA) by using carbon nanotube field-effect transistors. Design/methodology/approach Instead of using threshold detectors, which are common elements in current-mode logic, diodes are used to stabilize voltage. Zener diodes and ultra-low-power diodes are used within the first and second p

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25

Bernardo-Bermejo, Samuel, Elena Sánchez-López, María Castro-Puyana, Ana B. Fernández-Martínez, Francisco Javier Lucio-Cazaña, and María Luisa Marina. "Exploring the Metabolic Differences between Cisplatin- and UV Light-Induced Apoptotic Bodies in HK-2 Cells by an Untargeted Metabolomics Approach." International Journal of Molecular Sciences 24, no. 8 (2023): 7237. http://dx.doi.org/10.3390/ijms24087237.

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Among the extracellular vesicles, apoptotic bodies (ABs) are only formed during the apoptosis and perform a relevant role in the pathogenesis of different diseases. Recently, it has been demonstrated that ABs from human renal proximal tubular HK-2 cells, either induced by cisplatin or by UV light, can lead to further apoptotic death in naïve HK-2 cells. Thus, the aim of this work was to carry out a non-targeted metabolomic approach to study if the apoptotic stimulus (cisplatin or UV light) affects in a different way the metabolites involved in the propagation of apoptosis. Both ABs and their e

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"Approximate Reverse Carry Propagate Adder for Energy-Efficiency." International Journal of Innovative Technology and Exploring Engineering 9, no. 2 (2019): 3252–56. http://dx.doi.org/10.35940/ijitee.a4933.129219.

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The hypothesis of estimated measure is to design computation quality for computation efforts. The Approximate full adders (AFA’s) are the lead objective to reduce the length of carry propagation which is put through to the slightest error rate. Approximate adder comes up with important enhancement in delay, area and power. The developing attribute is carry doesn't propagate in it. So in this we mainly use the hybrid adders where it utilizes the RCPFA. The approximate adder generates the input carry from higher bit to lower bit to produce carry output, , the weight of the carry reduces when it

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"High Throughput Efficient Modified SQRT Carry Select Adder." International Journal of Recent Technology and Engineering 8, no. 5 (2020): 5261–63. http://dx.doi.org/10.35940/ijrte.e3205.018520.

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In numerous processors math unit is fundamental structure square like DSPs and chip. Adders are key structure obstructs in ALUs. In this manner expanding adders speed, lessening their vitality utilization and zone firmly impact the speed, control utilization and region of processor. There are numerous takes a shot at the subject of advancing velocity, zone of these units. One of way to deal with improve both the territory and speed is to forfeit the calculation precision. This methodology is rough registering, might be utilized for the applications where a few blunders might be endured. In Rev

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28

Beerendra, Patel, and Jitendra Kanungo. "Design of an Efficient Reverse Converter for Moduli Sets." Journal of Engineering Research, April 6, 2022. http://dx.doi.org/10.36909/jer.icmet.17193.

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The appropriate selection of moduli has a significant impact on the reverse converter's speed and complexity. The modified converter depends upon the arithmetic designs that are implemented without the read - only memories and lookup tables. The Carry Save Adder and Carry Propagate Adder are used in the reverse converter and modulo adder gives higher speed and less hardware complexity. The proposed converter has been implemented to get the conversion time and area as supported by the reverse converter of 12-bits and maximum up to 100-bits.

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29

S, Nagakumararaj. "Implementation of a Reverse Carry Propagate Adder Based On Efficient VLSI for Hardware Security and Area Consumption." International Journal of Advanced Trends in Engineering and Management III, no. 05 (2024). http://dx.doi.org/10.59544/ppym6586/ijatemv03i05p5.

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The various techniques inbuilt in the VLSI (Very Large Scale Integration) designing is originated from the basis of adder circuits. When these adder circuits are processed in the higher digital signal processing systems, the adders have to exhibit high performance, good efficiency with reduced cost and area of implementation. The major objective of designing the VLSI design is minimizing the complexity and to perform the operations more effectively. Whereas in some other methods, the logic circuit designing is made larger in order to achieve higher efficiency. This in turn, results in the redu

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30

Edem, K. Bankas, and A. Gbolagade Kazeem. "A New Efficient RNS Reverse Converter for the 4-Moduli Set ." February 6, 2014. https://doi.org/10.5281/zenodo.1091392.

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In this paper, we propose a new efficient reverse converter for the 4-moduli set {2<em><sup>n</sup></em><em>, </em>2<em><sup>n</sup></em> + 1<em>, </em>2<em><sup>n</sup></em> <em>− </em>1<em>, </em>2<sup>2</sup><em><sup>n</sup></em><sup>+1</sup> <em>– </em>1} based on a modified Chinese Remainder Theorem and Mixed Radix Conversion. Additionally, the resulting architecture is further reduced to obtain a reverse converter that utilizes only carry save adders, a multiplexer and carry propagate adders. The proposed converter has an area cost of (12n + 2) FAs and (5n + 1) HAs with a del

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31

Edem, K. Bankas and Kazeem A. Gbolagade. "A New Efficient RNS Reverse Converter For The 4-Moduli Set {2^{n}, 2^{n}+1, 2^{n}-1, 2^{2n+1}-1}." International Journal of Electronics and Communication Engineering 7.0, no. 11 (2013). https://doi.org/10.5281/zenodo.2660001.

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In this paper, we propose a new efficient reverse converter for the 4-moduli set {2^{n}, 2^{n}+1, 2^{n}-1, 2^{2n+1}} based on a modified Chinese Remainder Theorem and Mixed Radix Conversion. Additionally, the resulting architecture is further reduced to obtain a reverse converter that utilizes only carry save adders, a multiplexer and carry propagate adders. The proposed converter has an area cost of (12n+2) FAs and (5n+1) HAs with a delay of (9n+6)t_{FA}+t_{MUX}. When compared with state of the art, our proposal demonstrates to be faster, at the expense of slightly more hardware resources. Fu

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32

Ebrahimi-Azandaryani, Farhad, Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, and Massoud Pedram. "Accuracy Configurable Adders with Negligible Delay Overhead in Exact Operating Mode." ACM Transactions on Design Automation of Electronic Systems, October 26, 2022. http://dx.doi.org/10.1145/3549936.

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In this paper, two accuracy configurable adders capable of operating in approximate and exact modes are proposed. In the adders, which include a block-based carry propagate and a parallel prefix structure, the carry chains are cut off in the approximate mode limiting the carry chain depth to two blocks. In the case of parallel prefix adder, we propose a special carry generate tree equipped with a power gating means. In both of the proposed structures, the critical paths of the adders are not increased in the exact operating mode. Thus, the main objective of proposing these approximate adder st

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C., Thangam, Neelu Kumari K. S., and Nagakumararaj S. "Implementation of Ripple Carry Adder Design for Optimal VLSI Performance." International Journal of Advanced Trends in Engineering and Management II, no. 11 (2023). http://dx.doi.org/10.59544/pbmc1528/ijatemv02i11p3.

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In the province of wireless receivers, biomedical equipment, and portable/mobile devices, the demand for Very Large Scale Integration (VLSI) systems that optimize space, minimize power consumption, and deliver high performance is dominant. At the core of these systems, adders play a pivotal role as the primary component of arithmetic units. This paper proposes a ripple carry propagate adder with a high-speed area-efficient. The two’s complement representation is employed for adding two numbers, a common practice in various systems dealing with n-bit input sequences. Microprocessors and digital

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34

S, Lokesh. "A REVIEW OF LOW VOLTAGE AND LOW POWER CMOS ADDERS USING VLSI DESIGN IN VERILOG/VHDL." International Journal of Engineering Applied Sciences and Technology 6, no. 3 (2021). http://dx.doi.org/10.33564/ijeast.2021.v06i03.044.

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The dominant portion of power dissipation in CMOS adder circuits, due to logic transitions, varies as the square of the supply, significant savings in power dissipation may be exacted by operating with reduced supply voltage. If the supply voltage is reduced while threshold voltage stays same, the noise margins will reduce. Addition is a crucial process because it usually involve carry ripple steps which must propagate a carry signal from each bit to it’s higher bit position. This results in a substantial circuit delay. The adder which lies in the crucial delay path will effectively determine

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35

Turaka, Rajasekhar, Koteswara Rao Bonagiri, Talla Srinivasa Rao, et al. "Design of approximate reverse carry select adder using RCPA." International Journal of Electronics Letters, April 29, 2022, 1–11. http://dx.doi.org/10.1080/21681724.2022.2062791.

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36

Wang, Siyi, Ankit Mondal, and Anupam Chattopadhyay. "Optimal Toffoli-Depth Quantum Adder." ACM Transactions on Quantum Computing, June 10, 2025. https://doi.org/10.1145/3743691.

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Efficient quantum arithmetic circuits are commonly found in numerous quantum algorithms of practical significance. To date, the logarithmic-depth quantum adders includes a constant coefficient k ≥ 2 while achieving the Toffoli-Depth of \(k\log {}n + \mathcal {O}(1) \) . In this work, 160 alternative compositions of the carry-propagation structure are comprehensively explored to determine the optimal depth structure for a quantum adder. By extensively studying these structures, it is shown that an exact Toffoli-Depth of \(\log {}n + \mathcal {O}(1) \) is achievable. This presents a reduction of

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37

"A Hierarchical Design of 128 Bit Carry Lookahead Adder in 65 nm CMOS Technology." International Journal of Innovative Technology and Exploring Engineering 9, no. 3 (2020): 2643–48. http://dx.doi.org/10.35940/ijitee.c8757.019320.

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As One Giga Hertz microprocessors power mobiles, laptops, tablets and personal computers in last few years, there is a massive need to reduce the number cycles to do addition which plays a significant role in Arithmetic Logic Unit (ALU) or Digital Signal Processing (DSP). The complexity of carry propagation is the critical variable once the designs requires addition over 32 bits. A hierarchical design has been developed to find Carry out at 16-bit stage from Propagate and Generate techniques from a 4-bit stage of Carry Lookahead Adder (CLA), so called Carry Lookahead Logic (CLL). Four blocks o

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38

Cini, Ugur, and Gokhan Kocyigit. "Limited Carry-Propagate Multiply-Accumulate Unit Design for Reconfigurable Systems." Elektronika ir Elektrotechnika 23, no. 2 (2017). https://doi.org/10.5755/j01.eie.23.2.17997.

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Counter and compressor arrays are frequently employed in multiplier design to efficiently reduce partial products in VLSI design. On the other hand, in reconfigurable systems, fast carry chains boost the performance of carrypropagate adders. So that, in reconfigurable systems, to save logic element area, counter and compressor trees are not employed as much since they require more area than carrypropagate scheme. In this work, carry-propagate multioperand adders are employed in smaller blocks and the outputs are merged using double carry-save encoding to increase performance in reconfigurable

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"Design and Analysis of 32-bit Reverse Converter based on low power Parallel Prefix Adder." International Journal of Engineering and Advanced Technology 9, no. 1 (2019): 3028–31. http://dx.doi.org/10.35940/ijeat.a1207.109119.

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The Residue Number System (RNS) based reverse converter can play as main role in Parallel arithmetic operations of Digital Signal Processing (DSP) applications and VLSI technologies. Normally, by the use of carry adders, the reverse conversion design gives high delay and high power consumption. Due to resolve of above problem, the design of reverse converter is proposed by the use of familiar high speed (less propagation delay) Parallel Prefix - Kogge Stone Adder (PP- KSA). This paper describes the design of 32-bit Reverse converter with regular PP-KSA and proposed MUX (Multiplex) logic of PP-

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Garg, Bharat. "Energy-Efficient Gaussian Filter Design Using Novel Low-Complexity Accuracy Reconfigurable Reverse Carry Adder." National Academy Science Letters, August 13, 2020. http://dx.doi.org/10.1007/s40009-020-01016-9.

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Kumar, Gundugonti Kishore, Mahammad Firose Shaik, Vikram Kulkarni, and Rambabu Busi. "Power and Delay Efficient Haar Wavelet Transform for Image Processing Application." Journal of Circuits, Systems and Computers, February 23, 2022. http://dx.doi.org/10.1142/s0218126622200018.

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This paper presents a one-level decomposition Haar Discrete Wavelet Transform (DWT) architecture using a 4:2 compressor and carry propagate adder. In Haar DWT architecture, coefficient multiplication is an essential operation. The Haar coefficient multiplication [Formula: see text] is implemented with [Formula: see text] multiplier and the generated partial products are represented with sign power of two (SPT) terms. The addition of SPT terms is computed with a 4:2 compressor and the final sum is computed with CPA. A [Formula: see text] multiplier with 4:2 compressor technique is used to impro

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Hoßfeld, Konstantin J., Hans Jakob Damsgaard, Jari Nurmi, Michaela Blott, and Thomas B. Preußer. "High-Efficiency Compressor Trees for Latest AMD FPGAs." ACM Transactions on Reconfigurable Technology and Systems, February 10, 2024. http://dx.doi.org/10.1145/3645097.

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High-fan-in dot product computations are ubiquitous in highly relevant application domains, such as signal processing and machine learning. Particularly, the diverse set of data formats used in machine learning poses a challenge for flexible efficient design solutions. Ideally, a dot product summation is composed from a carry-free compressor tree followed by a terminal carry-propagate addition. On FPGA, these compressor trees are constructed from generalized parallel counters (GPCs) whose architecture is closely tied to the underlying reconfigurable fabric. This work reviews known counter desi

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Hossfeld, Konstantin J., Hans Jakob Damsgaard, Jari Nurmi, Michaela Blott, and Thomas B. Preusser. "High-Efficiency Compressor Trees for Latest AMD FPGAs." ACM Transactions on Reconfigurable Technology and Systems (TRETS), February 10, 2024. https://doi.org/10.1145/3645097.

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High-fan-in dot product computations are ubiquitous in highly relevant application domains, such as signal processing and machine learning. Particularly, the diverse set of data formats used in machine learning poses a challenge for flexible efficient design solutions. Ideally, a dot product summation is composed from a carry-free compressor tree followed by a terminal carry-propagate addition. On FPGA, these compressor trees are constructed from generalized parallel counters (GPCs) whose architecture is closely tied to the underlying reconfigurable fabric. This work reviews known counter desi

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Holmes, Ashley M. "Cohesion, Adhesion and Incoherence: Magazine Production with a Flickr Special Interest Group." M/C Journal 13, no. 1 (2010). http://dx.doi.org/10.5204/mcj.210.

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This paper provides embedded, reflective practice-based insight arising from my experience collaborating to produce online and print-on-demand editions of a magazine showcasing the photography of members of haphazart! Contemporary Abstracts group (hereafter referred to as haphazart!). The group’s online visual, textual and activity-based practices via the photo sharing social networking site Flickr are portrayed as achieving cohesive visual identity. Stylistic analysis of pictures in support of this claim is not attempted. Rather negotiation, that Elliot has previously described in M/C Journal

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