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Dissertations / Theses on the topic 'Reversible programmable logic array'

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Published: 4 June 2025

Last updated: 1 August 2025

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1

Pearce, Maureen. "Logic synthesis for programmable devices." Thesis, University of Bristol, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.357911.

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2

Bollinger, Patrick James. "Prime Factorization Through Reversible Logic Gates." Youngstown State University / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ysu1558867948427409.

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3

Wendt, Charles G. "Multiple-valued programmable logic array minimization by solution space search." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1993. http://handle.dtic.mil/100.2/ADA278033.

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4

Yuan, Shaohua. "A novel programmable logic array structure with low energy consumption." Thesis, University of British Columbia, 2009. http://hdl.handle.net/2429/7450.

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As modern integrated circuit design pushes further into the deep submicron era, the pseudo-random design structures become more and more difficult to fabricate and result in a yield reduction. To deal with process limitations due to photolithographic resolution, standard cell ASICs (SC-ASIC) may eventually need to be replaced by a more structured form of logic, such as programmable logic array (PLA). However, in order to compete with SC-ASIC, the PLA needs to be improved on delay, power and energy consumption. Here, we will explore a novel PLA structure by combining one design having the bes

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5

Earle, Robert C. "Minimization of multiple-valued programmable logic array using simulated annealing." Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/28360.

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6

Avadhanam, Karthik. "A new high speed low power Dynamic Programmable Logic Array /." Available to subscribers only, 2007. http://proquest.umi.com/pqdweb?did=1453188921&sid=5&Fmt=2&clientId=1509&RQT=309&VName=PQD.

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7

Treuer, Robert. "A new design of built-in self-testing programmable logic arrays with high fault coverage and low overhead /." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63215.

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8

Abbas, Samir I. "FACTPLA : functional analysis and the complexity of testing programmable logic array." Thesis, Brunel University, 1988. http://bura.brunel.ac.uk/handle/2438/7288.

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A computer aided method for analyzing the testability of Programmable Logic Arrays (PLAs) is described. The method, which is based on a functional verification approach, estimates the complexity of testing a PLA according to the amount of single undetectable faults in the array structure. An analytic program (FACTPLA) is developed to predict the above complexity without analyzing the topology of the array as such. Thus, the method is technology invariant and depends only on the functionality of the PLA. The program quantitatively evaluates the effects of undetectable faults and produces some t

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9

Han, Yi. "Development of nonlinear reconfigurable control of reconfigurable plants using the FPGA technology." Thesis, [S.l. : s.n.], 2008. http://dk.cput.ac.za/cgi/viewcontent.cgi?article=1011&context=td_cput.

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10

Biju, S., T. V. Narayana, P. Anguswamy, and U. S. Singh. "A Systolic Array Based Reed-Solomon Decoder Realised Using Programmable Logic Devices." International Foundation for Telemetering, 1995. http://hdl.handle.net/10150/611584.

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International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada<br>This paper describes the development of a Reed-Solomon (RS) Encoder-Decoder which implements the RS segment of the telemetry channel coding scheme recommended by the Consultative Committee on Space Data Systems (CCSDS)[1]. The Euclidean algorithm has been chosen for the decoder implementation, the hardware realization taking a systolic array approach. The fully pipelined decoder runs on a single clock and the operating speed is limited only by the Galois Field (GF) multiplier'

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11

Sedaghat, Maman Reza. "Fault emulation reconfigurable hardware based fault simulation using logic emulation systems with optimized mapping /." [S.l. : s.n.], 1999. http://deposit.ddb.de/cgi-bin/dokserv?idn=95853893X.

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12

Malik, Usama Computer Science &amp Engineering Faculty of Engineering UNSW. "Configuration encoding techniques for fast FPGA reconfiguration." Awarded by:University of New South Wales. School of Computer Science and Engineering, 2006. http://handle.unsw.edu.au/1959.4/26212.

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This thesis examines the problem of reducing reconfiguration time of an island-style FPGA at its configuration memory level. The approach followed is to examine configuration encoding techniques in order to reduce the size of the bitstream that must be loaded onto the device to perform a reconfiguration. A detailed analysis of a set of benchmark circuits on various island-style FPGAs shows that a typical circuit randomly changes a small number of bits in the {\it null} or default configuration state of the device. This feature is exploited by developing efficient encoding schemes for configur

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13

Koh, Shannon Computer Science &amp Engineering Faculty of Engineering UNSW. "Generating the communication infrastracture for module-based dynamic reconfiguration of FPGas." Publisher:University of New South Wales. Computer Science & Engineering, 2008. http://handle.unsw.edu.au/1959.4/41418.

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Current approaches to supporting module-based FPGA reconfiguration focus on various aspects and sub-problems in the area but do not combine to form a coherent, top-down methodology that factors low-level device parameters into every step of the design flow. This thesis proposes such a top-down methodology from application specification to low-level implementation, centered around examining the problem of generating a point-to-point communications infrastructure to support the changing interfaces of dynamically placed modules. Low-level implementation parameters are considered at every stage to

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14

Wood, Christopher Landon. "Runtime partial FPGA reconfiguration." Thesis, Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15051.

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15

Galindo, Juan Manuel. "A novel partial reconfiguration methodology for FPGAs of multichip systems /." Online version of thesis, 2008. http://hdl.handle.net/1850/7784.

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16

Rajagopalan, Kamal. "An FPGA architecture for improved arithmetic performance /." St. Lucia, Qld, 2001. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe16460.pdf.

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17

Sharma, Akshay. "Place and route techniques for FPGA architecture advancement /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6108.

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18

Yildirim, Cem. "Multiple-valued programmable logic array minimization by concurrent multiple and mixed simulated annealing." Thesis, Monterey, California. Naval Postgraduate School, 1992. http://hdl.handle.net/10945/28383.

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19

Van, Heerden Hein. "The design and testing of a superconducting programmable gate array." Thesis, Stellenbosch : University of Stellenbosch, 2006. http://hdl.handle.net/10019.1/1644.

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Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2006.<br>This thesis investigates to the design, analysis and testing of a Superconducting Programmable Gate Array (SPGA). The objective was to apply existing programmable logic concepts to RSFQ circuits and in the process develop a working prototype of a superconducting programmable logic device. Various programmable logic technologies and architectures were examined and compared to find the best solution. Using Rapid Single Flux Quantum (RSFQ) circuits as building blocks, a complete functional design wa

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20

Seater, Robert. "Efficient handling of dependence analysis for arrays." Diss., Connect to the thesis, 2002. http://hdl.handle.net/10066/1541.

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21

Mak, Wai-kei. "Partitioning and routing for multi-FPGA systems /." Digital version accessible at:, 1998. http://wwwlib.umi.com/cr/utexas/main.

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22

Chang, Mark L. "Variable precision analysis for FPGA synthesis /." Thesis, Connect to this title online; UW restricted, 2004. http://hdl.handle.net/1773/5901.

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23

Han, Yi. "A high-performance CMOS programmable logic core for system-on-chip applications /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/5948.

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24

Holland, Mark. "Automatic creation of product-term-based reconfigurable architectures for system-on-a-chip /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6124.

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25

Al-aqeeli, Abulqadir. "Reconfigurable wavelet-based architecture for pattern recognition applications using a field programmable gate array." Ohio University / OhioLINK, 1998. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1177008904.

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26

Raghavan, Anup Kumar. "JPG : a partial bitstream generation tool to support partial reconfiguration in Virtex FPGAs /." [St. Lucia, Qld.], 2004. http://www.library.uq.edu.au/pdfserve.php?image=thesisabs/absthe17691.pdf.

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27

Kapkar, Rohan Viren. "Modeling and Simulation of Altera Logic Array Block using Quantum-Dot Cellular Automata." University of Toledo / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1304616947.

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28

Schlottmann, Craig Richard. "Analog signal processing on a reconfigurable platform." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29623.

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Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.<br>Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Ghovanloo, Maysam. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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29

Wu, Lifei. "Minimization of Permuted Reed-Muller Trees and Reed-Muller Trees for Cellular Logic Programmable Gate Arrays." PDXScholar, 1993. https://pdxscholar.library.pdx.edu/open_access_etds/4745.

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The new family of Field Programmable Gate Arrays, CLI 6000 from Concurrent Logic Inc realizes truly Cellular Logic. It has been mainly designed for the realization of data path architectures. However, the realizable logic functions provided by its macrocells and their limited connectivity call also for new general-purpose logic synthesis methods. The basic cell of CLi 6000 can be programmed to realize a two-input multiplexer ( A*B + C*B ), an AND/EXOR cell ( A*B Ea C ), or the basic 2-input AND, OR and EXOR gate. This suggests to using these cells for tree-like expansions. These "cellular logi

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30

Tan, Chong Guan. "Another approach to PLA folding." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=66054.

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31

Schafer, Ingo. "Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping." PDXScholar, 1992. https://pdxscholar.library.pdx.edu/open_access_etds/1339.

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The growing complexity of integrated circuits and the large variety of architectures of Field Programmable Gate Arrays (FPGAs) require sophisticated logic design tools. In the beginning of the eighties the research in logic design was concentrated on the development of fast two-level AND-OR logic minimizers like the well known ESPRESSO. However, most logic functions have a smaller and often faster circuit realization as a multi-level circuit. Thus, synthesis tools emerged for the minimization of the circuit area in a multi-level realization. Most of these synthesis tools are based on the "unat

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32

Zhuo, Yue. "Timing and Congestion Driven Algorithms for FPGA Placement." Thesis, University of North Texas, 2006. https://digital.library.unt.edu/ark:/67531/metadc5423/.

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Placement is one of the most important steps in physical design for VLSI circuits. For field programmable gate arrays (FPGAs), the placement step determines the location of each logic block. I present novel timing and congestion driven placement algorithms for FPGAs with minimal runtime overhead. By predicting the post-routing timing-critical edges and estimating congestion accurately, this algorithm is able to simultaneously reduce the critical path delay and the minimum number of routing tracks. The core of the algorithm consists of a criticality-history record of connection edges and a cong

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33

Cornelia, Olivian E. "Conditional stuck-at fault model for PLA test generation." Thesis, McGill University, 1987. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63959.

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34

Shen, Ying. "Compiling a synchronous programming language into field programmable gate arrays." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0029/MQ47476.pdf.

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35

Pinkiewicz, T. "Design of a 32-bit Arithmetic Unit based on Composite Arithmetic and its Implementation on a Field Programmable Gate Array." Thesis, Honours thesis, University of Tasmania, 1999. https://eprints.utas.edu.au/584/1/Honours_Thesis.pdf.

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As we advance into the new century, computers of the future will require new techniques for arithmetic operations, which take advantage of the modern technology and yield accurate results. Floating-point arithmetic has been in use for nearly forty years, but is plagued with inaccuracies and limitations which necessitate introduction of a new concept in computer arithmetic, called Composite Arithmetic. Composite Arithmetic combines fixed-point and floating-point arithmetic into one integrated concept where numbers are automatically assigned the right form. This negates the need for diffe

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36

Lee, Hoon S. "A CAD tool for current-mode multiple-valued CMOS circuits." Thesis, Monterey, California. Naval Postgraduate School, 1988. http://hdl.handle.net/10945/22935.

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Approved for public release; distribution is unlimited<br>The contribution of this thesis is the development of a CAD (computer aided design) tool for current mode multiple-valued logic (MVL) CMOS circuits. It is only the second known MVL CAD tool and the first CAD tool for MVL CMOS. The tool accepts a specification of the function to be realized by the user, produces a minimal or near-minimal realization (if such a realization is possible), and produces a layout of a programmable logic array (PLA) integrated circuit that realizes the given function. The layout is in MAGIC format, suitab

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37

Draier, Benny. "Test vector generation and compaction for easily testable PLAs." Thesis, McGill University, 1988. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63970.

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38

Moon, Gyo Sik. "An Algorithm for the PLA Equivalence Problem." Thesis, University of North Texas, 1995. https://digital.library.unt.edu/ark:/67531/metadc278922/.

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The Programmable Logic Array (PLA) has been widely used in the design of VLSI circuits and systems because of its regularity, flexibility, and simplicity. The equivalence problem is typically to verify that the final description of a circuit is functionally equivalent to its initial description. Verifying the functional equivalence of two descriptions is equivalent to proving their logical equivalence. This problem of pure logic is essential to circuit design. The most widely used technique to solve the problem is based on Binary Decision Diagram or BDD, proposed by Bryant in 1986. Unfortunate

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39

Зубков, О. В., І. В. Свид, О. С. Мальцев, and Л. Ф. Сайківська. "In-circuit Signal Analysis in the Development of Digital Devices in Vivado 2018." Thesis, Theoretical and Applied Aspects of Device Development on Microcontrollers and FPGAs, MC&FPGA-2019, 2019. https://doi.org/10.35598/mcfpga.2019.003.

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Considered the implementation of in-circuit analysis of logical signals in digital devices synthesized in Xilinx Field-Programmable Gate Array. Designed a digital control device streaming analog-to-digital converter. An analysis of the results of the analog-digital conversion was carried out and measures were taken to smooth out the false results of the conversion.

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40

Зубков, О. В., І. В. Свид, О. С. Мальцев, and Л. Ф. Сайківська. "In-circuit Signal Analysis in the Development of Digital Devices in Vivado 2018." Thesis, NURE, MC&FPGA, 2019. https://mcfpga.nure.ua/conf/2019-mcfpga/10-35598-mcfpga-2019-003.

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Considered the implementation of in-circuit analysis of logical signals in digital devices synthesized in Xilinx Field-Programmable Gate Array. Designed a digital control device streaming analog-to-digital converter. An analysis of the results of the analog-digital conversion was carried out and measures were taken to smooth out the false results of the conversion.

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41

Foote, David W. "The Design, Realization and Testing of the ILU of the CCM2 Using FPGA Technology." PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4703.

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Most existing computers today are built upon a subset of the arithmetic system which is based upon the foundation of set theory. All formal systems can be expressed in terms of arithmetic and logic on current arithmetic computers through an appropriate model, then work with the model using software manipulation. However, severe speed degradation is the price one must pay for using a software-based approach, making several high-level formal systems impractical. To improve the speed at which computers can implement these high-level systems, one must either design special hardware, implementing s

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42

La, Spina Mark. "Parallel Genetic Algorithm Engine on an FPGA." Scholar Commons, 2010. https://scholarcommons.usf.edu/etd/1691.

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The field of FPGA design is ever-growing due to costs being lower than that of ASICs, as well as the time and cost of development. Creating programs to run on them is equally important as developing the devices themselves. Utilizing the increase in performance over software, as well as the ease of reprogramming the device, has led to complex concepts and algorithms that would otherwise be very time-consuming when implemented on software. One such focus has been towards a search and optimization algorithm called the genetic algorithm. The proposed approach is to take an existing application of

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43

Jíša, Pavel. "Využití jazyka C při implementaci algoritmů pro FPGA." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2012. http://www.nusl.cz/ntk/nusl-219682.

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This diploma thesis is engaged in implementations of algorithms for signal filtering in the field programmable gate array utilising the C and ImpulseC programming language. It is focused on one-dimensional FIR and IIR filters and also two-dimensional such as convolution and Sobel's operator. Moreover, evaluations of these filter algorithms are included.

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44

Hadjoudja, Abdelkader. "Macrogénération et prédiction temporelle sur les réseaux programmables CPLD." Grenoble INPG, 1997. http://www.theses.fr/1997INPG0177.

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Cette these a essentiellement consiste a etudier la synthese et la generation de macros sur les cibles programmables hierarchique de type cpld. Cette etude porte surtout sur les operateurs arithmetiques de base (additionneurs, comparateur,. . . ). Il s'agit de choisir les architectures appropriees, de generer des equations parametrees, de mettre en place une optimisation utilisant au maximum les ressources specifiques des produits recents de ces composants (mach5 de vantis, et atf1500 d'atmel). Une facette importante de ce travail a concerne les predictions et evaluations temporelles incluant

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45

Chiang, Kang-Chung. "Scan path design of PLA to improve its testability in VLSI realization." Ohio : Ohio University, 1986. http://www.ohiolink.edu/etd/view.cgi?ohiou1183128113.

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46

Wijaya, Shierly. "Fixed-point realisation of erbium doped fibre amplifer control algorithms on FPGA." University of Western Australia. School of Electrical, Electronic and Computer Engineering, 2009. http://theses.library.uwa.edu.au/adt-WU2009.0132.

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The realisation of signal processing algorithms in fixed-point offers substantial performance advantages over floating-point realisations. However, it is widely acknowledged that the task of realising algorithms in fixed-point is a challenging one with limited tool support. This thesis examines various aspects related to the translation of algorithms, given in infinite precision or floating-point, into fixed-point. In particular, this thesis reports on the implementation of a given algorithm, an EDFA (Erbium-Doped Fibre Amplifier) control algorithm, on a FPGA (Field Programmable Gate Array) us

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47

Hanriat, Stéphane. "Synthèse logique à base de règles pour les compilateurs de silicium." Phd thesis, Grenoble INPG, 1986. http://tel.archives-ouvertes.fr/tel-00322203.

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L'optimisation de la synthèse logique de circuits dépend de la structure matérielle cible pour les circuits combinatoires (logique aléatoire, réseaux prédiffusés, PLA...) ainsi que de l'architecture choisie par le concepteur pour les circuits plus complexes (contrôleur). On propose un système de synthèse flexible à base de règles (système ASYL). Ces règles traduisent les critères d'optimisation des structures cibles ainsi que les choix de conception. L'illustration pratique concerne essentiellement la synthèse des fonctions booléennes sur PLA et la synthèse de contrôleur

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48

Stamenkovich, Joseph Allan. "Enhancing Trust in Autonomous Systems without Verifying Software." Thesis, Virginia Tech, 2019. http://hdl.handle.net/10919/89950.

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The complexity of the software behind autonomous systems is rapidly growing, as are the applications of what they can do. It is not unusual for the lines of code to reach the millions, which adds to the verification challenge. The machine learning algorithms involved are often "black boxes" where the precise workings are not known by the developer applying them, and their behavior is undefined when encountering an untrained scenario. With so much code, the possibility of bugs or malicious code is considerable. An approach is developed to monitor and possibly override the behavior of autonomous

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49

Perez, Segovia Tomás. "Paola : un système d'optimisation topologique de PLA." Grenoble INPG, 1985. http://tel.archives-ouvertes.fr/tel-00316330.

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Lors de la conception des circuits intégrés VLSI, les Réseaux Logiques Programmables (P. L. A. ) permettent le dessin automatique des masques à partir d'une description logique. La surface occupée par ces PLAs peut, dans certains cas, s'avérer prohibitive; d'où l'intérêt des méthodes d'optimisation topologique de ceux-ci. Après avoir défini les différentes représentations possibles des PLAs, on présente l'état en ce qui concerne l'optimisation topologique des PLAs. La méthode des «Lignes Brisées» est ensuite détaillée en insistant sur les heuristiques choisies ainsi que sur les interactions qu

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50

Choudens, Philippe de. "Test intégré de processeur facilement testable." Grenoble INPG, 1985. http://tel.archives-ouvertes.fr/tel-00319265.

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Un test permet d'assurer la sécurité de fonctionnement des circuits VLSI. La première partie montre l'intérêt dans un tel contexte d'un processeur facilement testable; la deuxième partie développe pour de tels microprocesseurs une stratégie de test. Dans la troisième partie est traité le problème de la définition des vecteurs de test des circuits logiques programmables. Développement d'un test pour multiplieur itératif

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