Dissertations / Theses on the topic 'RF Front-ends'

The objective of this research is to explore the possibilities of developing transmit/receive (T/R) modules using silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) BiCMOS technology to integrate with organic liquid crystal polymer (LCP) packages for the next-generation phased-array radar system. The T/R module requirements are low power, compact, lightweight, low cost, high performance, and high reliability. All these requirements have provided a very strong motivation for developing fully monolithic T/R modules. SiGe HBT BiCMOS technology is an excellent candidate to integrate all the RF circuit blocks on the T/R module into a single die and thus, reducing the overall cost and size of the phase-array radar system. In addition, this research also investigates the effects and the modeling issues of LCP package on the SiGe circuits at X-band.

<p>Most of today’s microwave circuits are designed for specific function and specialneed. There is a growing trend to have flexible and reconfigurable circuits. Circuitsthat can be digitally programmed to achieve various functions based on specific needs. Realization of high frequency circuit blocks that can be dynamically reconfigured toachieve the desired performance seems to be challenging. However, with recentadvances in many areas of technology these demands can now be met.</p><p>Two concepts have been investigated in this thesis. The initial part presents thefeasibility of a flexible and programmable circuit (PROMFA) that can be utilized formultifunctional systems operating at microwave frequencies. Design details andPROMFA implementation is presented. This concept is based on an array of genericcells, which consists of a matrix of analog building blocks that can be dynamicallyreconfigured. Either each matrix element can be programmed independently or severalelements can be programmed collectively to achieve a specific function. The PROMFA circuit can therefore realize more complex functions, such as filters oroscillators. Realization of a flexible RF circuit based on generic cells is a new concept.In order to validate the idea, a test chip has been fabricated in a 0.2μm GaAs process, ED02AH from OMMIC^TM. Simulated and measured results are presented along withsome key applications like implementation of a widely tunable band pass filter and anactive corporate feed network.</p><p>The later part of the thesis covers the design and implementation of tunable andwideband highly linear LNAs that can be very useful for multistandard terminals suchas software defined radio (SDR). One of the key components in the design of a flexibleradio is low noise amplifier (LNA). Considering a multimode and multiband radiofront end, the LNA must provide adequate performance within a large frequency band.Optimization of LNA performance for a single frequency band is not suitable for thisapplication. There are two possible solutions for multiband and multimode radio frontends (a) Narrowband tunable LNAs (b) Wideband highly linear LNAs. A dual bandtunable LNA MMIC has been fabricated in 0.2μm GaAs process. A self tuningtechnique has also been proposed for the optimization of this LNA. This thesis alsopresents the design of a novel highly linear current mode LNA that can be used forwideband RF front ends for multistandard applications. Technology process for thiscircuit is 90nm CMOS.</p>

The pursuit of dense monolithic integration and higher operating speed continues to push the integrated circuit (IC) fabrication technologies to their limits. The increasing process variation, associated with aggressive technology scaling, is having a negative impact on circuit yield in current IC technologies, and the problem is likely to become worse in the future. Circuit solutions that are more tolerant of the process variations are needed to fully utilize the benefits of technology scaling. The primary goal of this research is to develop high-frequency circuits that can deliver consistent performance even under the threat of increasing process variation. These circuits can be used to build ``self-healing" systems, which can detect process imperfections and compensate accordingly to optimize performance. In addition to improving yield, such adaptive circuits and systems can provide more robust and efficient solutions for a wide range of applications under varying operational and environmental conditions.Silicon-germanium (SiGe) BiCMOS technology is an ideal platform for highly integrated systems requiring both high-performance analog and radio-frequency (RF) circuits as well as large-scale digital functionality. This research is focused on designing circuit components for a high-frequency wideband self-healing receiver in SiGe BiCMOS technology. An adaptive image-reject mixer, low insertion-loss switches, a wideband low-noise amplifier (LNA), and a SiGe complementary LC oscillator were designed. Healing algorithms were developed, and automated self-healing of multiple parameters of the mixer was demonstrated in measurement. A monte-carlo simulation based methodology was developed to verify the effectiveness of the healing procedure. In summary, this research developed circuits, algorithms, simulation tools, and methods that are useful for building "self-healing" systems.

This thesis presents novel millimeter-wave microelectromechanical-systems (MEMS) components for W-band reconfigurable beam-steering front-ends. The proposed MEMS components are novel monocrystalline-silicon dielectric-block phase shifters, and substrate-integrated three-dimensional (3D) micromachined helical antennas designed for the nominal frequency of 75 GHz. The novel monocrystalline-silicon dielectric-block phase shifters are comprised of multi-stages of a tailor-made monocrystalline-silicon block suspended on top of a 3D micromachined coplanar-waveguide transmission line. The relative phase-shift is obtained by vertically pulling the suspended monocrystalline-silicon block down with an electrostatic actuator, resulting in a phase difference between the up and downstate of the silicon block. The phase-shifter prototypes were successfully implemented on a high-resistivity silicon substrate using standard cleanroom fabrication processes. The RF and non-linearity measurements indicate that this novel phase-shifter design has an excellent figure of merit that offers the best RF performance reported to date in terms of loss/bit at the nominal frequency, and maximum return and insertion loss over the whole W-band, as compared to other state-of-the-art MEMS phase shifters. Moreover, this novel design offers high power handling capability and superior mechanical stability compared to the conventional MEMS phase-shifter designs, since no thin moving metallic membranes are employed in the MEMS structures. This feature allows MEMS phase-shifter technology to be utilized in high-power applications. Furthermore, the return loss of the dielectric-block phase shifter can be minimized by appropriately varying the individual distance between each phase-shifting stage. This thesis also investigates 3D micromachined substrate-integrated W-band helical antennas. In contrast to conventional on-chip antenna designs that only utilize the surface of the wafer, the novel helical radiator is fully embedded into the substrate, thereby utilizing the whole volume of the wafer and resulting in a compact high-gain antenna design. The performance of the antenna is substantially enhanced by properly etching the substrate, tailor making the antenna core, and by modifying size and geometry of the substrate-integrated ground plane. A linear line antenna array is composed of eight radiating elements and is demonstrated by simulations. Each antenna is connected to the input port through a multi-stage 3-dB power divider. The input and output of the single-stage 3-dB power divider is well matched to the 50-Ω impedance by four-section Chebyshev transformers. The simulation results indicate that the novel helical antenna arrays offer a narrow radiation beam with an excellent radiation gain that result in high-resolution scan angles on the azimuth plane. The proposed helical antenna structures can be fabricated by employing standard cleanroom micromachining processes.<br>QC 20120427

This dissertation deals with the development of RF MEMS switches with novel materials and micromachining techniques for the RF and microwave applications. To enable the integration of RF and microwave components on CMOS grade silicon, finite ground coplanar waveguide transmission line on CMOS grade silicon wafer were first studied using micromachining techniques. In addition, several RF MEMS capacitive switches were developed with novel materials. A novel approach for fabricating low cost capacitive RF MEMS switches using directly photo-definable high dielectric constant metal oxides was developed, these switches exhibited significantly higher isolation and load capacitances as compared to comparable switches fabricated using a simple silicon nitride dielectric. The second RF MEMS switch developed is on a low cost, flexible liquid crystal polymer (LCP) substrate. Its very low water absorption (0.04%), low dielectric loss and multi-layer circuit capability make it very appealing for RF Systems-On-a-Package (SOP). Also, a tunable RF MEMS switch on a sapphire substrate with BST as dielectric material was developed, the BST has a very high dielectric constant (>300) making it very appealing for RF MEMS capacitive switches. The tunable dielectric constant of BST provides a possibility of making linearly tunable MEMS capacitor-switches. For the first time a capacitive tunable RF MEMS switch with a BST dielectric and its characterization and properties up to 40 GHz was presented. Dielectric charging is the main reliability issue for MEMS switch, temperature study of dielectric polarization effect of RF MEMS was investigated in this dissertation. Finally, integration of two reconfigurable RF circuits with RF MEMS switches were discussed, the first one is a reconfigurable dual frequency (14GHz and 35 GHz) antenna with double polarization using RF MEMS switches on a multi-layer LCP substrate; and the second one is a center frequency and bandwidth tunable filter with BST capacitors and RF MEMS switches on sapphire substrate.

The objective of the research presented in this dissertation is to explore the achievable dynamic range limits in high-performance RF front-ends designed using SiGe HBTs, with a focus on complementary (npn + pnp) SiGe technologies. The performance requirements of RF front-ends are high gain, high linearity, low dc power consumption, very low noise figure, and compactness. The research presented in this dissertation shows that all of these requirements can easily be met by using complementary SiGe HBTs. Thus, a strong case is made in favor of using SiGe technologies for designing high dynamic range RF front-ends. The contributions from this research are summarized as follows: 1. The first-ever comparison study and comprehensive analysis of small-signal linearity (IIP3) for npn and pnp SiGe HBTs on SOI. 2. A novel comparison of large-signal robustness of npn and pnp SiGe HBTs for use in high-performance RF front-ends. 3. A systematic and rigorous comparison of SiGe HBT compact models for high-fidelity distortion modeling. 4. The first-ever feasibility study of using weakly-saturated SiGe HBTs for use in severely power constrained RF front-ends. 5. A novel X-band Low Noise Amplifier (LNA) using weakly-saturated SiGe HBTs. 6. Design and comprehensive analysis of RF switches with enhanced large-signal linearity. 7. Development of novel methods to reduce crosstalk noise in mixed-signal circuits and the first-ever analysis of crosstalk noise across temperature. 8. Design of a very high-linearity cellular band quadrature modulator for use in base-station applications using first-generation complementary SiGe HBTs.

The objective of this research is to understand the design and performance of state-of-the-art silicon-germanium (SiGe) BiCMOS high-frequency circuits for phased- array radar and wireless communication systems operating in extreme environment conditions. This work investigates the performance of RF circuits over a wide- temperature and exposure to a radiation intensive environment. The design and characterization of a fully integrated transmit/receive (T/R) module and integra- tion onto a multi-element antenna array is presented. In addition, individual circuit blocks are characterized in these extreme environments.

System-on-Chip (SoC) was adopted in recent years as one of the solutions to reduce the cost of integrated systems. When the SoC solution started to be used, the final product was actually more expensive due to lower yield. The developments in integrated technology through the years allowed the integration of more components in lesser area with a better yield. Thus, SoCs became a widely used solution to reduced the cost of the final product, integrating into a single-chip the main parts of a system: analog, digital and memory. As integrated technology kept scaling down to allow a higher density of transistors and thus providing more functionality with the same die area, the analog RF parts of the SoC became a bottleneck to cost reduction as inductors occupy a large die area and do not scale down with technology. Hence, the trend moves toward the research and design of inductor-less SoCs that further reduce the cost of the final solution. Also, as the demand for home networking high-data-rates communication systems has increased over the last decade, several standards have been developed to satisfy the requirements of each application, the most popular being wireless local area networks (WLANs) based on the IEEE 802.11 standard. However, poor signal propagation across walls make WLANs unsuitable for high-speed applications such as high-definition in-home video streaming, leading to the development of wired technologies using the existing in-home infrastructure. The ITU-T G.hn recommendation (G.9960 and G.9961) unifies the most widely used wired infrastructures at home (coaxial cables, phone lines and power lines) into a single standard for high-speed data transmission of up to 1 Gb/s. The G.hn recommendation defines a unified networking over power lines, phone lines and coaxial cables with different plans for baseband and RF. The RF-coax bandplan, where this thesis is focused, uses 50 MHz and 100 MHz bandwidth channels with 256 and 512 carriers respectively. The center frequency can range from 350 MHz to 2450 MHz. The recommendation specifies a transmission power limit of 5 dBm for the 50 MHz bandplan and 8~dBm for the 100 MHz bandplan, therefore the maximum transmitted power in each carrier is the same for both bandplans. Due to the nature of an in-home wired environment, receivers that can handle both very large and very small amplitude signals are required; when transmitter and receiver are connected on the same electric outlet there is no channel attenuation and the signal-to-noise-plus-distortion ratio (SNDR) is dominated by the receiver linearity, whereas when transmitter and receiver are several rooms apart channel attenuation is high and the SNDR is dominated by the receiver noise figure. The high dynamic range specifications for these receivers require the use of configurable-gain topologies that can provide both high-linearity and low-noise for different configurations. Thus, this thesis has been aimed at researching high dynamic range broadband inductor-less topologies to be used as the RF front-end for a G.hn receiver complying with the provided specifications. A large part of the thesis has been focused on the design of the input amplifier of the front-end, which is the most critical stage as the noise figure and linearity of the input amplifier define the achievable overall specifications of the whole front-end. Three prototypes has been manufactured using a 65 nm CMOS process: two input RFPGAs and one front-end using the second RFPGA prototype.<br>El "sistema en un chip" (SoC) fue adoptado recientemente como una de las soluciones para reducir el coste de sistemas integrados. Cuando se empezó a utilizar la solución SoC, el producto final era más caro debido al bajo rendimiento de producción. Los avances en tecnología integrada a lo largo de los años han permitido la integración de más componentes en menos área con mejoras en rendimiento. Por lo tanto, SoCs pasó a ser una solución ampliamente utilizada para reducir el coste del producto final, integrando en un único chip las principales partes de un sistema: analógica, digital y memoria. A medida que las tecnologías integradas se reducían en tamaño para permitir una mayor densisdad de transistores y proveer mayor funcionalidad con la misma área, las partes RF analógicas del SoC pasaron a ser la limitación en la reducción de costes ya que los inductores ocupan mucha área y no escalan con la tecnología. Por lo tanto, las tendencias en investigación se mueven hacia el diseño de SoCs sin inductores que todavía reducen más el coste final del producto. También, a medida que la demanda en sistemas de comunicación domésticos de alta velocidad ha crecido a lo largo de la última década, se han desarrollado varios estándares para satisfacer los requisitos de cada aplicación, siendo las redes sin hilos (WLANs) basadas en el estándar IEEE 802.11 las más populares. Sin embargo, una pobre propagación de señal a través de las paredes hacen que las WLANs sean inadecuadas para aplicaciones de alta-velocidad como transmisión de vídeo de alta definición en tiempo real, resultando en el desarrollo de tecnologías con hilos utilizando la infraestructura existente en los domicilios. La recomendación ITU-T G.hn (G.9960 and G.9961) unifica las principales infraestructuras con hilos domésticas (cables coaxiales, línias de teléfono y línias de electricidad) en un sólo estándar para la transmisión de datos hasta 1 Gb/s. La recomendación G.hn define una red unificada sobre línias de electricidad, de teléfono y coaxiales con diferentes esquemas para banda base y RF. El esquema RF-coax en el cual se basa esta tesis, usa canales con un ancho de banda de 50 MHz y 100 MHz con 256 y 512 portadoras respectivamente. La frecuencia centra puede variar desde 350 MHz hasta 2450 MHz. La recomendación especifica un límite en la potencia de transmisión de 5 dBm para el esquema de 50 MHz y 8 dBm para el esquema de 100 MHz, de tal forma que la potencia máxima por portadora es la misma en ambos esquemas. Debido a la estructura de un entorno doméstico con hilos, los receptores deben ser capaces de procesar señales con amplitud muy grande o muy pequeña; cuando transmisor y receptor están conectados en la misma toma eléctrica no hay atenuación de canal y el ratio de señal a rudio más distorsión (SNDR) está dominado por la linealidad del receptor, mientras que cuando transmisor y receptor están separados por varias habitaciones la atenuación es elevada y el SNDR está dominado por la figura de ruido del receptor. Los elevados requisitos de rango dinámico para este tipo de receptores requieren el uso de topologías de ganancia configurable que pueden proporcionar tanto alta linealidad como bajo ruido para diferentes configuraciones. Por lo tanto, esta tesis está encarada a la investigación de topologías sin inductores de banda ancha y elevado rango dinámico para ser usadas a la entrada de un receptor G.hn cumpliendo con las especificaciones proporcionadas. Una gran parte de la tesis se ha centrado en el diseño del amplificador de entrada al ser la etapa más crítica, ya que la figura de ruido y linealidad del amplificador de entrada definen lás máximas especificaciones que el sistema puede conseguir. Se han fabricado 3 prototipos con un proceso CMOS de 65 nm: 2 amplificadores y un sistema completo con amplificador y mezclador.

The design of an analog frontend including a receiver amplifier (RX) and laser diode driver (LDD) for optical communication system is described. The RX consists of a transimpedance amplifier, a limiting amplifier, and an output buffer (BUF). An offset compensation and common-mode control circuit is designed using switched-capacitor technique to save chip area, provides continuous reduction of the offset in the RX. Active-peaking methods are used to enhance the bandwidth and gain. The very low gate-oxide breakdown voltage of transistors in deep sub-micron technologies is overcome in the LDD by implementing a topology which has the amplifier placed in a floating well. It comprises a level shifter, a pre-amplifier, and the driver stage. The single-chip frontend, fabricated in a 28 nm bulk-digital complementary metal–oxide–semiconductor (CMOS) process has a total active area of 0.003 mm² , is among the smallest optical frontends. Without the BUF, which consumes 8 mW from a separate supply, the RX power consumption is 21 mW, while the LDD consumes 32 mW. Small-signal gain and bandwidth are measured. A photo diode and laser diode are bonded to the chip on a test-printed circuit board. Electro-optical measurements show an error-free detection with a bit error rate of 10⁻¹² at 20 Gbit/s of the RX at and a 25 Gbit/s transmission of the LDD.

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.<br>Includes bibliographical references (leaves 169-173).<br>In the Wireless-Gigabit-Local-Area-Network (WiGLAN) project, we proposes a system architecture that adopts multiple antennas [1, 2, 3, 4] to control the trade-off between data rate and transmission quality [5, 6] through Space-Time Coding (STC) [7, 8, 9] and Orthogonal Frequency Division Multiplexing (OFDM). However, along the multiple RF front-ends, there are multiple nodes that signal cross-talk can occur. Such signal cross-talk occurring on a silicon chip becomes more and more significant as the integration level and operating radio frequency rise, seriously degrading the system performance, the data rate and transmission quality. Most of the literature about on-chip crosstalk suppression have been focusing on adopting various process-technology techniques, such as using guard ring structures to separate the parallel RF front ends or inserting a ground plane to shield the cross-talk. In this study, we will take a different approach. We will investigate the effects of on-chip cross-talk upon the operations of the coding and modulation schemes adopted in the WiGLAN system and explore methods, other than those mentioned, to counteract them.<br>by Jie De Jacky Liang.<br>S.M.

<p>The explosive development of wireless communication services creates a demand for more flexible and cost-effective communication systems that offer higher data rates. The obvious trend towards small-size and ultra low power systems, in combination with the ever increasing number of applications integrated in a single portable device, tightens the design constraints at hardware and software level. The integration of current mobile systems with the third generation systems exemplifies and emphasizes the need of monolithic multi-band transceivers. A long term goal is a software defined radio, where several communication standards and applications are embedded and reconfigured by software. This motivates the need for highly flexible and reconfigurable analog radio frequency (RF) circuits that can be fully integrated in standard low-cost complementary metal-oxide-semiconductor (CMOS) technologies.</p><p>In this thesis, the Voltage-Controlled Oscillator (VCO), one of the main challenging RF circuits within a transceiver, is investigated for today’s and future communication systems. The contributions from this work may be divided into two parts. The first part exploits the possibility and design related issues of wide-band reconfigurable integrated VCOs in CMOS technologies. Aspects such as frequency tuning, power dissipation and phase noise performance are studied and design oriented techniques for wide-band circuit solutions are proposed. For demonstration of these investigations several fully functional wide-band multi-GHz VCOs are implemented and characterized in a 0.18µm CMOS technology.</p><p>The second part of the thesis concerns theoretical analysis of phase noise in VCOs. Due to the complex process of conversion from component noise to phase noise, computer aided methods or advanced circuit simulators are usually used for evaluation and prediction of phase noise. As a consequence, the fundamental properties of different noise sources and their impact on phase noise in commonly adopted VCO topologies have so far not been completely described. This in turn makes the optimization process of integrated VCOs a very complex task. To aid the design and to provide a deeper understanding of the phase noise mechanism, a new approach based on a linear time-variant model is proposed in this work. The theory allows for derivation of analytic expressions for phase noise, thereby, providing excellent insight on how to minimize and optimize phase noise in oscillators as a function of circuit related parameters. Moreover, it enables a fair performance comparison of different oscillator topologies in order to ascertain which structure is most suitable depending on the application of interest. The proposed method is verified with very good agreement against both advanced circuit simulations and measurements in CMOS and bipolar technologies. As a final contribution, using the knowledge gained from the theoretical analysis, a fully integrated 0.35µm CMOS VCO with superior phase noise performance and power dissipation is demonstrated.</p>

The growing demand for wireless communication systems is driving the integration of radio frequency (RF) front-ends on the same chip with multi-band functionality and higher spectral efficiency. Microelectromechanical systems (MEMS) have an overarching applicability to RF communications and are critical components in facilitating this integration process. Among a variety of RF MEMS devices, piezoelectric MEMS resonators have sparked significant research and commercial interest for use in oscillators, filters, and duplexers. Compared to their bulky quartz crystal and surface acoustic wave (SAW) counterparts, MEMS resonators exhibit impressive advantages of compact size, lower production cost, lower power consumption, and higher level of integration with CMOS fabrication processes. One of the promising piezoelectric MEMS resonator technologies is the aluminum nitride (AlN) contour mode resonator (CMR). On one hand, AlN is chemically stable and offers superior acoustic properties such as large stiffness and low loss. Furthermore, CMRs offer low motional resistance over a broad range of frequencies (few MHZ to GHz), which are lithographically-definable on the same silicon substrates. To date, RF MEMS resonators (include CMRs) have been extensively studied; however, one aspect that was not thoroughly investigated is how to modulate/tune their equivalent parameters to enhance their performance in oscillators and duplexers. The goal of this thesis is to investigate various modulation methods to improve the thermal stability of the resonator, its “effective” quality factor when used in an oscillator, and build completely novel non-reciprocal components. Broadly defined, modulation refers to the exertion of a modifying or controlling influence on something, herein specifically, the resonator admittance. In this thesis, three categories of modulation methods are investigated: thermal modulation, force modulation, and external electronic modulation. Firstly, the AlN CMR’s center frequency can be tunned by the applied thermal power to the resonator body. The resonator temperature is kept constant (for example, 90 °C) via a temperature sensor and feedback control such that the center frequency is stable over the whole operation temperature range of interest (e.g. –35 to 85 °C). The maximum power consumption to sustain the maximum temperature difference (120 ºC in this thesis) between resonator and ambient is reduced to a value as low as 353 μW – the lowest ever reported for any MEMS device. These results were attained while simultaneously maintaining a high quality factor (up to 4450 at 220 MHz device). The feedback control was implemented by either analog circuits or via a microprocessor. The analog feedback control, which innovatively utilized a dummy resistor to compensate for temperature gradients, resulted in a total power consumption of 3.8 mW and a frequency stability of 100 ppm over 120 ºC. As for the digital compensation, artificial neural network algorithm was employed to facilitate faster calibration of look-up tables for multiple frequencies. This method attained a frequency stability of 14 ppm over 120 ºC. The second modulation method explored in this thesis is based on the use of an effective external force to enhance the 3-dB quality factor of AlN CMRs and improve the phase noise performance of resonator-based oscillators. The force modulation method was embodied in a two-port device, where one of the two ports is used as a one-port resonator and the other is driven by an external signal to effectively apply an external force to the first port. Through this technique, the quality factor of the resonator was boosted by 140 times (up to 150,000) and the phase noise of the corresponding oscillator realized using the resonator was reduced by 10 dBc/Hz. Lastly, a novel magnetic-free electrical circulator topology that facilitates the development of in-band full duplexers (IBFD) for simultaneous transmit and receive (STAR) is proposed and modeled. Fundamentally, a linear time-invariant (LTI) filter network parametrically modulated via a switching matrix is used to break the reciprocity of the filter. The developed model accurately predicts the circulator behavior and shows very good agreement with the experimental results for a 21.4 MHz circulators built with MiniCircuit filter and switch components. Furthermore, a high frequency (1.1 GHz) circulator was synthesized based on AlN MEMS bandpass filters and CMOS RF switches, hence showing a compact approach that can be used in handheld devices. The modulation frequency and duty cycle are optimized so that the circulator can provide up to 15 dB of isolation over the filter bandwidth while good power transfer between the other two ports is maintained. The demonstrated device is expected to intrinsically offer low noise and high linearity. The combination of the first two modulation methods facilitates the implementation of monolithic, temperature-stable, ultra-low noise, multi-frequency oscillator banks. The third modulation technique that was investigated sets the path for the development of CMOS-compatible in-band full duplexers for simultaneous transmit and receive and thus facilitates the efficient utilization of the electromagnetic spectrum. With the aid of all these three modulation approaches, the author believes that a fully integrated, multi-frequency, spectrum-efficient transceiver is enabled for next-generation wireless communications.

The investigation of liquid crystal polymer (LCP) technology to function as a low-cost next-generation organic platform for designs up to millimeter-wave frequencies has been performed. Prior to this research, the electrical performance of LCP had been characterized only with the implementation of standard transmission lines and resonators. In this research, a wide variety of passive functions have been developed on LCP technology and characterized for the first time. Specifically, we present the development of patch antenna arrays for remote sensing applications, the performance of compact low-pass and band-pass filters up to millimeter-wave frequencies, and the integration of passive elements for X-band and V-band transceiver systems. First, dual-frequency/dual-polarization antenna arrays have been developed on multilayer LCP technology and have been integrated with micro-electro-mechanical-system (MEMS) switches to achieve real-time polarization reconfigurability. These arrays are conformal, efficient and have all the features desirable for applications that require space deployment. Second, a wide variety of filters with different physical and functional characteristics have been implemented on both single and multilayer LCP technology. These filters can be classified based on the filter type (low-pass/band-pass), the resonators used (single-mode/dual-mode), the response characteristics (symmetric/asymmetric), and the structure of the filter (modular/non-modular). Last, examples of integrated modules for use in transceiver systems are presented. This part of the research involves the development of duplexers, radiating elements, as well as their integration. The duplexers themselves are realized by integrating a set of band-pass filters and matching networks. The characterization of the individual components, and of the integrated system are included. This research has resulted in a thorough understanding of LCP's electrical performance and its multilayer lamination capabilities pertaining to its functioning as a material platform for integrated microwave systems. Novel passive prototypes that can take advantage of such multilayer capabilities have been developed.

碩士<br>國立臺北科技大學<br>電子工程系<br>106<br>This thesis is divided into two sections, the first section using 0.18 µm CMOS process which is provided by Taiwan Semiconductor Manufacturing Company (TSMC) and glass-integrated passive device (GIPD) process which is provided by Walsin Technology Company to implementation the dual-mode VCO. The VCO switches the different modes by switching the turn on and turn off of the two sets of NMOS switches, using the GIPD process to design the transformers used in the circuit, and through the GIPD process to improve the disadvantages of high loss and low quality factor of the passive circuit components. The tuning range of chip measurement results is 19.3% and 17.7%, and the power consumption of the core circuits is respectively 0.57 mW and 2.37 mW. The second section uses CMOS MEMS process provided by TSMC to implementation the design of the wideband amplifier. The inductor in the circuit is used to reduce the whole area of the chip by using the stack inductance. The circuit design adopts the resistance-feedback technology to achieve the increase of the overall gain of the circuit, and reduces the voltage and power consumption is reduced by the technology of the self-forward body bias. By using the MEMS process without affecting the characteristics of the CMOS circuit, reducing the parasitic capacitance to improve the overall characteristics of the circuit, and the MEMS process does not affect the reliability of the CMOS circuit. Measurement results |S11| at 3.1~10.6 GHz are relatively below 10 dB ,the |S21| Max gain in 16 dB, measured P1dB respectively -13 dBm.

Ultra-Wideband (UWB) technology has become one of the hottest topics in wireless communications, for it provides cost-effective, power-efficient, high bandwidth solution for relaying data in the immediate area (up to 10 meters). This work demonstrates two different solutions for the RF front-end designs in the UWB receivers, one is distributed topology, and the other is based on traditional lumped element topology. The distributed amplifier is one of the attractive candidates for UWB Low Noise Amplifier (LNA). The design, analysis and operation of the distributed amplifiers will be presented. A distributed amplifier is designed with Coplanar Waveguide (CPW) transmission lines in 0.25-μm CMOS process for time domain UWB applications. New design techniques and new topologies are developed to enhance the power-efficiency and reduce the chip area. A compact and high performance distributed amplifier with Patterned Grounded Shield (PGS) inductors is developed in 0.25-μm CMOS process. The amplifier has a measurement result of 7.2dB gain, 4.2-6dB noise figure, and less than -10dB return loss through 0-11GHz. A new distributed amplifier implementing cascade common source gain cells is presented in 0.18-μm CMOS. The new amplifier demonstrates a high gain of 16dB at a power consumption of 100mW, and a gain of 10dB at a low power consumption of 19mW. A UWB LNA utilizing resistive shunt feedback technique is reported in 0.18-μm CMOS process. The measurement results of the UWB LNA demonstrate a maximum gain of 10.5dB and a noise figure of 3.3-4.5dB from 3-9.5GHz, while only consuming 9mW power. Based on the distributed amplifier and resistive shunt-feedback amplifier designs, two UWB RF front-ends are developed. One is a distributed LNA-Mixer. Unlike the conventional distributed mixer, which can only deliver low gain and high noise figure, the proposed distributed LNA-Mixer demonstrates 12-14dB gain ,4-5dB noise figure and higher than 10dB return loss at RF and LO ports over 2-16GHz. To overcome the power consumption and chip area problems encountered in distributed circuits, another UWB RF front-end is also designed with lumped elements. This front-end, employing resistive shunt-feedback technique into its LNA design, can achieve a gain of 12dB and noise figure of 8-10dB through 3-10GHz, the return loss of less than -10dB from 3- 10GHz at RF port, and less than -7dB at LO port, while only consuming 25mA current from 1.8V voltage supply.

碩士<br>國立臺北科技大學<br>電子工程系研究所<br>103<br>This paper discuss the radar which detects the Doppler shift caused by breathe and heartbeats. By the detection theory, we can design the Doppler radar for vital-sign sensing. The architecture of conventional transceiver include oscillator, power amplifier, and low noise amplifier, the quality of detection signals are decided by the performance of transceiver. Compare to the traditional architectures of vital-sign sensors, the proposed vital-sign sensors are based on injection-locked oscillator. The advantages of this sensors are less complex and no need of low noise amplifier at receiver. To prevent the null detection points, the IQ demodulators are used in this design. In this paper, the components of transceivers are design and implement on FR4, include Clapp oscillator based on BJT, circulators, IQ demodulator, and baseband active band pass filters. Test the sensor can sense the frequencies of breathe and hearts beat away from subjects about 80 cm with an error rate 4 % and IQ demodulator can solve the null detection point. This thesis also complete a fully integrated vital-sign sensor by using TSMC 0.18μm CMOS technology, include a VCO with injection port and an IQ demodulator made by mixers and RC phase shifter. To improve the ability of sensor, the baseband active band pass filter are required.

Enhancing the digital controllability of wideband RF transceiver front-ends helps in widening the range of operating conditions and applications in which such systems can be employed. Technology limitations and design challenges often constrain the extensive adoption of digital controllability in RF front-ends. This work focuses on three major aspects associated with the design and implementation of a digitally controllable RF transceiver front-end for enhanced digital control. Firstly, the influence of the choice of semiconductor technology for a system-on-chip integration of digital gain control circuits are investigated. The digital control of gain is achieved by utilizing step attenuators that consist of cascaded switched attenuation stages. A design methodology is presented to evaluate the influence of the chosen technology on the performance of the three conventionally used switched attenuator topologies for desired attenuation levels, and the constraints that the technology suitable for high amplification places on the attenuator performance are examined. Secondly, a novel approach to the integrated implementation of gain slope equalization is presented, and the suitability of the proposed approach for integration within the RF front-end is verified. Thirdly, a sensitivity-aware implementation of a peak power detector is presented. The increased employment of digital gain control also increases the requirements on the sensitivity of the power detector employed for adaptive power and gain control. The design, implementation, and measurement results of a state-of-the-art wideband power detector with high sensitivity and large dynamic range are presented. The design is optimized to provide a large offset cancellation range, and the influence of offset cancellation circuits on the sensitivity of the power detector is studied. Moreover, design considerations for high sensitivity performance of the power detector are investigated, and the noise contributions from individual sub-circuits are evaluated. Finally, a wideband RF transceiver front-end is realized using a commercially available SiGe BiCMOS technology to demonstrate the enhancements in the digital controllability of the system. The RF front-end has a bandwidth of 500 MHz to 2.5 GHz, an input dynamic range of 20 dB, a digital gain control range larger than 30 dB, a digital gain slope equalization range from 1.49 dB/GHz to 3.78 dB/GHz, and employs a power detector with a sensitivity of -56 dBm and dynamic range of 64 dB. The digital control in the RF front-end is implemented using an on-chip serial-parallel-interface (SPI) that is controlled by an external micro-controller. A prototype implementation of the RF front-end system is presented as part of an RFIC intended for use in optical transceiver modules for fiber-to-the-x applications.

Modern wireless communication systems require low-cost, compact, and highly integrated tunable components such as filters, phase shifters, frequency-agile antennas, and adaptive impedance matching networks. One basic element of these components is the tunable capacitor (varactor). Among other technologies, ferroelectric thin-film varactors exhibit high power handling, low tuning voltage, quick response, high capacitance density, and good adaptability into the microwave frequency range (DC to 20 GHz). In particular, BST-based thin-film varactors have an excellent potential to reduce size, weight, cost, and to improve the functionality of wireless communication systems. Electric losses of thin-film ferroelectric varactors depend highly on the loss of the dielectric layer. In general, the choice of the bottom electrode material has a big influence on the dielectric properties and the total losses. For this reason, efforts were made to use conducting oxide materials as bottom electrodes, enabling the deposition of a dielectric layer with low defect density and misfit strain. However, due to the high electrical resistivity of the so far used electrode materials, it was concluded that oxide electrodes are too resistive for integration into microwave varactors. In this work, the SrMoO3 as a highly conducting perovskite material was integrated for the first time as the bottom electrode into thin-film BST-based varactors. Epitaxial SrTiO3/SrMoO3/SrTiO3/Ba0.4Sr0.6TiO3 heterostructure was grown onto (110) GdScO3 substrate using Pulsed Laser Deposition (PLD). The microstructure of the deposited layers was characterized by X-ray diffraction techniques and Scanning Transmission Electron Microscopy (STEM). It was shown that epitaxial growth of the SrTiO3/SrMoO3/SrTiO3/Ba0.4Sr0.6TiO3 stack, locked commensurately to the GdScO3 substrate, is possible. Moreover, optimization of the deposition conditions resulted in homogeneous, single-phase growth of all the layers with low mosaicity and excellent crystal quality. Using lift-off lithography, Pt/Au top electrodes were deposited by Magnetron Sputtering to enable the electrical characterization of the MIM-structured varactors. It was shown that a tunability of 50% is achievable by applying small biasing voltage of 8V. Furthermore, a quality factor of 180 at 30 MHz suggests a very low dielectric loss at the Ba0.4Sr0.6TiO3. A commutation Quality Factor (CQF) of 10000 at 100 MHz shows the potential of SrMoO3 for integration into devices for microwave applications. As an initial step towards industrialization of this technology, a selective etching procedure for processing and fabrication of SrMoO3-based electronic devices was established.

The development of integrated circuits has been governed by Moore's law for several decades. Through continuous advancements in CMOS technology, the industry has maintained exponential progress rates in transistor miniaturization and integration density. However, this technology scaling trend is only conditionally beneficial for analog circuit performance. Compared with the analog circuits, digital circuits are cheaper, faster, more complex, and more power efficient. Due to these reasons, the researchers are undertaking a paradigm shift from high performance analog circuits to digitally assisted analog circuits. Adaptive impedance matching techniques are attractive because they provide resilience to antenna impedance variation caused by body-effects and several other reasons. In principle, they can preserve maximum radiated power, power amplifier linearity, receiver sensitivity, and power efficiency of a mobile phone simultaneously. However, achieving proper adaptive impedance control over a large impedance region is a challenge. Recent analog and RF circuits are increasing performance and efficiency with the aid of digital technology. To apply this technique to a reconfigurable antenna system, a fully integrated micro-controller based on AMS H35 technology has been designed. Digital calibration blocks wrapped around an analog core are capable of performing dead time and impedance matching schemes. Therefore, the intelligence and robustness of the system are improved significantly. Furthermore, compared with S11 controller (18.8mm2, 186mW), the silicon area of the digitally assisted circuit (4mm2, 62mW) is acceptable. In addition, this dissertation presents a set of convergence criteria for the tunable matching network, which leads to the finding of matching point with high probability. Furthermore, to accelerate the convergence speed, the binary search tuning algorithm has been proposed. In contrast to the single step method, the tuning speed is improved from O(N) to O(log(N)).

Η πληθώρα των εφαρμογών που μπορεί να εξυπηρετήσει η τεχνολογία Υπερευρείας Ζώνης (UWB), από τα ασύρματα προσωπικά δίκτυα υψηλών ταχυτήτων, μέχρι τα ασύρματα δίκτυα αισθητήρων με δυνατότητες ακριβούς εντοπισμού θέσης, και τα ασύρματα δίκτυα ιατρικών αισθητήρων, έχει προκαλέσει έντονο ερευνητικό ενδιαφέρον γύρω από τις υλοποιήσεις UWB συστημάτων. Η ασυνήθιστα μεγάλη περιοχή συχνοτήτων που έχει ανατεθεί στο UWB, από τα 3.1-10.6 GHz, επιτρέπει την επίτευξη υψηλών ταχυτήτων με απλά σχήματα διαμόρφωσης, ωστόσο, λόγω της διαμοίρασης του φάσματος με τις υφιστάμενες τεχνολογίες ασύρματης δικτύωσης, οι UWB εκπομπές πρέπει να περιορίζονται σε ισχύ κάτω από το κατώφλι των -41.3 dBm/MHz, ικανοποιώντας πολύ αυστηρές μάσκες εκπομπής που εισάγουν έντονες προκλήσεις στη σχεδίαση των πομπών. Η υλοποίηση αναδιατάξιμων UWB πομπών σε σύγχρονες CMOS τεχνολογίες, με υψηλή φασματική ευελιξία, ταχύτητα και ποιότητα διαμόρφωσης, καθώς και με χαμηλή κατανάλωση, αποτέλεσε το αντικείμενο της συγκεκριμένης διατριβής. Υιοθετώντας την αρχιτεκτονική Multi-Band Impulse-Radio (MB-IR) σε συνδυασμό με την τεχνική Direct Sequence BPSK, η έρευνα προσανατολίστηκε προς την ανάπτυξη καινοτόμων μονάδων βασικής ζώνης, με στόχο την ενεργειακά αποδοτική αντιστροφή Γκαουσιανών μορφοποιημένων παλμών υψηλής ποιότητας φάσματος και διάρκειας μικρότερης ακόμα και από 1 nsec. Προς αυτή την κατεύθυνση, αναπτύχθηκε μια καινοτόμα γεννήτρια Γκαουσιανών παλμών με πολύ χαμηλούς πλευρικούς λοβούς στο φάσμα, τυπικά κάτω από -40 dB, ώστε να υποστηρίζονται οι αυστηρότερες μάσκες εκπομπής ή και μελλοντικές. Η σχεδίασης της προτεινόμενης γεννήτριας είχε ως κριτήριο την ευέλικτη ρύθμιση της διάρκειας των παραγόμενων παλμών, και αξιοποίησε τη χαρακτηριστική μεταφοράς τάσης ενός ωμικά φορτωμένου, ασύμμετρου CMOS αντιστροφέα. Η γεννήτρια βασίζεται κυρίως σε ψηφιακά κυκλώματα πολύ χαμηλής τάσης και, σε σύγκριση με τις υφιστάμενες υλοποιήσεις, παρουσιάζει σημαντικό προβάδισμα στον τομέα της ταχύτητας, καθώς και στο πλάτος εξόδου, η μεγάλη τιμή του οποίου χαλαρώνει σημαντικά τη σχεδίαση του RF front end. Η γεννήτρια μελετήθηκε διεξοδικά, διεξήχθη ανάλυση κλιμάκωσης, έγινε εξαγωγή σχεδιαστικών εξισώσεων και αναπτύχθηκαν εργαλεία λογισμικού για την αυτοματοποιημένη σχεδίασή της. Για περαιτέρω αύξηση της ταχύτητας των παλμικών σημάτων εφαρμόσθηκε ειδική σχεδίαση, η οποία αντιπραγματεύεται την ταχύτητα με το επίπεδο των λοβών του φάσματος. Για την αποδοτική BSPK διαμόρφωση των Γκαουσιανών παλμών αναπτύχθηκε ειδική τοπολογία “Μεταγωγής Σήματος Πυροδότησης Πλήρους Ισορροπίας με Up-Conversion”. Η τοπολογία αυτή, σε αντίθεση με τις ανταγωνιστικές τοπολογίες, αποφεύγει την αντιστροφή του παλμού με αναλογικά κυκλώματα υψηλής κατανάλωσης, αλλά και την αναλογική μεταγωγή, καθώς η διαμόρφωση λαμβάνει χώρα πριν από την παραγωγή των παλμών. Παράλληλα, επιτυγχάνονται υψηλοί ρυθμοί, καθώς και υψηλή ποιότητα διαμόρφωσης λόγω των ισορροπημένων μονοπατιών της τοπολογίας. Η γεννήτρια μαζί με το διαμορφωτή αποτελούν τις καινοτόμες παρεμβάσεις στη μονάδα Βασικής Ζώνης του προτεινόμενου πομπού. Για την ολοκλήρωση της λειτουργικότητας του πομπού, αναπτύχθηκε ένα RF front end, το οποίο αποτελείται από έναν διπλά ισορροπημένο μίκτη, έναν LO buffer, ένα μετατροπέα διαφορικού σήματος σε απλό, και έναν ενισχυτή ισχύος, ο οποίος είναι προσαρμοσμένος στα 50 Ohms, χωρίς να απαιτεί κανένα εξωτερικό στοιχείο. Το RF front end ολοκληρώθηκε μαζί με τη μονάδα βασικής ζώνης, και ο ολοκληρωμένος πομπός κατασκευάστηκε σε τεχνολογία CMOS 130 nm. Το ολοκληρωμένο προσαρτήθηκε στην RF πλακέτα συστήματος με την τεχνική Chip on Board. Για την επιτυχία του συστήματος με την πρώτη προσπάθεια έγινε συσχεδίαση σε επίπεδο IC-Package-PCB, δίνοντας ιδιαίτερη έμφαση στα ζητήματα Signal/Power Integrity. Ο πομπός παρουσίασε την υψηλότερη ταχύτητα από τις ανταγωνιστικές MB-IR UWB υλοποιήσεις, ίση με 1.5 Gbps, με αντίστοιχη ενεργειακή αποδοτικότητα 21 pJoule/bit και μέτρο διανυσματικού σφάλματος 5.5%. Ο πομπός βελτίωσε τους πλευρικούς λοβούς στο φάσμα περισσότερο από 10 dB, ενώ η διατριβή, εκμεταλλευόμενη την αναδιαταξιμότητα του πομπού, παρουσιάζει, επιπλέον, τις πρώτες μετρήσεις σε ταχύτητες εκατοντάδων Mbps για ικανοποίηση της χαμηλής ζώνης της πρόσφατα θεσμοθετημένης, και εξαιρετικά αυστηρής, ευρωπαϊκής μάσκας εκπομπής.<br>The multitude of applications that Ultra-Wideband (UWB) technology can serve, from high-speed Wireless Personal Area Networks, to Wireless Sensor Networks with precision Geolocation abilities, and Wireless Medical Networks, has attracted intense research interest in the implementation of UWB systems. The unusually wide range of frequencies assigned to UWB, from 3.1-10.6 GHz, allows UWB systems employing low order modulation schemes to enjoy high throughput at low power consumption. However, since UWB shares the spectrum with existing wireless networking technologies, UWB emissions must be limited to a power spectral density below the threshold of -41.3 dBm/MHz, satisfying very stringent emission masks and introducing great challenges in the design of UWB transmitters. The subject of this thesis is the design of low power, fully integrated, reconfigurable CMOS UWB transmitters, with high spectral flexibility, high speed and high modulation quality. Adopting the Multi-Band Impulse-Radio architecture, in conjunction with the Direct Sequence BPSK modulation, the research focused on the development of a baseband unit, able to precisely invert Gaussian shaped, subnanosecond pulses. The key contributions of this thesis are a CMOS Gaussian Pulse Generator and a BSPK modulation topology, which jointly constitute the proposed baseband unit. The Pulse Generator (PG) is based on non-linear shaping, so as to facilitate the configurability of the output pulse duration, and exploits the voltage transfer characteristic of a Resistive Loaded Asymmetrical CMOS Inverter, which results in spectral sidelobes typically better than -40 dB. The PG incorporates mostly-digital low voltage circuits, while the MOSFET devices that undertake the pulse shaping avoid exclusive operation in weak inversion, in contrast to previous implementations. Consequently, the proposed CMOS PG is able to support higher throughput, as well as higher output amplitude, which relaxes considerably the design of the RF front end. This thesis presents a systematic design procedure and a scaling analysis of the non-linear pulse shaper. Moreover, in order to further increase the speed, a special PRF boost technique is proposed, which trades off speed and spectral efficiency for the spectral sidelobes level. Regarding the BPSK modulator, this work introduces the “Trigger Switching Fully Balanced Up-Conversion” topology, which avoids the use of power-hungry and distortion-prone analog circuits for the accurate inversion of the subnanosecond shaped pulses, as well as avoids the application of analog waveform switching to the baseband pulses, since the baseband modulation takes place before the generation of the pulses. The digital nature of the switching lends itself to high data rates, while the balanced paths of the topology ensure high modulation quality with minimal design effort. Wafer probing measurements confirmed the high performance of the baseband unit. The functionality of the transmitter was completed by the development of an RF front end which consists of a double balanced mixer, an LO buffer, a differential to single-ended (DtoSE) converter, and a power amplifier which is ready to drive a 50 Ohms load without requiring any off-chip components. The integrated transmitter, which incorporates the proposed baseband unit and the RF front end, was fabricated in 130 nm CMOS technology. The transmitter RFIC was directly attached to the system RF PCB using the Chip-on-Board packaging option. The First-Pass success of the system was ensured by paying particular attention to Signal/Power Integrity issues and following an IC-Package-PCB co-design procedure. The transmitter was measured up to 1.5 Gbps, which, to the author’s knowledge, was the highest speed amongst the competitive Multi-Band Impulse-Radio UWB implementations in the literature. The corresponding energy efficiency was 21 pJoule/bit and the Error Vector Magnitude (EVM) 5.5%, while the proposed transmitter improved the spectral sidelobes by over 10 dB. Exploiting the reconfigurability of the transmitter, this thesis presents the first measurements at multi-Mbps speeds that completely meet the final version of the European spectrum emission mask.