Relevant bibliographies by topics / RF power transistor

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'RF power transistor'

Author: Grafiati
Published: 4 June 2021
Last updated: 18 February 2022

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Journal articles on the topic "RF power transistor"

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Sleptsova, Anastasia A., Sergey V. Chernykh, Dmitry A. Podgorny, and Ilya A. Zhilnikov. "Optimization of passivation in AlGaN/GaN heterostructure microwave transistor fabrication by ICP CVD." Modern Electronic Materials 6, no. 2 (July 15, 2020): 71–75. http://dx.doi.org/10.3897/j.moem.6.2.58860.

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We have studied the effect of silicon nitride (SiN) dielectric passivating film deposition by inductively coupled plasma chemical vapor deposition (ICP CVD) on the parameters of AlGaN/GaN heterostructure high electron mobility transistors (HEMT). Study of the parameters of the dielectric layers has allowed us to determine the effect of RF and ICP power and working gas flow ratio on film growth rate and structural perfection, and on the current vs voltage curves of the passivated HEMT. The deposition rate changes but slightly with an increase in RF power but increases with an increase in ICP power. Transistor slope declines considerably with an increase in RF power: it is the greatest at minimum power RF = 1 W. In the beginning of growth even at a low RF power (3 W) the transistor structure becomes completely inoperable. Dielectric deposition for HEMT passivation should be started at minimum RF power. We have developed an AlGaN/GaN microwave HEMT passivation process providing for conformal films and low closed transistor drain–source currents without compromise in open state transistor performance: within 15 and 100 mA, respectively, for a 1.25 and 5 mm common T-gate (Ug = –8 V and Ud-s = 50 V).
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Timoshenkov, V. P., A. I. Khlybov, D. V. Rodionov, and A. I. Panteleev. "Research of Influence of Power RF GaN Transistor Constructions on it's Thermal Mode." Nano- i Mikrosistemnaya Tehnika 22, no. 8 (October 23, 2020): 415–21. http://dx.doi.org/10.17587/nmst.22.415-421.

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This paper shows influence of power RF GaN transistors construction on it's thermal mode. Field GaN transistor (with field plate) was researched. The influence of field-plate on transistor thermal mode was analysed and compared to other constructions.
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Khlybov, A. I., D. V. Rodionov, A. I. Panteleev, P. V. Timoshenkov, and N. V. Guminov. "Simulation of Power RF GaN Transistors Thermal Parameters in Pulse Mode." Nano- i Mikrosistemnaya Tehnika 23, no. 4 (August 20, 2021): 179–85. http://dx.doi.org/10.17587/nmst.23.179-185.

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This paper contains research results of thermal process in power GaN RF transistor in silicon substrate for pulse mode. Thermal mode research was done using computer simulation. Authors developed methodic allows significant decrease computational complexity. The dependences of maximum transistor channel temperature and thermal resistance as function of pulse width (with constant duty cycle) were done. Thermal simulation was done for power GaN RF transistor with overall gate width 2.1 mm.
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Morad, E., S. Z. Moussavi, M. Alasvandi, and E. Rasouli. "A Low Voltage, Low Power and Highly Linear CMOS Down-Conversion Gilbert Cell Mixer Using MGTR Method." Journal of Circuits, Systems and Computers 24, no. 07 (June 17, 2015): 1550098. http://dx.doi.org/10.1142/s021812661550098x.

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A radio frequency (RF) low voltage and low power down conversion mixer with high linearity using TSMC 0.18-μm technology is presented which operates in 2.4 GHz Industrial Scientific and Medical (ISM) band. The local oscillator (LO) frequency is 2.1 GHz with an input power of 5 dBm, whereas IF frequency is 300 MHz. Multiple gated transistors (MGTRs) method is used to increase the linearity of Gilbert cell mixer. In this method an auxiliary transistor is used parallel to the transconductance stage transistor. This increases linearity by decreasing of transconductance stage transistor. The simulation results show an IIP3 improvement of 16.55 dBm. The proposed low power and highly linear mixer consumes a power of 4.46 mW from 1.8 V a supply voltage. The noise figure (NF) and gain conversion are about 13.8 dB and 9.11 dB, respectively.
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Moraes Junior, Tarcisio Oliveira, Raimundo Carlos Silvério Freire, and Cleonilson Protásio de Souza. "A High-Efficiency CMOS Rectifier for RF Using Bulk Biasing Control Circuit." Journal of Integrated Circuits and Systems 13, no. 2 (October 4, 2018): 1–6. http://dx.doi.org/10.29292/jics.v13i2.35.

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In MOSFET-transistor based rectifier circuits, leakage currents occur through both source-bulk and drain-bulk connections of their transistors causing some power dissipation decreasing their efficiency. Such a scenario is more worrying in ultra-low power circuits as those used in energy harvesting. As a solution, in this work it is proposed a control circuit of transistor bulk biasing that switches the bulk bias in an efficient way assuring adequate inversion of the source-bulk and drain-bulk junctions. The rectifier based on the proposed bulk biasing control circuit shows to be a high-efficiency one capable of reducing the leakage currents. To obtain experimental results, the circuit was fabricated in a 130 nm CMOS process and tested on a micromanipulator. The results were compared with other works where it is observed that the efficiency of our proposal reaches up to 72.5% or 5% higher that the best previous one.
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Konstantinov, Andrey O., Chris I. Harris, and I. C. Ray. "High Power Lateral Epitaxy MESFET Technology in Silicon Carbide." Materials Science Forum 483-485 (May 2005): 853–56. http://dx.doi.org/10.4028/www.scientific.net/msf.483-485.853.

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High impedance silicon carbide power RF transistors are reported, which use the technology of Lateral Epitaxy Metal-Semiconductor FET (LEMES). The LEMES transistor utilizes a heavily doped buried depletion stopper to increase output impedance and breakdown voltage and to eliminate undesirable hot-carrier trapping effects. A power density of 2-3 W/mm at 2 GHz is routinely achieved resulting in a total output power of 10W for packaged components. The value of input and output impedance is around 50 Ohms for a frequency of around 2 GHz.
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Cheng, Yu Jie, Jian Hua Xu, and Hai Feng Cheng. "Research on VRM in RF PA System Based on Enhancement Mode GaN HEMT." Materials Science Forum 1014 (November 2020): 149–56. http://dx.doi.org/10.4028/www.scientific.net/msf.1014.149.

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As a key part of the RF PA system, VRM (Voltage-Regulate-Modulator), whose main role is to offer pulse voltage for RF power transistor, is often slighted. As a result, VRM has been a restraining factor now. In order to realize the needs of high speed and high frequency, a new method based on enhancement mode GaN HEMT of designing VRM is proposed in this paper. By using this method, the rise time and fall time of VRM could be as about 10ns with the peak voltage 75V and the peak current 150A, which is quite suitable for driving high voltage and high power GaN-based RF power transistor.
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RAJAN, SIDDHARTH, UMESH K. MISHRA, and TOMÁS PALACIOS. "AlGaN/GaN HEMTs: RECENT DEVELOPMENTS AND FUTURE DIRECTIONS." International Journal of High Speed Electronics and Systems 18, no. 04 (December 2008): 913–22. http://dx.doi.org/10.1142/s0129156408005874.

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This paper provides an overview of recent work and future directions in Gallium Nitride transistor research. We discuss the present status of Ga -polar AlGaN / GaN HEMTs and the innovations that have led to record RF power performance. We describe the development of N -polar AlGaN / GaN HEMTs with microwave power performance comparable with state-of-art Ga -polar AlGaN / GaN HEMTs. Finally we will discuss how GaN -based field effect transistors could be promising for a less obvious application: low-power high-speed digital circuits.
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Jardel, Olivier, Jean-Claude Jacquet, Lény Baczkowski, Dominique Carisetti, Didier Lancereau, Maxime Olivier, Raphaël Aubry, et al. "InAlN/GaN HEMTs based L-band high-power packaged amplifiers." International Journal of Microwave and Wireless Technologies 6, no. 6 (February 25, 2014): 565–72. http://dx.doi.org/10.1017/s175907871400004x.

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This paper presents power results of L-band packaged hybrid amplifiers using InAlN/GaN/SiC HEMT power dies. The high-power densities achieved both in pulsed and continuous wave (cw) modes confirm the interest of such technology for high-frequency, high-power, and high-temperature operation. We present here record RF power measurements for different versions of amplifiers. Up to 260 W, i.e. 3.6 W/mm, in pulsed (10 µs/10%) conditions, and 105 W, i.e. 2.9 W/mm, in cw conditions were achieved. Such results are made possible thanks to the impressive performances of InAlN/GaN transistors, even when operating at high temperatures. Unit cell transistors deliver output powers of 4.3 W/mm at Vds = 40 V in the cw mode of operation at the frequency of 2 GHz. The transistor process is described here, as well as the amplifiers design and measurements, with a particular focus to the thermal management aspects.
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Drillet, Frédéric, Jérôme Loraine, Hassan Saleh, Imene Lahbib, Brice Grandchamp, Lucas Iogna-Prat, Insaf Lahbib, Ousmane Sow, Albert Kumar, and Gregory U'Ren. "RF Small and large signal characterization of a 3D integrated GaN/RF-SOI SPST switch." International Journal of Microwave and Wireless Technologies 13, no. 6 (February 24, 2021): 517–22. http://dx.doi.org/10.1017/s1759078721000076.

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AbstractThis paper presents the radio frequency (RF) measurements of an SPST switch realized in gallium nitride (GaN)/RF-SOI technology compared to its GaN/silicon (Si) equivalent. The samples are built with an innovative 3D heterogeneous integration technique. The RF switch transistors are GaN-based and the substrate is RF-SOI. The insertion loss obtained is below 0.4 dB up to 30 GHz while being 1 dB lower than its GaN/Si equivalent. This difference comes from the vertical capacitive coupling reduction of the transistor to the substrate. This reduction is estimated to 59% based on a RC network model fitted to S-parameters measurements. In large signal, the linearity study of the substrate through coplanar waveguide transmission line characterization shows the reduction of the average power level of H2 and H3 of 30 dB up to 38 dBm of input power. The large signal characterization of the SPST shows no compression up to 38 dBm and the H2 and H3 rejection levels at 38 dBm are respectively, 68 and 75 dBc.
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Dissertations / Theses on the topic "RF power transistor"

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Ankarcrona, Johan. "High Frequency Analysis of Silicon RF MOS Transistors." Doctoral thesis, Uppsala : Acta Universitatis Upsaliensis : Universitetsbiblioteket [distributör], 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-5909.

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Syed, Asad Abbas. "Large Signal Physical Simulations of Si LD-MOS transistor for RF application." Thesis, Linköping University, The Department of Physics, Chemistry and Biology, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2627.

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The development of computer aided design tools for devices and circuits has increased the interest for accurate transistor modeling in microwave applications. In the increasingly expanding wireless communication market, there is a huge demand for high performance RF power devices. The silicon LD- MOSFET transistor is dueto its high power performance is today widely used in systems such as mobile base stations, private branch exchanges (PBX), and local area networks (LAN) utilizing the bands between 0.9 to 2.5 GHz.

In this research we simulated LD-MOSFET transistor characteristics of the structure provided by Infineon technology at Kista, Stockholm. The maximum drain current obtained in the simulation was 400 mA at a gate voltage of 8 V. This value is somewhat higher than the measured one. This difference can be attributed to the parasitic effects since no parasitic effects were included in the simulations in the beginning. The only parasitic effect studied was by placing the source contact at the bottom of the substrate according to real commercial device. The matching between simulated and measured results were improved and maximum drain current was reduced to 300 mA/mm which was 30% higher than the measured drain current

The large signal RF simulations were performed in time-domain in our novel technique developed at LiU. This technique utilizes a very simple amplifier circuit without any passive components. Only DC bias and RF signals are applied to the gate and drain terminals, with the same fundamental frequency but with 180o phase difference. The RF signal at the drain acting as a short at higher harmonics. These signals thus also acted as an active match to the transistor. Large signal RF simulations were performed at 1, 2 and 3 GHz respectively. The maximum of drain current signal was observed at the maximum of drain voltage signal indicating the normal behavior of the transistor. At 1 GHz the output power was 1.25 W/mm with 63% of drain efficiency and 23.7 dB of gain. The out pout power was decreased to 1.15 W/mm and 1.1 W/mm at 2 and 3 GHz respectively at the same time the efficiency and gain was also decreased to 57% and 19 dB at 2 GHz and 51% and 15 dB at 3GHz respectively.

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Kashif, Ahsan-Ullah. "Optimization of LDMOS Transistor in Power Amplifiers for Communication Systems." Doctoral thesis, Linköpings universitet, Halvledarmaterial, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-61599.

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The emergence of new communication standards has put a key challenge for semiconductor industry to develop RF devices that can handle high power and high data rates simultaneously. The RF devices play a key role in the design of power amplifiers (PAs), which is considered as a heart of base-station. From economical point of view, a single wideband RF power module is more desirable rather than multiple narrowband PAs especially for multi-band and multi-mode operation. Therefore, device modeling has now become much more crucial for such applications. In order to reduce the device design cycle time, the researchers also heavily rely on computer aided design (CAD) tools. With improvement in CAD technology the model extraction has become more accurate and device physical structure optimization can be carried out with less number of iterations. LDMOS devices have been dominating in the communication field since last decade and are still widely used for PA design and development. This thesis deals with the optimization of RFLDMOS transistor and its evaluation in different PA classes, such as linear, switching, wideband and multi-band applications. For accurate evaluation of RF-LDMOS transistor parameters, some techniques are also developed in technology CAD (TCAD) using large signal time domain computational load-pull (CLP) methods. Initially the RF-LDMOS is studied in TCAD for the improved RF performance. The physical intrinsic structure of RF-LDMOS is provided by Infenion Technologies AG. A reduced surface field (RESURF) of low-doped drain (LDD) region is considered in detail because it plays an important role in RF-LDMOS devices to obtain high breakdown voltage (BVDS). But on the other hand, it also reduces the RF performance due to high on-resistance (Ron). The excess interface state charges at the RESURF region are introduced to reduce the Ron, which not only increases the dc drain current, but also improve the RF performance in terms of power, gain and efficiency. The important achievement is the enhancement in operating frequency up to 4 GHz. In LDD region, the effect of excess interface charges at the RESURF is also compared with dual implanted-layer of p-type and n-type. The comparison revealed that the former provides 43 % reduction in Ron with BVDS of 70 V, while the later provides 26 % reduction in Ron together with BVDS of 64 - 68 V. In the second part of my research work, computational load pull (CLP) simulation technique is used in TCAD to extract the impedances of RF-LDMOS at different frequencies under large signal operation. Flexible matching is an issue in the design of broadband or multi-band PAs. Optimum impedance of RF-LDMOS is extracted at operating frequencies of 1, 2 and 2.5 GHz in class AB PA. After this, CLP simulation technique is further developed in TCAD to study the non-linear behavior of RF devices. Through modified CLP technique, non-linear effects inside the transistor structure are studied by conventional two-tone RF signals in time domain. This is helpful to detect and understand the phenomena, which can be resolved to improve the device performance. The third order inter-modulation distortion (IMD3) of RF- LDMOS was observed at different power levels. The IMD3 of −22 dBc is obtained at 1-dB compression point (P1-dB), while at 10 dB back off the value increases to −36 dBc. These results were also verified experimentally by fabricating a linear PA. Similarly, CLP technique is developed further for the analysis of RF devices in high efficiency operation by investigating the odd harmonic effects for the design of class-F PA. RF-LDMOS can provide a power added efficiency (PAE) of 81.2 % in class-F PA at 1 GHz in TCAD simulations. The results are verified by design and fabrication of class-F PA using large signal model of the similar device in ADS. In fabrication, a PAE of 76 % is achieved.
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Srirattana, Nuttapong. "High-Efficiency Linear RF Power Amplifiers Development." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6899.

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Next generation mobile communication systems require the use of linear RF power amplifier for higher data transmission rates. However, linear RF power amplifiers are inherently inefficient and usually require additional circuits or further system adjustments for better efficiency. This dissertation focuses on the development of new efficiency enhancement schemes for linear RF power amplifiers. The multistage Doherty amplifier technique is proposed to improve the performance of linear RF power amplifiers operated in a low power level. This technique advances the original Doherty amplifier scheme by improving the efficiency at much lower power level. The proposed technique is supported by a new approach in device periphery calculation to reduce AM/AM distortion and a further improvement of linearity by the bias adaptation concept. The device periphery adjustment technique for efficiency enhancement of power amplifier integrated circuits is also proposed in this work. The concept is clearly explained together with its implementation on CMOS and SiGe RF power amplifier designs. Furthermore, linearity improvement technique using the cancellation of nonlinear terms is proposed for the CMOS power amplifier in combination with the efficiency enhancement technique. In addition to the efficiency enhancement of power amplifiers, a scalable large-signal MOSFET model using the modified BSIM3v3 approach is proposed. A new scalable substrate network model is developed to enhance the accuracy of the BSIM3v3 model in RF and microwave applications. The proposed model simplifies the modeling of substrate coupling effects in MOS transistor and provides great accuracy in both small-signal and large-signal performances.
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Heo, Deukhyoun. "Silicon MOS field effect transistor RF/Microwave nonlinear model study and power amplifier development for wireless communications." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/15618.

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Sun, Wenyuan. "Impact of As-grown and Radiation-induced Traps on GaN RF and Power Transistor Performance and Reliability." The Ohio State University, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1586989454689707.

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Willemann, Michael Howard. "Polymer-Supported Bridges for Multi-Finger AlGaN/GaN Heterojunction Field Effect Transistors (HFETs)." Thesis, Virginia Tech, 2007. http://hdl.handle.net/10919/34801.

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Current AlGaN/GaN Heterojunction Field Effect Transistors (HFETs) make use of multiple sources, drains, and gates in parallel to maximize transconductance and effective gain while minimizing the current density through each channel. To connect the sources to a common ground, current practice prescribes the fabrication of air bridges above the gates and drains. This practice has the advantage of a low dielectric constant and low parasitic capacitance, but it is at the expense of manufacturability and robust device operation. In the study described below, the air bridges in AlGaN/GaN HFETs were replaced by a polymer supported metallization bridge with the intention of improving ease of fabrication and reliability. The DC, high frequency, and power performance for several polymer step heights were investigated. The resultant structures were functional and robust; however, their electrical performance was degraded due to high source resistance. The cause of the high source resistance was found to be thinning of the metallization at the polymer step. The effect was more pronounced for higher step heights.
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Connor, Mark Anthony. "Design of Power-Scalable Gallium Nitride Class E Power Amplifiers." University of Dayton / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1405437893.

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Banerjee, Aritra. "Design of digitally assisted adaptive analog and RF circuits and systems." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/52919.

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With more and more integration of analog and RF circuits in scaled CMOS technologies, process variation is playing a critical role which makes it difficult to achieve all the performance specifications across all the process corners. Moreover, at scaled technology nodes, due to lower voltage and current handling capabilities of the devices, they suffer from reliability issues that reduce the overall lifetime of the system. Finally, traditional static style of designing analog and RF circuits does not result in optimal performance of the system. A new design paradigm is emerging toward digitally assisted analog and RF circuits and systems aiming to leverage digital correction and calibration techniques to detect and compensate for the manufacturing imperfections and improve the analog and RF performance offering a high level of integration. The objective of the proposed research is to design digital friendly and performance tunable adaptive analog/RF circuits and systems with digital enhancement techniques for higher performance, better process variation tolerance, and more reliable operation and developing strategy for testing the proposed adaptive systems. An adaptation framework is developed for process variation tolerant RF systems which has two parts – optimized test stimulus driven diagnosis of individual modules and power optimal system level tuning. Another direct tuning approach is developed and demonstrated on a carbon nanotube based analog circuit. An adaptive switched mode power amplifier is designed which is more digital-intensive in nature and has higher efficiency, improved reliability and better process resiliency. Finally, a testing strategy for adaptive RF systems is shown which reduces test time and test cost compared to traditional testing.
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Rennesson, Stéphanie. "Développement de nouvelles hétérostructures HEMTs à base de nitrure de gallium pour des applications de puissance en gamme d'ondes millimétriques." Phd thesis, Université Nice Sophia Antipolis, 2013. http://tel.archives-ouvertes.fr/tel-00943619.

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Les matériaux III-N sont présents dans la vie quotidienne pour des applications optoélectroniques (diodes électroluminescentes, lasers). Les propriétés remarquables du GaN (grand gap, grand champ de claquage, champ de polarisation élevé, vitesse de saturation des électrons importante...) en font un candidat de choix pour des applications en électronique de puissance à basse fréquence, mais aussi à haute fréquence, par exemple en gamme d'ondes millimétriques. L'enjeu de ce travail de thèse consiste à augmenter la fréquence de travail des transistors tout en maintenant une puissance élevée. Pour cela, des hétérostructures HEMTs (High Electron Mobility Transistors) sont développées et les épaisseurs de cap et de barrière doivent être réduites, bien que ceci soit au détriment de la puissance délivrée. Une étude sera donc menée sur l'influence des épaisseurs de cap et de barrière ainsi que le type de barrière (AlGaN, AlN et InAlN) de manière à isoler les hétérostructures offrant le meilleur compromis en termes de fréquence et de puissance. De plus, les moyens mis en œuvre pour augmenter la fréquence de travail entrainent une dégradation du confinement des électrons du canal. De manière à limiter cet effet, une back-barrière est insérée sous le canal. Ceci fera l'objet d'une deuxième étude. Enfin, une étude de la passivation de surface des transistors sera menée. La combinaison des ces trois études permettra d'identifier la structure optimale pour délivrer le plus de puissance à haute fréquence (ici à 40 GHz).
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Books on the topic "RF power transistor"

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Corporation, Toshiba. RF power transistor and module: Data book. Tokyo: Toshiba Corporation, 1993.

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Charge-based MOS transistor modelling: The EKV model for low-power and RF IC design. Chichester, UK: John Wiley & Sons, 2006.

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Semiconductors, Philips. RF power bipolar transistors: Data handbook. Eindhoven: Philips Semiconductors, 1993.

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Semiconductors, Philips. RF power MOS transistors: Data handbook. Eindhoven: Philips Semiconductors, 1993.

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Baliga, Jayant. Silicon RF power MOSFETs. Singapore: World Scientific, 2005.

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Silicon RF power MOSFETS. Singapore: World Scientific, 2005.

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Enz, Christian, and Eric Vittoz. Charge-based Mos Transistor Modeling: The Ekv Model for Low-power And Rf Ic Design. John Wiley & Sons Inc, 2006.

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Enz, Christian C., and Eric A. Vittoz. Charge-Based MOS Transistor Modeling: The EKV Model for Low-Power and RF IC Design. Wiley & Sons, Incorporated, John, 2006.

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Enz, Christian C., and Eric A. Vittoz. Charge-Based MOS Transistor Modeling: The EKV Model for Low-Power and RF IC Design. Wiley, 2006.

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Modeling and Characterization of RF and Microwave Power FETs (The Cambridge RF and Microwave Engineering Series). Cambridge University Press, 2007.

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Book chapters on the topic "RF power transistor"

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"Transistor Modeling and Simulation." In Introduction to RF Power Amplifier Design and Simulation, 93–196. CRC Press, 2015. http://dx.doi.org/10.1201/b18677-4.

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Eroglu, Abdullah. "Transistor Modeling and Simulation." In Introduction to RF Power Amplifier Design and Simulation, 93–195. CRC Press, 2018. http://dx.doi.org/10.1201/9781315215297-3.

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Shim, Dongha, Eunyoung Seok, Daniel J. Arenas, Dimitrios Koukis, David B. Tanner, and K. O. Kenneth. "THz power generation beyond transistor fmax." In RF and mm-Wave Power Generation in Silicon, 461–84. Elsevier, 2016. http://dx.doi.org/10.1016/b978-0-12-408052-2.00017-7.

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Fiorelli, Rafaella, Eduardo Peralías, and Fernando Silveira. "An All-Inversion-Region gm/ID Based Design Methodology for Radiofrequency Blocks in CMOS Nanometer Technologies." In Advances in Wireless Technologies and Telecommunication, 15–39. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-4666-0083-6.ch002.

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This chapter presents a design optimization methodology for analog radiofrequency (RF) blocks based on the gm/ID technique and on the exploration of all-inversion regions (from weak inversion or sub-threshold to strong inversion or above threshold) of the MOS transistor in nanometer technologies. The use of semi-empirical models of MOS transistors and passive components, as inductors or capacitors, assures accurate designs, reducing time and efforts for transferring the initial block specifications to a compliant design. This methodology permits the generation of graphical maps to visualize the evolution of the circuit characteristics when sweeping both the inversion zone and the bias current, allowing reaching very good compromises between performance aspects of the circuit (e.g. noise and power consumption) for a set of initial specifications. In order to demonstrate the effectiveness of this methodology, it is applied in the design of two basic blocks of RF transceivers: low noise amplifiers (LNAs) and voltage controlled oscillators (VCOs), implemented in two different nanometer technologies and specified to be part of a 2.4 GHz transceiver. A possible design flow of each block is provided; resulting designs are implemented and verified both with simulations and measurements.
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Ferreira, Pietro M., Hao Cai, and Lirida Naviner. "Reliability Aware AMS/RF Performance Optimization." In Advances in Computer and Electrical Engineering, 28–54. IGI Global, 2015. http://dx.doi.org/10.4018/978-1-4666-6627-6.ch002.

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Reliability has become an important issue in the continuously CMOS technology scaling down. The exploration of the technology limits using classic performance optimization techniques and leads to the best trade-off for the area, power consumption, and speed. Nevertheless, such key characteristics have been degraded in a context of continuous use and stressful environment. Thus, circuit reliability emerges as a design criterion for AMS/RF performance optimization. Aiming a design for reliability, this chapter presents an overview of CMOS unreliable phenomena. Reliability-aware methodologies for circuit design, simulation, and optimization are reviewed. The authors focus in particular on large and complex systems, providing circuit design insights to achieve a reliability specification from system-level to transistor-level. They highlight the more sensitive building blocks in CT S? modulator and demonstrate how performance is affected by unreliable phenomena. A system-level direct-conversion RF front-end design is described in top-down approach. Electrical simulations are presented with 65 nm CMOS technology.
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"RF Performance." In GaN Transistors for Efficient Power Conversion, 201–22. Chichester, UK: John Wiley & Sons, Ltd, 2019. http://dx.doi.org/10.1002/9781119594406.ch9.

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"RF Performance." In GaN Transistors for Efficient Power Conversion, 150–71. Chichester, UK: John Wiley & Sons, Ltd, 2014. http://dx.doi.org/10.1002/9781118844779.ch08.

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"RF Performance." In GaN Transistors for Efficient Power Conversion, 150–71. Chichester, UK: John Wiley & Sons, Ltd, 2014. http://dx.doi.org/10.1002/9781118844779.ch8.

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Perugupalli, Prasanth, Larry Leighton, Jan Johansson, and Qiang Chen. "LDMOS RF Power Transistors and Their Applications." In Radio Frequency Transistors, 259–92. Elsevier, 2001. http://dx.doi.org/10.1016/b978-075067281-8/50032-1.

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"Radio Frequency Power Transistors." In Introduction to RF Power Amplifier Design and Simulation, 61–92. CRC Press, 2015. http://dx.doi.org/10.1201/b18677-3.

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Conference papers on the topic "RF power transistor"

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Kashif, A., C. Svensson, and Q. Wahab. "High Power LDMOS Transistor for RF-Amplifiers." In 2007 International Bhurban Conference on Applied Sciences & Technology. IEEE, 2007. http://dx.doi.org/10.1109/ibcast.2007.4379896.

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Cai, W. Z., B. Gogoi, R. Davies, D. Lutz, D. Rice, G. H. Loechelt, and G. Grivna. "TCAD Analysis of a Vertical RF Power Transistor." In 2009 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD). IEEE, 2009. http://dx.doi.org/10.1109/sispad.2009.5290204.

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Voinigescu, S. P., S. Shopov, A. Balteanu, and I. Sarkas. "Mm-wave power-DAC transmitters with transistor and antenna segmentation." In 2014 IEEE International Microwave and RF Conference (IMaRC). IEEE, 2014. http://dx.doi.org/10.1109/imarc.2014.7038969.

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Mahmoudi, R., M. de Kok, K. Mouthaan, and J. L. Tauritz. "On the Deembedding of RF High Power Transistor Parameters." In 48th ARFTG Conference Digest. IEEE, 1996. http://dx.doi.org/10.1109/arftg.1996.327193.

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Song, Liang, and Yaohui Zhang. "Internal matching circuit design of RF LDMOS power transistor." In 2016 International Conference on Integrated Circuits and Microsystems (ICICM). IEEE, 2016. http://dx.doi.org/10.1109/icam.2016.7813554.

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"Workshops WS2: RF Power Transistor and Amplifier Characterization Techniques." In 2007 IEEE Radio and Wireless Symposium. IEEE, 2007. http://dx.doi.org/10.1109/rws.2007.351768.

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Hashizume, Tamotsu, Ryota Ochi, Erika Maeda, Toshihide Nabatame, Koji Shiozaki, and Taketomo Sato. "HfSiOx-gate GaN MOS-HEMTs for RF power transistor." In Gallium Nitride Materials and Devices XVI, edited by Hadis Morkoç, Hiroshi Fujioka, and Ulrich T. Schwarz. SPIE, 2021. http://dx.doi.org/10.1117/12.2577403.

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Hou, Fucheng, and Yaohui Zhang. "RF LDMOS power transistor for multi-carrier GSM base station." In 2014 IEEE International Wireless Symposium (IWS). IEEE, 2014. http://dx.doi.org/10.1109/ieee-iws.2014.6864254.

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Dutta, Sayantika, and Subir Kumar Maity. "Temperature dependent analog/RF performance of double gate MOS transistor." In 2016 International conference on Signal Processing, Communication, Power and Embedded System (SCOPES). IEEE, 2016. http://dx.doi.org/10.1109/scopes.2016.7955558.

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Nenadovic, N., W. Cuoco, M. P. van de Heijden, L. K. Nanver, J. W. Slotboom, S. J. Theeuwen, and H. F. Jos. "High-performance Silicon-On-Glass VDMOS Transistor for RF-Power Applications." In 32nd European Solid-State Device Research Conference. IEEE, 2002. http://dx.doi.org/10.1109/essderc.2002.194948.

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Reports on the topic "RF power transistor"

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Shah, Pankaj B., and Joe X. Qiu. Physics Based Analysis of Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) for Radio Frequency (RF) Power and Gain Optimization. Fort Belvoir, VA: Defense Technical Information Center, December 2011. http://dx.doi.org/10.21236/ada554911.

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Motayed, Abhishek, Baomei Wen, and Ratan Debnath. Two-Dimensional MoS2 Transistors for Low- Power RF Applications. Fort Belvoir, VA: Defense Technical Information Center, February 2015. http://dx.doi.org/10.21236/ada628472.

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