Dissertations / Theses: 'RF power transistor'

1

Ankarcrona, Johan. "High Frequency Analysis of Silicon RF MOS Transistors." Doctoral thesis, Uppsala : Acta Universitatis Upsaliensis : Universitetsbiblioteket [distributör], 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-5909.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Syed, Asad Abbas. "Large Signal Physical Simulations of Si LD-MOS transistor for RF application." Thesis, Linköping University, The Department of Physics, Chemistry and Biology, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2627.

Full text

Abstract:

The development of computer aided design tools for devices and circuits has increased the interest for accurate transistor modeling in microwave applications. In the increasingly expanding wireless communication market, there is a huge demand for high performance RF power devices. The silicon LD- MOSFET transistor is dueto its high power performance is today widely used in systems such as mobile base stations, private branch exchanges (PBX), and local area networks (LAN) utilizing the bands between 0.9 to 2.5 GHz.

In this research we simulated LD-MOSFET transistor characteristics of the structure provided by Infineon technology at Kista, Stockholm. The maximum drain current obtained in the simulation was 400 mA at a gate voltage of 8 V. This value is somewhat higher than the measured one. This difference can be attributed to the parasitic effects since no parasitic effects were included in the simulations in the beginning. The only parasitic effect studied was by placing the source contact at the bottom of the substrate according to real commercial device. The matching between simulated and measured results were improved and maximum drain current was reduced to 300 mA/mm which was 30% higher than the measured drain current

The large signal RF simulations were performed in time-domain in our novel technique developed at LiU. This technique utilizes a very simple amplifier circuit without any passive components. Only DC bias and RF signals are applied to the gate and drain terminals, with the same fundamental frequency but with 180o phase difference. The RF signal at the drain acting as a short at higher harmonics. These signals thus also acted as an active match to the transistor. Large signal RF simulations were performed at 1, 2 and 3 GHz respectively. The maximum of drain current signal was observed at the maximum of drain voltage signal indicating the normal behavior of the transistor. At 1 GHz the output power was 1.25 W/mm with 63% of drain efficiency and 23.7 dB of gain. The out pout power was decreased to 1.15 W/mm and 1.1 W/mm at 2 and 3 GHz respectively at the same time the efficiency and gain was also decreased to 57% and 19 dB at 2 GHz and 51% and 15 dB at 3GHz respectively.

APA, Harvard, Vancouver, ISO, and other styles

3

Kashif, Ahsan-Ullah. "Optimization of LDMOS Transistor in Power Amplifiers for Communication Systems." Doctoral thesis, Linköpings universitet, Halvledarmaterial, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-61599.

Full text

Abstract:

The emergence of new communication standards has put a key challenge for semiconductor industry to develop RF devices that can handle high power and high data rates simultaneously. The RF devices play a key role in the design of power amplifiers (PAs), which is considered as a heart of base-station. From economical point of view, a single wideband RF power module is more desirable rather than multiple narrowband PAs especially for multi-band and multi-mode operation. Therefore, device modeling has now become much more crucial for such applications. In order to reduce the device design cycle time, the researchers also heavily rely on computer aided design (CAD) tools. With improvement in CAD technology the model extraction has become more accurate and device physical structure optimization can be carried out with less number of iterations. LDMOS devices have been dominating in the communication field since last decade and are still widely used for PA design and development. This thesis deals with the optimization of RFLDMOS transistor and its evaluation in different PA classes, such as linear, switching, wideband and multi-band applications. For accurate evaluation of RF-LDMOS transistor parameters, some techniques are also developed in technology CAD (TCAD) using large signal time domain computational load-pull (CLP) methods. Initially the RF-LDMOS is studied in TCAD for the improved RF performance. The physical intrinsic structure of RF-LDMOS is provided by Infenion Technologies AG. A reduced surface field (RESURF) of low-doped drain (LDD) region is considered in detail because it plays an important role in RF-LDMOS devices to obtain high breakdown voltage (BVDS). But on the other hand, it also reduces the RF performance due to high on-resistance (Ron). The excess interface state charges at the RESURF region are introduced to reduce the Ron, which not only increases the dc drain current, but also improve the RF performance in terms of power, gain and efficiency. The important achievement is the enhancement in operating frequency up to 4 GHz. In LDD region, the effect of excess interface charges at the RESURF is also compared with dual implanted-layer of p-type and n-type. The comparison revealed that the former provides 43 % reduction in Ron with BVDS of 70 V, while the later provides 26 % reduction in Ron together with BVDS of 64 - 68 V. In the second part of my research work, computational load pull (CLP) simulation technique is used in TCAD to extract the impedances of RF-LDMOS at different frequencies under large signal operation. Flexible matching is an issue in the design of broadband or multi-band PAs. Optimum impedance of RF-LDMOS is extracted at operating frequencies of 1, 2 and 2.5 GHz in class AB PA. After this, CLP simulation technique is further developed in TCAD to study the non-linear behavior of RF devices. Through modified CLP technique, non-linear effects inside the transistor structure are studied by conventional two-tone RF signals in time domain. This is helpful to detect and understand the phenomena, which can be resolved to improve the device performance. The third order inter-modulation distortion (IMD3) of RF- LDMOS was observed at different power levels. The IMD3 of −22 dBc is obtained at 1-dB compression point (P1-dB), while at 10 dB back off the value increases to −36 dBc. These results were also verified experimentally by fabricating a linear PA. Similarly, CLP technique is developed further for the analysis of RF devices in high efficiency operation by investigating the odd harmonic effects for the design of class-F PA. RF-LDMOS can provide a power added efficiency (PAE) of 81.2 % in class-F PA at 1 GHz in TCAD simulations. The results are verified by design and fabrication of class-F PA using large signal model of the similar device in ADS. In fabrication, a PAE of 76 % is achieved.

APA, Harvard, Vancouver, ISO, and other styles

4

Srirattana, Nuttapong. "High-Efficiency Linear RF Power Amplifiers Development." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6899.

Full text

Abstract:

Next generation mobile communication systems require the use of linear RF power amplifier for higher data transmission rates. However, linear RF power amplifiers are inherently inefficient and usually require additional circuits or further system adjustments for better efficiency. This dissertation focuses on the development of new efficiency enhancement schemes for linear RF power amplifiers. The multistage Doherty amplifier technique is proposed to improve the performance of linear RF power amplifiers operated in a low power level. This technique advances the original Doherty amplifier scheme by improving the efficiency at much lower power level. The proposed technique is supported by a new approach in device periphery calculation to reduce AM/AM distortion and a further improvement of linearity by the bias adaptation concept. The device periphery adjustment technique for efficiency enhancement of power amplifier integrated circuits is also proposed in this work. The concept is clearly explained together with its implementation on CMOS and SiGe RF power amplifier designs. Furthermore, linearity improvement technique using the cancellation of nonlinear terms is proposed for the CMOS power amplifier in combination with the efficiency enhancement technique. In addition to the efficiency enhancement of power amplifiers, a scalable large-signal MOSFET model using the modified BSIM3v3 approach is proposed. A new scalable substrate network model is developed to enhance the accuracy of the BSIM3v3 model in RF and microwave applications. The proposed model simplifies the modeling of substrate coupling effects in MOS transistor and provides great accuracy in both small-signal and large-signal performances.

APA, Harvard, Vancouver, ISO, and other styles

5

Heo, Deukhyoun. "Silicon MOS field effect transistor RF/Microwave nonlinear model study and power amplifier development for wireless communications." Diss., Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/15618.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Sun, Wenyuan. "Impact of As-grown and Radiation-induced Traps on GaN RF and Power Transistor Performance and Reliability." The Ohio State University, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1586989454689707.

Full text

APA, Harvard, Vancouver, ISO, and other styles

7

Willemann, Michael Howard. "Polymer-Supported Bridges for Multi-Finger AlGaN/GaN Heterojunction Field Effect Transistors (HFETs)." Thesis, Virginia Tech, 2007. http://hdl.handle.net/10919/34801.

Full text

Abstract:

Current AlGaN/GaN Heterojunction Field Effect Transistors (HFETs) make use of multiple sources, drains, and gates in parallel to maximize transconductance and effective gain while minimizing the current density through each channel. To connect the sources to a common ground, current practice prescribes the fabrication of air bridges above the gates and drains. This practice has the advantage of a low dielectric constant and low parasitic capacitance, but it is at the expense of manufacturability and robust device operation. In the study described below, the air bridges in AlGaN/GaN HFETs were replaced by a polymer supported metallization bridge with the intention of improving ease of fabrication and reliability. The DC, high frequency, and power performance for several polymer step heights were investigated. The resultant structures were functional and robust; however, their electrical performance was degraded due to high source resistance. The cause of the high source resistance was found to be thinning of the metallization at the polymer step. The effect was more pronounced for higher step heights.
Master of Science

APA, Harvard, Vancouver, ISO, and other styles

8

Connor, Mark Anthony. "Design of Power-Scalable Gallium Nitride Class E Power Amplifiers." University of Dayton / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1405437893.

Full text

APA, Harvard, Vancouver, ISO, and other styles

9

Banerjee, Aritra. "Design of digitally assisted adaptive analog and RF circuits and systems." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/52919.

Full text

Abstract:

With more and more integration of analog and RF circuits in scaled CMOS technologies, process variation is playing a critical role which makes it difficult to achieve all the performance specifications across all the process corners. Moreover, at scaled technology nodes, due to lower voltage and current handling capabilities of the devices, they suffer from reliability issues that reduce the overall lifetime of the system. Finally, traditional static style of designing analog and RF circuits does not result in optimal performance of the system. A new design paradigm is emerging toward digitally assisted analog and RF circuits and systems aiming to leverage digital correction and calibration techniques to detect and compensate for the manufacturing imperfections and improve the analog and RF performance offering a high level of integration. The objective of the proposed research is to design digital friendly and performance tunable adaptive analog/RF circuits and systems with digital enhancement techniques for higher performance, better process variation tolerance, and more reliable operation and developing strategy for testing the proposed adaptive systems. An adaptation framework is developed for process variation tolerant RF systems which has two parts – optimized test stimulus driven diagnosis of individual modules and power optimal system level tuning. Another direct tuning approach is developed and demonstrated on a carbon nanotube based analog circuit. An adaptive switched mode power amplifier is designed which is more digital-intensive in nature and has higher efficiency, improved reliability and better process resiliency. Finally, a testing strategy for adaptive RF systems is shown which reduces test time and test cost compared to traditional testing.

APA, Harvard, Vancouver, ISO, and other styles

10

Rennesson, Stéphanie. "Développement de nouvelles hétérostructures HEMTs à base de nitrure de gallium pour des applications de puissance en gamme d'ondes millimétriques." Phd thesis, Université Nice Sophia Antipolis, 2013. http://tel.archives-ouvertes.fr/tel-00943619.

Full text

Abstract:

Les matériaux III-N sont présents dans la vie quotidienne pour des applications optoélectroniques (diodes électroluminescentes, lasers). Les propriétés remarquables du GaN (grand gap, grand champ de claquage, champ de polarisation élevé, vitesse de saturation des électrons importante...) en font un candidat de choix pour des applications en électronique de puissance à basse fréquence, mais aussi à haute fréquence, par exemple en gamme d'ondes millimétriques. L'enjeu de ce travail de thèse consiste à augmenter la fréquence de travail des transistors tout en maintenant une puissance élevée. Pour cela, des hétérostructures HEMTs (High Electron Mobility Transistors) sont développées et les épaisseurs de cap et de barrière doivent être réduites, bien que ceci soit au détriment de la puissance délivrée. Une étude sera donc menée sur l'influence des épaisseurs de cap et de barrière ainsi que le type de barrière (AlGaN, AlN et InAlN) de manière à isoler les hétérostructures offrant le meilleur compromis en termes de fréquence et de puissance. De plus, les moyens mis en œuvre pour augmenter la fréquence de travail entrainent une dégradation du confinement des électrons du canal. De manière à limiter cet effet, une back-barrière est insérée sous le canal. Ceci fera l'objet d'une deuxième étude. Enfin, une étude de la passivation de surface des transistors sera menée. La combinaison des ces trois études permettra d'identifier la structure optimale pour délivrer le plus de puissance à haute fréquence (ici à 40 GHz).

APA, Harvard, Vancouver, ISO, and other styles

11

Coulot, Thomas. "Stratégie d'alimentation pour les SoCs RF très faible consommation." Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-00951423.

Full text

Abstract:

Les réseaux de capteurs sans fil nécessitent des fonctions de calcul et de transmissionradio associées à chaque capteur. Les SoCs RF intégrant ces fonctions doivent avoir uneautonomie la plus grande possible et donc une très faible consommation. Aujourd'hui, leursperformances énergétiques pourraient être fortement améliorées par des systèmes d'alimentationinnovants. En effet, les circuits d'alimentation remplissent leur fonction classique de conversiond'énergie mais aussi des fonctions d'isolation des blocs RF et digitaux. Leurs performancess'évaluent donc en termes d'efficacité énergétique et de réponse transitoire mais aussi d'isolationentre blocs et de réjection de bruit.Ce travail de thèse concerne l'intégration du système de gestion et de distribution del'énergie aux différents blocs RF d'un émetteur/récepteur en élaborant une méthodologie " topdown" pour déterminer la sensibilité de chaque bloc à son alimentation et en construisant unearchitecture innovante et dynamique de gestion/distribution de l'énergie sur le SoC. Cetteméthodologie repose sur la disponibilité de régulateurs de tension présentant des performancesadaptées. Un deuxième volet du travail de thèse a donc été de réaliser un régulateur linéaire detype LDO à forte réjection sur une bande passante relativement large et bien adapté àl'alimentation de blocs RF très sensibles aux bruits de l'alimentation.

APA, Harvard, Vancouver, ISO, and other styles

12

Giry, Alexandre. "Étude des potentialités des technologies CMOS avancées pour les radiofréquences : application aux amplificateurs de puissance." Grenoble INPG, 2001. http://www.theses.fr/2001INPG0057.

Full text

APA, Harvard, Vancouver, ISO, and other styles

13

Hniki, Saâdia. "Contribution à la modélisation des dispositifs MOS haute tension pour les circuits intégrés de puissance ("Smart Power")." Toulouse 3, 2010. http://thesesups.ups-tlse.fr/1162/.

Full text

Abstract:

Au cours des dernières décennies, les circuits intégrés de puissance ont connu une croissance très importante. Aujourd'hui la régulation et distribution d'énergie électrique jouent un rôle crucial. La réduction constante des dimensions ainsi que le besoin en densité de puissance de plus en plus élevée ont mis en évidence la nécessité de structures toujours plus performantes. La technologie “smart power” a été développée pour satisfaire ces demandes. Cette technologie utilise les dispositifs DMOS, offrant de nouvelles solutions grâce à ses caractéristiques uniques forte tension et fort courant. Le fonctionnement de ces dispositifs est accompagné par l’apparition de nombreux phénomènes. Une bonne modélisation permet de rendre compte de ces phénomènes et prédire le comportement physique du transistor avant sa production. L'objectif de cette thèse était donc d'améliorer la modélisation et de mettre en place une méthode d'extraction de certains paramètres physiques liés au fonctionnement du MOS HV (High Voltage). Cette thèse a été principalement dédiée à la modélisation du phénomène de l'auto-échauffement et à la définition d'une méthode d'extraction des parasites RF dans les transistors MOS et, enfin, à la comparaison du macro-modèle utilisé par STMicroelectronics avec le modèle compact HiSIM-HV dédié au MOS HV. Pour cela, il était essentiel de mettre en place des nouvelles procédures de modélisation et d'extraction et de dessiner des structures de test spécifiques. Les résultats présentés dans cette thèse ont été validés par différentes comparaisons avec les mesures en technologies sur SOI et sur substrat massif
In recent decades, power integrated circuits have experienced very significant growth. Today the regulation and distribution of electrical energy are crucial. The reduction of the dimensions and the need for power highlighted the need for efficient structures. Technology "smart power" has been developed to meet these demands. This technology uses high voltage devices, offering new solutions through its unique characteristics at high voltages and currents. The behavior of these devices is accompanied by the appearance of many phenomena. An accurate modeling of these phenomena is needed to replicate its physical behavior. The objective of this thesis is to improve modeling and to establish a good method of extracting physical parameters related to HV MOS. This thesis has been mainly devoted to modeling the phenomenon of self-heating: development of test structure, modeling of thermal coupling between the sources of transistor, development tool for generating the thermal network. This thesis also looks at the definition of a method for extracting RF noise in the high-voltage transistor including extrinsic gate resistance and capacity Cgs and Cgd. Finally, the last part of the thesis presents a brief assessment of compact HiSIM_HV dedicated to HV MOS and compares it with the macro model used by STMicroelectronics. The results presented in this thesis have been validated by comparison with different measures on SOI technology and solid substrate

APA, Harvard, Vancouver, ISO, and other styles

14

Bengtsson, Olof. "Design and Characterization of RF-Power LDMOS Transistors." Doctoral thesis, Uppsala : University Library, Universitetsbiblioteket, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-9259.

Full text

APA, Harvard, Vancouver, ISO, and other styles

15

Akhtar, Siraj. "Modeling of RF power transistors for power amplifier design /." The Ohio State University, 2000. http://rave.ohiolink.edu/etdc/view?acc_num=osu1488196781733682.

Full text

APA, Harvard, Vancouver, ISO, and other styles

16

EL-Rashid, Jihad, and Youssef Tawk. "Current Distribution in High RF Power Transistors." Thesis, University of Gävle, Ämnesavdelningen för elektronik, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-5735.

Full text

Abstract:

To obtain the power levels required from high RF power transistors, the size of the chip has often to be made so large that inductance of electrical connections inside the package cannot be neglected. This may have the effect that various parts of the transistor chip are not connected exactly parallel, i.e. drain and gate voltages and currents densities will not be the same on different parts of the chip. This may result in degraded output power and efficiency. The same effect may occur when more than one chip are connected in parallel in a transistor package to obtain even higher output power.Often the connections to the transistor package are approximated as a number of electrical point connections (normally three: gate, drain, source); meaning that each of them can be described by a single electrical potential and current. In reality, they may be large enough that voltage and current distributions have to be considered. These distributions will be affected by different mountings of the transistor and other connected components.In this work, the LDMOS power transistor MRF6S21140HR3 was modeled using the segmentation method in high frequency signal simulation HFSS which is a 3D Full-Wave Electromagnetic Field Simulation, and utilized the advanced design system ADS to find a parameterized lumped model. Both the electromagnetic and lumped models showed consistent results. Non-ideal parallel connection of sub-transistors on chip is very important, but further studies are needed for definite conclusion. It was verified through modeling that non ideal parallel connection of different chips in the package does have an effect; the effect however is quiet small which proves that the signal is slightly non-uniformly distributed between the three chips in the package. External connection to PCB (drain connection is considered in this work) can effectively be taken as a point connection to some approximation. The electrical behavior of the modeled transistor was studied through the design of a class B power amplifier in order to estimate the importance of performance degradation due to non-ideal parallel connections and how these non ideal connections degrade efficiency and output power. The modeled transistor can deliver a maximum output power of 147 watts and efficiency of 65%. We have also studied the current distribution between the three chips in a three stage class B power amplifier. Again, the difference in the current distribution between the three chips turned out to be quiet small. All these results are presented through this work. The final conclusion regarding the current distribution between multichips cannot be made just based on these simulation results. The next step should be aimed at considering other effects, the thermal effect for example, in order to know exactly whether it is uniformly or not uniformly distributed.

APA, Harvard, Vancouver, ISO, and other styles

17

Hniki, Saadia. "Contribution à la modélisation des dispositifs MOS haute tension pour les circuits intégrés de puissance ("Smart Power")." Phd thesis, Université Paul Sabatier - Toulouse III, 2010. http://tel.archives-ouvertes.fr/tel-00581114.

Full text

Abstract:

Au cours des dernières décennies, les circuits intégrés de puissance ont connu une croissance très importante. Aujourd'hui la régulation et distribution d'énergie électrique jouent un rôle crucial. La réduction constante des dimensions ainsi que le besoin en densité de puissance de plus en plus élevée ont mis en évidence la nécessité de structures toujours plus performantes. La technologie "smart power" a été développée pour satisfaire ces demandes. Cette technologie utilise les dispositifs DMOS, offrant de nouvelles solutions grâce à ses caractéristiques uniques forte tension et fort courant. Le fonctionnement de ces dispositifs est accompagné par l'apparition de nombreux phénomènes. Une bonne modélisation permet de rendre compte de ces phénomènes et prédire le comportement physique du transistor avant sa production. L'objectif de cette thèse était donc d'améliorer la modélisation et de mettre en place une méthode d'extraction de certains paramètres physiques liés au fonctionnement du MOS HV (High Voltage). Cette thèse a été principalement dédiée à la modélisation du phénomène de l'auto-échauffement et à la définition d'une méthode d'extraction des parasites RF dans les transistors MOS et, enfin, à la comparaison du macro-modèle utilisé par STMicroelectronics avec le modèle compact HiSIM_HV dédié au MOS HV. Pour cela, il était essentiel de mettre en place des nouvelles procédures de modélisation et d'extraction et de dessiner des structures de test spécifiques. Les résultats présentés dans cette thèse ont été validés par différentes comparaisons avec les mesures en technologies sur SOI et sur substrat massif.

APA, Harvard, Vancouver, ISO, and other styles

18

Xia, Zhanbo. "Materials and Device Engineering for High Performance β-Ga2O3-based Electronics." The Ohio State University, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1587688595358557.

Full text

APA, Harvard, Vancouver, ISO, and other styles

19

Bordelon, John H. "A large-signal model for the RF power MOSFET." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/15048.

Full text

APA, Harvard, Vancouver, ISO, and other styles

20

Cao, Guangjun. "Physics and technology of silicon RF power devices." Thesis, De Montfort University, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.391785.

Full text

APA, Harvard, Vancouver, ISO, and other styles

21

Bertilsson, Kent. "Simulation and Optimization of SiC Field Effect Transistors." Doctoral thesis, KTH, Microelectronics and Information Technology, IMIT, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-81.

Full text

Abstract:

Silicon Carbide (SiC) is a wide band-gap semiconductor material with excel-lent material properties for high frequency, high power and high temperature elec-tronics. In this work different SiC field-effect transistors have been studied using theoretical methods, with the focus on both the devices and the methods used. The rapid miniaturization of commercial devices demands better physical models than the drift-diffusion and hydrodynamic models most commonly used at present.

The Monte Carlo method is the most accurate physical methods available and has been used in this work to study the performance in short-channel SiC field-effect devices. The drawback of the Monte-Carlo method is the computational power required and it is thus not well suited for device design where the layout requires to be optimized for best device performance. One approach to reduce the simulation time in the Monte Carlo method is to use a time-domain drift-diffusion model in contact and bulk regions of the device. In this work, a time-domain drift-diffusion model is implemented and verified against commercial tools and would be suitable for inclusion in the Monte-Carlo device simulator framework.

Device optimization is traditionally performed by hand, changing device pa-rameters until sufficient performance is achieved. This is very time consuming work without any guarantee of achieving an optimal layout. In this work a tool is developed, which automatically changes device layout until optimal device per-formance is achieved. Device optimization requires hundreds of device simulations and thus it is essential that computationally efficient methods are used. One impor-tant physical process for RF power devices is self heating. Self heating can be fairly accurately modeled in two dimensions but this will greatly reduce the computa-tional speed. For realistic influence self heating must be studied in three dimensions and a method is developed using a combination of 2D electrical and 3D thermal simulations. The accuracy is much improved by using the proposed method in comparison to a 2D coupled electro/thermal simulation and at the same time offers greater efficiency. Linearity is another very important issue for RF power devices for telecommunication applications. A method to predict the linearity is imple-mented using nonlinear circuit simulation of the active device and neighboring passive elements.

APA, Harvard, Vancouver, ISO, and other styles

22

Cheng, Peng. "Reliability of SiGe HBTs for extreme environment and RF applications." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/42836.

Full text

Abstract:

The objective of the proposed research is to characterize the safe-operating-area of silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) under radiofrequency (RF) operation and extreme environments. The degradation of SiGe HBTs due to mixed-mode DC and RF stress has been modeled for the first time. State-of-the-art 200 GHz SiGe HBTs were first characterized, and then DC and RF stressed. Excess base leakage current was modeled as a function of the stress current and voltage. This physics-based stress model was then designed as a sub-circuit in Cadence, and incorporated into SiGe power amplifier design to predict the DC and RF stress-induced excess base current. Based on these studies, characterization of RF safe-operating-area for SiGe HBTs using devices and circuits is proposed.

APA, Harvard, Vancouver, ISO, and other styles

23

Yi, Changhyun. "InP-based heterojunction bipolar transistors for high speed and RF power applications : advanced emitter-base designs." Diss., Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/13083.

Full text

APA, Harvard, Vancouver, ISO, and other styles

24

Tsui, Kenneth Kin Pun. "RF characterization and modeling of MOSFET power amplifier in wireless communication /." View Abstract or Full-Text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20TSUI.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

Doudorov, Grigori. "Evaluation of Si-LDMOS transistors for RF Power Amplifier in 2-6 GHz frequency range." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1837.

Full text

Abstract:

In this thesis the models of Si-LDMOS transistors have been investigated with Agilent EEsof ADS version 2002a for operation in the 2-6 GHz frequency range. The first one is the Motorola’s (MRF21010) model based on a 30 mm prototype of a Si-LDMOS transistor. The second one is a model based on a 1 mm prototype of Si-LDMOS transistor developed at Chalmers University. Large-signal simulations of Chalmers’ model have demonstrated results, which lead to the conclusion that,this model cannot be efficiently utilised for design for a PA in the 2-6 GHz frequency range. However, additional simulations with reduced Rd (drain losses) show the deep impact of this parameter on the main properties of the designed PA. Hence, it is important to take it into account during new processes of Si-LDMOS as well as to improve the CAD model. The final conclusion regarding Si-LDMOS cannot be made just based on these simulation results, since they are not in accordance with the published ones. The next step should be aimed at improving the model and further investigation of Si-LDMOS to prove their ability to operate in the 2-6 GHz frequency range.

APA, Harvard, Vancouver, ISO, and other styles

26

Wong, Melinda F. "Effect of varying gate-drain distance on the RF power performance of pseudomorphic high electron mobility transistors." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/34638.

Full text

Abstract:

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.
Includes bibliographical references (p. 134-137).
AIGaAs/lnGaAs Pseudomorphic High Electron Mobility Transistors (PHEMTs) are widely used in satellite communications, military and commercial radar, cellular telephones, and other RF power applications. One key figure of merit in these applications is RF power output. Increasing the gate-to-drain length (LRD) of the PHEMT leads to an increase in its breakdown voltage. This should theoretically allow the selection of a higher drain operating voltage and consequently result in higher output power at microwave frequencies. However, experimentally, a decrease in output power and peak power-added efficiency is generally observed with increasing LRD In order to understand this, we have studied in detail the RF power performance of industrial PHEMTs with different values of LRD. We have found that there is an optimum value of LRD beyond which the maximum RF power output that the device can deliver drops. In addition, we have found that the output power of long LRD devices declines significantly with increasing frequency. We explain the difference in RF power behavior of the different devices through the evolution of load lines with frequency, LRD, and operating voltage. We have found that the presence of oscillations in the NDR region limit the maximum allowable operating voltage of long LRD devices through catastrophic burnout. The maximum voltage of short LRD devices is limited by electrical degradation. Pulsed I-V measurements have revealed that long LRD devices increasingly suffer from surface state activity that limit the maximum drain current under RF operation. A delay time analysis has shown an increasing extension of the depletion region toward the drain with increasing LRD that limits the frequency response of long LRD devices.
by Melinda F. Wong.
S.M.

APA, Harvard, Vancouver, ISO, and other styles

27

Fonder, Jean-Baptiste. "Analyse des mécanismes de défaillance dans les transistors de puissance radiofréquences HEMT AlGaN/GaN." Thesis, Cergy-Pontoise, 2012. http://www.theses.fr/2012CERG0576/document.

Full text

Abstract:

Les HEMT AlGaN/GaN sont en passe de devenir incontournables dans le monde de l'amplification de puissance radiofréquence, grâce à leurs performances exceptionnelles. Cependant,en raison de la relative jeunesse de cette technologie, des études de fiabilité dans plusieurs modes de fonctionnement sont toujours nécessaires pour comprendre les mécanismes de défaillance propres à ces composants et responsables de leur vieillissement. Cette étude porte sur l'analyse des défaillances dans les transistors HEMT AlGaN/GaN de puissance,en régime de fonctionnement de type RADAR (pulsé et saturé). Elle s'appuie sur la conception d'amplificateurs de test, leur caractérisation et leur épreuve sur bancs de vieillissement. La mise en place d'une méthodologie visant à discriminer les mécanismes de dégradation prépondérants, conjointement à une analyse micro-structurale des composants vieillis, permet d'établir le lien entre l'évolution des performances électriques et l'origine physique de ces défauts
AlGaN/GaN HEMTs are on the way to lead the radiofrequency power amplificationfield according to their outstanding performances. However, due to the relative youth of this technology, reliability studies in several types of operating conditions are still necessaryto understand failure mechanisms peculiar to these devices and responsible for their wearingout. This study deals with the failure analysis of power AlGaN/GaN HEMTs in RADARoperating mode (pulsed and saturated). This is based on the design of test amplifiers, theircharacterization and their stress on ageing benches. The setting up of a methodology aimingat discriminating predominant degradation modes, jointly with a micro-structural analysisof aged devices, permits to link the evolution of electrical performances with the physicalroots of these defects

APA, Harvard, Vancouver, ISO, and other styles

28

Medrel, Pierre. "Amplification de puissance linéaire à haut rendement en technologie GaN intégrant un contrôle de polarisation de grille." Thesis, Limoges, 2014. http://www.theses.fr/2014LIMO0006/document.

Full text

Abstract:

Cette thèse s’inscrit dans le domaine de l’amplification de puissance microonde linéaire et haut rendement en technologie GaN. Le premier chapitre décrit le contexte général de l’émission de signaux microondes de puissance pour les télécommunications sans fil, avec un focus particulier apporté sur l’amplificateur de puissance RF. Les différents critères de linéarité et d’efficacité énergétique sont introduits.Le second chapitre présente plus particulièrement la technologie GaN et le transistor de puissance comme brique de base pour l’amplification de puissance microonde. Une revue synthétique des différentes architectures relevées dans la littérature relative à l’amplification à haut rendement est faite.En troisième chapitre, le banc de mesure temporelle d’enveloppe développé et servant de support expérimental à cette étude est présenté. Les procédures d’étalonnage et de synchronisation sont décrites. En illustration, une nouvelle méthode de mesure du NPR large bande est présentée, et validée expérimentalement.Une solution d’amplification adaptative innovante est étudiée dans le quatrième chapitre, et constitue le cœur de ce mémoire. Celle-ci se base sur le contrôle dynamique de la polarisation de grille autour du point de pincement, au rythme de l’enveloppe de modulation. Un démonstrateur d’amplification 10W GaN en bande S (2.5GHz) est développé. Comparativement à la classe B fixe, une forte amélioration de la linéarité est obtenue, sans impact notable sur le rendement moyen de l’amplificateur RF. Finalement, une investigation de la technique proposée pour l’amélioration du rendement du modulateur dans l’architecture d’envelope tracking de drain est menée
This work deals with linear and high efficiency microwave power amplification in GaN technology.The first chapter is dedicated to the general context of wireless telecommunication with a special emphasis on the RF power amplifier. The most representative figures of merit in terms of linearity and power efficiency are introduced.The second chapter deals more specifically with the GaN technology and GaN-based transistor for microwave power amplification. A description of the principal architectures found in the literature related to high efficiency and linear amplification is summarized.In the third chapter, the developed envelope time-domain test bench is presented. Time-synchronization and envelope calibration procedures are discussed. As an illustration, a new specific wideband NPR measurement is presented and experimentally validated.An innovative power amplifier architecture is presented in the fourth chapter. It is based on a specific dynamic gate biasing technique of the power amplifier biased close to the pinch-off point. A 10W GaN S-band demonstrator has been developed. Compared to fixed class-B conditions, a linearity improvement has been reported without any prohibitive efficiency degradation of the RF power amplifier. Finally, an investigation of the proposed technique for the efficiency improvement in the drain envelope tracking technique is proposed

APA, Harvard, Vancouver, ISO, and other styles

29

Dai, Wenhua. "Large signal electro-thermal LDMOSFET modeling and the thermal memory effects in RF power amplifiers." Connect to this title online, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1078935135.

Full text

Abstract:

Thesis (Ph. D.)--Ohio State University, 2004.
Title from first page of PDF file. Document formatted into pages; contains xix, 156 p.; also includes graphics (some col.). Includes bibliographical references (p. 152-156).

APA, Harvard, Vancouver, ISO, and other styles

30

Subramani, Nandha kumar. "Physics-based TCAD device simulations and measurements of GaN HEMT technology for RF power amplifier applications." Thesis, Limoges, 2017. http://www.theses.fr/2017LIMO0084/document.

Full text

Abstract:

Depuis plusieurs années, la technologie de transistors à effet de champ à haute mobilité (HEMT) sur Nitrure de Gallium (GaN) a démontré un potentiel très important pour la montée en puissance et en fréquence des dispositifs. Malheureusement, la présence des effets parasites dégrade les performances dynamiques des composants ainsi que leur fiabilité à long-terme. En outre, l'origine de ces pièges et leur emplacement physique restent incertains jusqu'à aujourd'hui. Une partie du travail de recherche menée dans cette thèse est axée sur la caractérisation des pièges existant dans les dispositifs HEMTs GaN à partir de mesures de paramètre S basse fréquence (BF), les mesures du bruit BF et les mesures I(V) impulsionnelles. Parallèlement, nous avons effectué des simulations physiques basées sur TCAD afin d'identifier la localisation des pièges dans le transistor. De plus, notre étude expérimentale de caractérisation et de simulation montre que les mesures BF pourraient constituer un outil efficace pour caractériser les pièges existant dans le buffer GaN, alors que la caractérisation de Gate-lag pourrait être plus utile pour identifier les pièges de barrière des dispositifs GaN HEMT. La deuxième partie de ce travail de recherche est axée sur la caractérisation des dispositifs AlN/GaN HEMT sur substrat Si et SiC. Une méthode d’extraction simple et efficace de la résistance canal et de la résistance de contact a été mise au point en utilisant conjointement la simulation physique et les techniques de caractérisation. Le principe de l’extraction de la résistance canal est basée sur la mesure de la résistance RON. Celle-ci est calculée à partir des mesures de courant de drain IDS et de la tension VDS pour différentes valeurs de températures En outre, nous avons procédé à une évaluation complète du comportement thermique de ces composants en utilisant conjointement les mesures et les simulations thermiques tridimensionnelles (3D) sur TCAD. La résistance thermique (RTH) a été extraite pour les transistors de différentes géométries à l'aide des mesures et ensuite validée par les simulations thermiques sur TCAD
GaN High Electron Mobility Transistors (HEMTs) have demonstrated their capabilities to be an excellent candidate for high power microwave and mm-wave applications. However, the presence of traps in the device structure significantly degrades the device performance and also detriments the device reliability. Moreover, the origin of these traps and their physical location remains unclear till today. A part of the research work carried out in this thesis is focused on characterizing the traps existing in the GaN/AlGaN/GaN HEMT devices using LF S-parameter measurements, LF noise measurements and drain-lag characterization. Furthermore, we have used TCAD-based physical device simulations in order to identify the physically confirm the location of traps in the device. Moreover, our experimental characterization and simulation study suggest that LF measurements could be an effective tool for characterizing the traps existing in the GaN buffer whereas gate-lag characterization could be more useful to characterize the AlGaN barrier traps of GaN HEMT devices. The second aspect of this research work is focused on characterizing the AlN/GaN/AlGaN HEMT devices grown on Si and SiC substrate. We attempt to characterize the temperature-dependent on-resistance (RON) extraction of these devices using on-wafer measurements and TCAD-based physical simulations. Furthermore, we have proposed a simplified methodology to extract the temperature and bias-dependent channel sheet resistance (Rsh) and parasitic series contact resistance (Rse) of AlN/GaN HEMT devices. Further, we have made a comprehensive evaluation of thermal behavior of these devices using on-wafer measurements and TCAD-based three-dimensional (3D) thermal simulations. The thermal resistance (RTH) has been extracted for various geometries of the device using measurements and validated using TCAD-thermal simulations

APA, Harvard, Vancouver, ISO, and other styles

31

Plet, Sullivan. "Conception d'amplificateurs intégrés de puissance en technologies Silicium pour station de base de la quatrième génération des systèmes de radiocommunications cellulaires." Thesis, Limoges, 2016. http://www.theses.fr/2016LIMO0095/document.

Full text

Abstract:

Ces travaux de recherche concernent les amplificateurs RF de puissance pour stations de base. La technologie actuelle de transistor RF la plus compétitive, le LDMOS, est confrontée à l’augmentation constante du débit et à la concurrence d’autres technologies comme le HEMT GaN. Un autre challenge est l’intégration de l’adaptation de sortie réalisée en dehors du boîtier qui n’est plus compatible avec les futurs standards combinant jusqu’à soixante-quatre amplificateurs de puissance proches les uns des autres.Une première piste envisagée dans cette thèse est le substrat Si à haute résistivité. A partir de simulations puis de mesures sur plaques, l’amélioration du facteur de qualité des éléments passifs a été démontrée mais ces premières investigations ne permettent pas l’intégration de l’adaptation de sortie avec la technologie actuelle bien que les résultats soient très encourageants. Les challenges technologiques de ce nouveau substrat ont mené à considérer la structure différentielle pour les amplificateurs. En plus des avantages connus de cette configuration, nous avons montré que la conception d’un amplificateur de puissance différentiel montre une amélioration importante de la bande instantanée répondant au besoin d’un débit toujours plus élevé. Cette amélioration ne dégrade pas les autres performances en gain, rendement et puissance de sortie. Dans la continuité de cette thèse, les perspectives concernent la conception d’un amplificateur de puissance sur substrat SI à haute résistivité combinée à une structure différentielle qui pourrait permettre une avancée majeure sur toutes les performances tout en gardant l’avantage du faible coût du LDMOS Silicium en comparaison des autres substrats
This research concerns the RF power amplifiers for base stations. The current most competitive technology of RF transistor, the LDMOS, faces the constantly increasing data rate and competition from other technologies such as GaN HEMT. Another challenge is the integration of the output matching made outside of the package which is not compatible with future standards combining up to sixty-four power amplifiers close to each other. A first track proposed in this thesis is the high resistivity Si substrate. From simulations and measurements on wafers, improved passive elements quality factor has been demonstrated but these initial investigations do not allow the integration of the output matching with the current technology, although the results are very encouraging. The technological challenges of this new substrate led to consider the differential structure for amplifiers. Besides to the known advantages of this configuration, we have shown that the design of a differential power amplifier shows a significant improvement in the instantaneous band width meeting the need for higher data rate. This improvement does not degrade other performance as gain, efficiency and output power. In continuation of this thesis, the perspective concerns the design of a power amplifier on a high resistivity Si substrate combined with a differential structure that could enable a major advance over all performance while keeping the advantage of low cost of LDMOS silicon compared to other substrates

APA, Harvard, Vancouver, ISO, and other styles

32

Coen, Christopher T. "Development and integration of silicon-germanium front-end electronics for active phased-array antennas." Thesis, Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/48990.

Full text

Abstract:

The research presented in this thesis leverages silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technology to develop microwave front-end electronics for active phased-array antennas. The highly integrated electronics will reduce costs and improve the feasibility of snow measurements from airborne and space-borne platforms. Chapter 1 presents the motivation of this research, focusing on the technological needs of snow measurement missions. The fundamentals and benefits of SiGe HBTs and phased-array antennas for these missions are discussed as well. Chapter 2 discusses SiGe power amplifier design considerations for radar systems. Basic power amplifier design concepts, power limitations in SiGe HBTs, and techniques for increasing the output power of SiGe HBT PAs are reviewed. Chapter 3 presents the design and characterization of a robust medium power X-band SiGe power amplifier for integration into a SiGe transmit/receive module. The PA design process applies the concepts presented in Chapter 2. A detailed investigation into measurement-to-simulation discrepancies is outlined as well. Chapter 4 discusses the development and characterization of a single-chip X-band SiGe T/R module for integration into a very thin, lightweight active phased array antenna panel. The system-on-package antenna combines the high performance and integration potential of SiGe technologies with advanced substrates and packaging techniques to develop a high performance scalable antenna panel using relatively low-cost materials and silicon-based electronics. The antenna panel presented in this chapter will enable airborne SCLP measurements and advance the technology towards an eventual space-based SCLP measurement instrument that will satisfy a critical Earth science need. Finally, Chapter 5 provides concluding remarks and discusses future research directions.

APA, Harvard, Vancouver, ISO, and other styles

33

El, Ghouli Salim. "UTBB FDSOI mosfet dynamic behavior study and modeling for ultra-low power RF and mm-Wave IC Design." Thesis, Strasbourg, 2018. http://www.theses.fr/2018STRAD015/document.

Full text

Abstract:

Ce travail de recherche a été principalement motivé par les avantages importants apportés par la technologie UTBB FDSOI aux applications analogiques et RF de faible puissance. L'objectif principal est d'étudier le comportement dynamique du transistor MOSFET du type UTBB FDSOI et de proposer des modèles prédictifs et des recommandations pour la conception de circuits intégrés RF, en mettant un accent particulier sur le régime d'inversion modérée. Après une brève analyse des progrès réalisés au niveau des architectures du transistor MOSFET, un état de l’art de la modélisation du transistor MOSFET UTBB FDSOI est établi. Les principaux effets physiques impliqués dans le transistor à double grille avec une épaisseur du film de 7 nm sont passés en revue, en particulier l’impact de la grille arrière, à l’aide de mesures et de simulations TCAD. La caractéristique gm/ID en basse fréquence et la caractéristique ym/ID proposée pour la haute fréquence sont étudiées et utilisées dans une conception analogique efficace. Enfin, le modèle NQS haute fréquence proposé reproduit les mesures dans toutes les conditions de polarisation y compris l’inversion modérée jusqu’à 110 GHz
This research work has been motivated primarily by the significant advantages brought about by the UTBB FDSOI technology to the Low power Analog and RF applications. The main goal is to study the dynamic behavior of the UTBB FDSOI MOSFET in light of the recent technology advances and to propose predictive models and useful recommendations for RF IC design with particular emphasis on Moderate Inversion regime. After a brief review of progress in MOSFET architectures introduced in the semiconductor industry, a state-of-the-art UTBB FDSOI MOSFET modeling status is compiled. The main physical effects involved in the double gate transistor with a 7 nm thick film are reviewed, particularly the back gate impact, using measurements and TCAD. For better insight into the Weak Inversion and Moderate Inversion operations, both the low frequency gm/ID FoM and the proposed high frequency ym/ID FoM are studied and also used in an efficient first-cut analog design. Finally, a high frequency NQS model is developed and compared to DC and S-parameters measurements. The results show excellent agreement across all modes of operation including very low bias conditions and up to 110 GHz

APA, Harvard, Vancouver, ISO, and other styles

34

Cui, Xian. "Efficient radio frequency power amplifiers for wireless communications." Columbus, Ohio : Ohio State University, 2007. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1195652135.

Full text

APA, Harvard, Vancouver, ISO, and other styles

35

Disserand, Anthony. "Nouvelle architecture d’amplificateur de puissance fonctionnant en commutation." Thesis, Limoges, 2017. http://www.theses.fr/2017LIMO0107/document.

Full text

Abstract:

L’essor et l’évolution des systèmes de télécommunication sont liés inéluctablement à la montée en fréquence et à l’augmentation des bandes passantes des futurs systèmes d’une part, et à une place sans cesse croissante prise par l’électronique numérique dans les chaînes d’émission/réception d’autre part. Concernant ce deuxième aspect, la génération de puissance RF avant émission est encore à ce jour implémentée de façon analogique, mais la gestion énergétique des amplificateurs de puissance RF est de plus en plus assistée numériquement. L’apparition du ‘numérique’ dans le domaine de la puissance RF se traduit par la mise en œuvre de systèmes électroniques fonctionnant en commutation : modulateurs de polarisation pour l’envelope tracking, convertisseurs numérique-analogique de puissance (Power-DAC) ou amplificateurs en commutation à fort rendement (classe S ou D). C’est dans ce contexte que s’inscrivent ces travaux de thèse : deux dispositifs de commutation originaux à base de transistors GaN HEMT sont présentés, analysés et réalisés en technologie MMIC. Ces cellules de commutation élémentaires permettent, jusqu’à des fréquences de quelques centaines de MHz, de commuter des tensions jusqu’à 50V, avec des puissances de l’ordre de 100W, ceci avec un rendement énergétique supérieur à 80%. Ces cellules de commutation sont ensuite utilisées dans diverses applications : deux types de modulateurs de polarisation destinés à l’envelope tracking ainsi que deux architectures d’amplificateurs classe D (demi-pont et pont en H) sont étudiés et les résultats expérimentaux permettent de valider ces différentes topologies
Telecommunication systems development is linked to working frequency and bandwidths increasement of future systems on one hand, and the growing place taken by digital electronics in the transmission chains on the other hand. Concerning the second point, the RF power generation in emitters is still implemented in an analog way, but the energy management of the RF power amplifiers is more and more assisted by numeric devices. The appearance of the 'digital technology' in the field of RF power is characterized by the implementation of high speed switching electronic systems like bias modulators for envelope tracking, power digital to analog converters (Power-DAC) or switching mode RF amplifiers (Classe S or D). This thesis work fits in this context, it describes two original switching devices based on GaN HEMT transistors. These elementary switching cells are realized in MMIC technology, they allow switching frequencies up to few hundreds MHz, with voltages reaching 50V, powers about 100W and energy efficiency greater than 80%. These switching cells are then used in various applications: two kinds of bias modulators for envelope tracking system as well as two architectures of class D amplifiers (half-bridge and full-bridge) are analyzed and validated by experimental results

APA, Harvard, Vancouver, ISO, and other styles

36

Zhang, Hao. "Circuit d'amplification Doherty intégré large bande pour applications radio cellulaires de puissance." Thesis, Poitiers, 2019. http://www.theses.fr/2019POIT2265.

Full text

Abstract:

Ces travaux de recherche concernent la conception, la réalisation et la mesure des circuits d’amplification Doherty LDMOS intégrés large-bande pour stations de base, nécessaires au développement de la 5G. Suite à la recherche des techniques pour l’amélioration du rendement électrique pour des signaux à forte dynamique d’amplitude et les possibilités d’intégration, la technique Doherty a été choisie. Des études sur les structures Doherty à deux puis trois voies montrent que l’amélioration de rendement pourra être renforcée et étendue par l’ajout d’un troisième étage avec des tailles de transistors calculées en prenant en compte un fonctionnement en classe C des étages auxiliaires. Des limitations d’utilisation de la technique Doherty sont montrées par la prise en compte des différentes non-linéarités des transistors LDMOS. La recherche des architectures large-bandes montre que la technique d’absorption du CdS et l’utilisation de circuits de répartition de type mixte en entrée présentent des avantages pour l’intégration. A partir des différentes études, des amplificateurs de puissance Doherty MMIC à trois voies ont été réalisés avec un ratio d’asymétrie de 1 :3 :3 dans la bande de 1805 MHz à 2170 MHz. Les performances expérimentales montrent les potentialités du Doherty et notamment une nette amélioration du rendement sur toute la bande de fréquence. Des considérations spécifiques d’adaptation sont présentées dans le but de réduire les produits de distorsions d’ordre 3, 10 et 12 (IMD 10 /12). Les mesures de linéarité à différentes largeurs de bande instantanées sont très encourageantes et valident la nouvelle architecture du Doherty à trois voies asymétriques
This work presents the design, realization and measurement result of integrated broadband Doherty amplification circuits for base stations, required for 5G. Initially, based on the research for techniques to improve electrical efficiency for signals with high dynamic range, the Doherty technique is chosen to continue the work. Studies on different Doherty architectures showed that performance can be improved and extended by adding a third stage (3-way Doherty) with calculated auxiliary transistors’ sizes for which are operated in class C mode. Limitations on the practical use of the Doherty technique is demonstrated by the considerations of various non linearities of the LDMOS transistors. The research of wideband architectures shows simultaneous advantages of integration and broadband capability by the CdS absorption technique and the use of mixed type of input splitters. Based on the results of various studies, three-way Doherty MMIC power amplifiers were designed and realized using the CdS absorption technique with an asymmetry ratio of 1 : 3 : 3 in the band of 1805 MHz to 2170 MHz. Experimental performances have shown the potentialities of the 3-way Doherty and a clear efficiency improvement over the entire frequency band. Specific wideband operating conditions are presented to reduce distortion products of third (IMD 3), 10th and 12th (IMD 10/12). The linearity measurements at different instantaneous bandwidths are very encouraging and validate the new asymmetric three-way Doherty architecture

APA, Harvard, Vancouver, ISO, and other styles

37

Ayari, Lotfi. "Contribution au développement d’un banc de mesures temporelles 4-canaux pour la caractérisation avancée de composants et de sous-systèmes RF non linéaires." Thesis, Limoges, 2016. http://www.theses.fr/2016LIMO0117/document.

Full text

Abstract:

Les communications futures pour les applications civiles et militaires utilisent des signaux modulés complexes large bande qui seront émis à travers des amplificateurs de puissance multivoie de type DOHERTY qui devront avoir des performances en puissance, rendement, OBO et largeur de bande qui constituent aujourd’hui un véritable défi à relever. Pour ce faire les concepteurs ont besoin d’outils de caractérisation temporelle permettant la mesure normalisées et l’optimisation des tensions et courants aux accès des dispositifs non linéaires sous pointes ou connectorisés. Ce travail de thèse a permis de mettre en œuvre cet outil de caractérisation temporelle qui a été utilisé pour répondre à des besoins spécifiques pour la modélisation de transistor, pour l’optimisation de leur fonctionnement en termes de stabilité impulsion à impulsion, pour la recherche des conditions optimales de leur fonctionnement dans un amplificateur de type Doherty. Pour cette mise en œuvre une modélisation mathématique des échantillonneurs a été réalisée pour évaluer leurs performances et choisir le mieux adapté à la mesure temporelle RF. Des procédures d’étalonnages rigoureuses ont été développées pour obtenir simultanément des formes d’ondes temporelles calibrées à spectre très large (Basse fréquences jusqu’aux Hyperfréquences)
The future communications for civil and military applications will use complex wideband modulated signals to be transmitted through multi-channel DOHERTY power amplifiers which should have high performance in terms of power, efficiency, OBO, and bandwidth. In order to meet these stringent requirements, designers need time-domain characterization tools for calibrated measurements and for optimizing voltages and currents at both ports of non-linear connectorized or on-wafer devices. This work successfully implements time-domain characterization tools used to meet specific needs for transistor modeling, to optimize their operation in terms of pulse to pulse stability, and to search optimal conditions of their operation modes in a Doherty power amplifier. For this implementation, mathematical modeling is performed to evaluate sampler’s performances in terms of time-domain sampling efficiency in order to choose the best suited sampling architecture for RF time-domain measurements. Rigorous calibration procedures have been developed to obtain simultaneously full time-domain calibrated waveforms (from low Frequencies to Microwave frequencies)

APA, Harvard, Vancouver, ISO, and other styles

38

Courty, Alexis. "Architecture d'amplificateur de puissance linéaire et à haut rendement en technologie GaN de type Doherty numérique." Thesis, Limoges, 2019. http://www.theses.fr/2019LIMO0067/document.

Full text

Abstract:

Les fortes capacités actuelles et envisagées des futurs liens satellites de communication pour la 5G conduisent les signaux traités dans les charges utiles à présenter simultanément d'importantes variations d'amplitude (PAPR>10dB) et de très larges bandes passantes instantanées (BW>1GHz). A l'intérieur du sous-système d'émission hyperfréquence, le fonctionnement du module d'amplification de puissance se trouve très contraint par les formes d'ondes véhiculées, il se présente comme l'un des postes de consommation énergétique des plus importants, et ayant le plus d'impact sur l'intégrité du signal émis. Dans ce contexte, les fonctions dédiées au traitement numérique des signaux et couramment implémentées par le processeur numérique (telles que le filtrage, la canalisation, et éventuellement la démodulation et la régénération des signaux bande de base) embarquées dans les charges utiles, représentent une solution à fort potentiel qui permettrait de relâcher les contraintes reportées sur la fonction d'amplification de puissance afin de gérer au mieux la ressource électrique allouée. Ces travaux de thèse proposent d'étudier les potentialités d'amélioration du fonctionnement en rendement et linéarité d'un amplificateur de type Doherty à double entrée de gamme 20W en technologie GaN et fonctionnant en bande C. La combinaison des signaux de puissance sur la charge RF est optimisée par une distribution optimale des signaux en amplitude et phase à l'entrée par des moyens numériques de génération. Dans un premier temps une méthodologie de conception large bande d'un amplificateur Doherty est introduite et validée par la conception d'un démonstrateur en bande C. Dans un second temps, l'outil expérimental permettant l'extraction des lois optimales de distribution d'amplitude et de phase RF est présenté en détail, et la caractérisation expérimentale du dispositif en double entrée est réalisée puis comparée aux simulations. Finalement, en perspective à ces travaux, une étude préliminaire des potentialités de l'architecture Doherty à double entrée pour la gestion d’une désadaptation de la charge de sortie (gestion de TOS) est menée et des résultats sont mis en avant
The high capabilities of current and future 5G communication satellite links lead the processed signals in the payloads to simultaneously exhibit large amplitude variations (PAPR>10dB) and wide instantaneous bandwidths (BW>1GHz). Within the microwave transmission subsystem, the operation of the power amplification stage is highly constrained by the transmitted waveforms, it is one of the most energy-consuming module of the payload affecting as well the integrity of the transmitted signal. In this context, the functions dedicated to digital signal processing and currently implemented by the digital processor (such as filtering, channeling, and possibly the demodulation and regeneration of baseband signals) embedded in the payloads, represent a potential solution that would reduce the constraints reported on the power amplification function and help to manage the allocated power ressource. This work proposes a study on the capability of dual input power amplifier architectures in order to manage the efficiency-linearity trade-off over a wide bandwidth. This study is carried out on a 20W GaN Doherty demonstrator operating in C band. The combination of the output signals on the RF load is managed by an optimal amplitude and phase distribution that is digitally controlled at the input. Firstly, a wideband design methodology of Doherty amplifier is introduced and validated on a C band demonstrator. In a second time the experimental tool allowing the extraction of amplitude and phase input distributions is presented, the dual input characterization is achieved and compared with simulation results. Finally, in perspective of this work, a preliminary study of the capabilities of the digital Doherty for the management of an output load mismatch (VSWR management) is carried out and the results are put forward

APA, Harvard, Vancouver, ISO, and other styles

39

Delprato, Julien. "Analyse de la stabilité d'impulsion à impulsion des amplificateurs de puissance HEMT GaN pour applications radar en bande S." Thesis, Limoges, 2016. http://www.theses.fr/2016LIMO0060/document.

Full text

Abstract:

Les systèmes radar nécessitent d’être de plus en plus performants et doivent émettre des impulsions les plus identiques possibles. Un critère permet de quantifier la bonne régularité des impulsions radar au cours du temps : la stabilité pulse à pulse. L’amplificateur de puissance est un élément essentiel du système radar. Dans ce sens, ce travail présente une analyse du critère de stabilité pulse à pulse dans le cas d’un amplificateur HEMT GaN. Les formules mathématiques permettant d’extraire la valeur de la stabilité pulse à pulse des mesures temporelles d’enveloppe sont présentées. La conception et la réalisation d’un amplificateur de puissance RF connectorisé 50 Ω sont décrites. Divers cas de rafales radar ont été étudiés au travers des mesures temporelles d’enveloppe pour en quantifier l’impact sur les valeurs de stabilité pulse à pulse. Un banc de mesure hétérodyne de la stabilité pulse à pulse a été spécialement développé pendant ces travaux de thèse. Finalement, ces résultats de stabilité pulse à pulse ont été utilisés pour optimiser le modèle électrique non linéaire du transistor HEMT GaN afin de prendre en compte lors des simulations temporelles d’enveloppe les effets de la thermique et des pièges
Radar-oriented applications require stringent performances. Among them, emitting pulse train with uniform envelope characteristics in term of amplitude and phase. The criterion to quantify the self-consistency of radar signals over the pulse train is the pulse to pulse stability. The power amplifier is the most critical element in the RF radar chain because it has a strong impact on the overall pulse to pulse stability performances. In this context, this work is focused on the study of the impact of a HEMT GaN power amplifier on the pulse to pulse stability. Mathematical approach is presented to derive the pulse to pulse stability from time domain envelope measurements. Design and implementation of a 50Ω matched RF power amplifier are presented. Different radar bursts scenario are investigated and their impact on the pulse to pulse stability are quantified through extensive time domain envelope measurements. For that purpose, a dedicated experimental heterodyne time domain envelope test bench has been developed. These pulse to pulse stability measurements are finally used to optimize and fully validate a nonlinear electrical model of a HEMT GaN, allowing to quantify the relative impact of thermal and trapping effects during circuit envelope simulation in radar-oriented applications

APA, Harvard, Vancouver, ISO, and other styles

40

Hsu, Heng-Ming, and 許恒銘. "Integrated Power MOS Transistor for RF System-On-a-Chip Applications." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/64361917309699092660.

Full text

Abstract:

博士
國立臺灣大學
電機工程學研究所
91
Silicon RF power transistor integrated into 0.18um CMOS technology is proposed at first time in the study. Because of thinner gate oxide and shallow source/drain junction in deep submicron technology, the resulted breakdown voltage of the associated device is inferior for high power operation. In order to enhance the breakdown voltage, one may face with the challenge of integrating power transistor into deep submicron technology. In this study, many efforts are engaged in device engineering; it contains drain engineering by adopting additional mask and substrate engineering by using butted structure to implement the resulted device. Considering both DC and RF characteristics based on the knowledge of device engineering, the breakdown voltage may be improved to 10V and the cutoff and maximum oscillation frequencies to 16GHz and 24GHz, respectively. The resulted device is more than enough to operate at 2.4GHz for Blue tooth and lithium battery applications. The maximum output power can attain 21.26dBm corresponding to power added efficiency 44.3% after optimization of quiescent point on the matrix measurement of large-signal performance. In this study, successfully integrated power device into state-of-the-art technology is demonstrated and it is a milestone for system-on-a-chip (SoC) to provide portable handholds with the properties of short-distance, low-power, and high-frequency operation.

APA, Harvard, Vancouver, ISO, and other styles

41

Lai, Bo-Kang, and 來伯康. "Design and Fabrication of RF Power AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistor." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/rc3a9f.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

Hoile, Gary Alec. "Computer-aided design of RF MOSFET power amplifiers." Thesis, 1992. http://hdl.handle.net/10413/6890.

Full text

Abstract:

The process of designing high power RF amplifiers has in the past relied heavily on measurements, in conjunction with simple linear theory. With the advent of the harmonic balance method and increasingly faster computers, CAD techniques can be of great value in designing these nonlinear circuits. Relatively little work has been done in modelling RF power MOSFETs. The methods described in numerous papers for the nonlinear modelling of microwave GaAsFETs cannot be applied easily to these high power devices. This thesis describes a modelling procedure applicable to RF MOSFETs rated at over 100 W. This is achieved by the use of cold S parameters and pulsed drain current measurements taken at controlled temperatures. A method of determining the required device thermal impedance is given. A complete nonlinear equivalent circuit model is extracted for an MRF136 MOSFET, a 28 V, 15 W device. This includes two nonlinear capacitors. An equation is developed to describe accurately the drain current as a function of the internal gate and drain voltages. The model parameters are found by computer optimisation with measured data. Techniques for modelling the passive components in RF power amplifiers are given. These include resistors, inductors, capacitors, and ferrite transformers. Although linear ferrite transformer models are used, nonlinear forms are also investigated. The accuracy of the MOSFET model is verified by comparison to large signal measurements in a 50 0 system. A complete power amplifier using the MRF136, operating from 118 MHz to 175 MHz is built and analysed. The accuracy of predictions is generally within 10 % for output power and DC supply current, and around 30 % for input impedance. An amplifier is designed using the CAD package, and then built, requiring only a small final adjustment of the input matching circuit. The computer based methods described lead quickly to a near-optimal design and reduce the need for extensive high power measurements. The use of nonlinear analysis programs is thus established as a valuable design tool for engineers working with RF power amplifiers.
Thesis (Ph.D.)-University of Natal, Durban, 1992.

APA, Harvard, Vancouver, ISO, and other styles

43

Chen, Ying Jen, and 陳膺任. "A 2.4GHz RF CMOS Power Amplifier Using High Breakdown Voltage Asymmetric-LDD MOS Transistors." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/51062007806292744050.

Full text

Abstract:

碩士
國立交通大學
電子工程系所
96
This thesis presents a 2.4 GHz RF CMOS power amplifier based on two stages amplifiers topology with asymmetric-lightly-doped-drain (LDD) CMOS power cell which is fully embedded in the conventional foundry logic process with only one additional mask but without extra process step. The power amplifier can achieved higher output power and higher power-added efficiency (PAE) and novel linearity. The simulation result demonstrated 20dB power gain, and 30% PAE with 2.5V supply voltage, 21.5dBm at 1-dB compression point (P1dB), 23.2dBm saturate output power, -41dBc ACPR at 15dBm output power point with standard W-CDMA π/4 QPSK modulation , and ~36dBm OIP3 with 2.75V supply voltage.

APA, Harvard, Vancouver, ISO, and other styles

44

Deng, Jie Hwang James C. M. Bartoli Filbert J. Curtice Walter R. Ooi Boon S. White Marvin H. "Modeling and characterization of gallium nitride based metal-oxide-semiconductor heterostructure field-effect transistors for RF power amplifiers." 2009. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:3373073.

Full text

APA, Harvard, Vancouver, ISO, and other styles

Dissertations / Theses on the topic 'RF power transistor'

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles