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1
Alyaa, Ghanim Sulaiman, and Salim Mahmood AlDabbagh Sufyan. "Modified 128-EEA2 Algorithm by Using HISEC Lightweight Block CipherAlgorithm with Improving the Security and Cost Factors." Indonesian Journal of Electrical Engineering and Computer Science 10, no. 1 (2018): 337–42. https://doi.org/10.11591/ijeecs.v10.i1.pp337-342.
Full textAbstract:
128-EEA2 (Evolved Packet System Encryption Algorithm 2) is a confidentiality algorithm which is used to encrypt and decrypt block of data based on confidentiality key. This confidentiality algorithm 128-EEA2 is based on the AES-128 which is the block cipher algorithm of 128 bit in CTR mode. In this paper, we are going to replace the AES-128 block cipher algorithm by HISEC block cipher algorithm for two reasons such as reducing cost and ameliorate security factor.
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Sidik, Agung Purnomo. "Algoritma Hybrid dengan Kombinasi Elgamal Algorithm dan Electronic Code Book untuk Mengatasi Masalah Key Distribution." JURNAL UNITEK 15, no. 2 (2022): 114–22. http://dx.doi.org/10.52072/unitek.v15i2.309.
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Tujuan dari penelitian ini adalah mengombinasikan algoritma kunci publik Elgamal dengan model operasi Electronic Code Book (ECB) untuk menghasilkan algoritma yang cepat dan aman yang terbebas dari masalah key distribution. Masalah key distribution terjadi dikarenakan adanya proses pengiriman kunci rahasia dalam jaringan publik. Model operasi Electronic Code Book (ECB) digunakan untuk proses enkripsi dengan panjang blok 128-bit. Algoritma Elgamal digunakan untuk mengenkripsi kunci simetris 128-bit yang berbentuk acak untuk menghasilkan cipher key yang bersifat publik atau tidak rahasia. Hasil penelitian menunjukkan masalah key distribution berhasil teratasi. Cipher text yang dihasilkan sangat kuat karena terdapat 2128 kombinasi acak dari cipher text per blok dan 2128 kombinasi kunci acak yang mungkin. Waktu proses dekripsi lebih cepat dari pada waktu proses enkripsi. Waktu proses enkripsi dan dekripsi sangat cepat sehingga cocok digunakan untuk mengenkripsi dan mendekripsi data yang berukuran besar. Sifat kunci yang acak sepanjang 128-bit dan terenkripsi dengan algoritma Elgamal membuat kunci sulit untuk dipecahkan.
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Nagnath, B. Hulle, B. Prathiba, and R. Khope Sarika. "Compact Reconfigurable Architecture for Sosemanuk Stream Cipher." International Journal of Engineering and Advanced Technology (IJEAT) 9, no. 3 (2020): 607–11. https://doi.org/10.35940/ijeat.C5252.029320.
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Sosemanuk is word oriented synchronous stream cipher capable to produce 32 bit ciphertext. It uses variable key from 128 bit to 256 bit and publically known Initialization Vector (IV) of 128 bit. Sosemanuk is one of the finalists in Profile 1 of the eSTREAM Portfolio. This cipher targets to avoid structural properties of SNOW2.0 to improve its efficiency by reducing the internal state size. It also uses reduced round Serpent24 block cipher to provide secure and efficient key loading process. This paper presents compact architecture for Sosemanuk stream cipher. The proposed architecture uses compact S-box architecture and compact modulo adders designed using CLA. The proposed compact S-box minimizes resources utilized without affecting performance. Proposed modulo adder architecture minimizes resources used as compared to conventional CLA implementation. The algorithm was designed by using VHDL language with CAD tool Xilinx ISE design suite 13.2 and implemented on Xilinx Virtex XC5VFX100E FPGA device. The proposed architecture achieved throughput of 4.281 Gbps at clock frequency of 133.788 MHz
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Ghanim Sulaiman, Alyaa, and Sufyan Salim Mahmood AlDabbagh. "Modified 128-EEA2 Algorithm by Using HISEC Lightweight Block Cipher Algorithm with Improving the Security and Cost Factors." Indonesian Journal of Electrical Engineering and Computer Science 10, no. 1 (2018): 337. http://dx.doi.org/10.11591/ijeecs.v10.i1.pp337-342.
Full textAbstract:
<span>128-EEA2 (Evolved Packet System Encryption Algorithm 2) is a confidentiality algorithm which is used to encrypt and decrypt block of data based on confidentiality key. This confidentiality algorithm 128-EEA2 is based on the AES-128 which is the block cipher algorithm of 128 bit in CTR mode. In this paper, we are going to replace the AES-128 block cipher algorithm by HISEC block cipher algorithm for two reasons such as reducing cost and ameliorate security factor.</span>
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Robbi, Rahim, and Ikhwan Ali. "Cryptography Technique with Modular Multiplication Block Cipher and Playfair Cipher." International Journal of Scientific Research in Science and Technology (IJSRST) 2, no. 6 (2016): 71–78. https://doi.org/10.5281/zenodo.239080.
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There are many data security techniques like a cryptography, there are many algorithm like a MMB (Modular Multiplication Block Cipher) and Playfair Cipher. MMB operates using 128-bit plaintext, but it also uses 32-bit subblock MMB text (x0, x1, x2, x3) and 32-bit key subblock (k0, k1, k2, k3) and then the fundamental of this algorithm is determined by a multiplication modulo operation 2<sup>32</sup>-1. Different from MMB, playfair cipher is a diagram substitution cipher which takes two letter from message and replace with two another pair letter, this paper combines playfair cipher as a key substitution and messages in plaintext to be encrypted with algorithms MMB, this combination is expected to increase the security level of messages.
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Ananth, Raghavendra, Panduranga Rao Malode V., and Narayana Swamy Ramaiah. "Hardware-based efficient Mickey-128 stream cipher with unrolling factors for throughput enhancement." Bulletin of Electrical Engineering and Informatics 14, no. 1 (2025): 388–97. http://dx.doi.org/10.11591/eei.v14i1.8270.
Full textAbstract:
The emerging trend known as "ubiquitous computation" aims to incorporate intelligent gadgets into commonplace items. The lightweight cryptographic techniques are being researched and developed to minimize the gadgets' resources and a perpetual desire to reduce production expenses. A key element of symmetric cryptography, the stream cipher has unique benefits in terms of scalability as well as performance. The Mickey-128 stream cipher is designed and implemented in this manuscript. Additionally, unrolling features are incorporated with Mickey-128 cipher to enhance the throughput. The Mickey-128 contains a 128-bit key, an initialization vector (IV), and two clocking registers (R and S) with mapping units. The finite state machine (FSM) controller initializes and controls the key, IV and RS- registers data. The proposed Mickey-128 cipher runs on an Artix-7 field programmable gate array (FPGA) at 639.1 MHz and uses less than 1% of the chip's area (Slices). For unrolling factors 8 and 16, the Mickey-128 cipher achieves a throughput of 5.12 Gbps and 10.23 Gbps, accordingly. Finally, a comparison is made between the proposed Mickey-128 cipher and the existing ciphers' better hardware efficiency and throughput.
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Tew, Jia Jian, Chia Yee Ooi, and Yeam Tan Chong. "Compact Hardware Implementation Of The CLEFIA Block Cipher." Journal of Advanced Research in Computing and Applications 30, no. 1 (2024): 1–6. http://dx.doi.org/10.37934/arca.30.1.16.
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This study presents the implementation of the CLEFIA block cipher, a lightweight symmetric encryption algorithm, with a focus on its application in secure communication and data protection. In recent years, several lightweight block ciphers for hardware implementation have been proposed. Block ciphers are used to protect data in cryptographic applications. CLEFIA is known for its strong security properties and efficient performance, making it suitable for resource-constrained environments. The objective of this report is to implement CLEFIA algorithm in hardware description language and to develop a hardware implementation of the CLEFIA algorithm with less memory space requirement. The report provides an overview of the CLEFIA algorithm, including its round structure, key expansion, and encryption/decryption processes. The implementation process utilizes Verilog, a hardware description language, to design the 128-bit key length of CLEFIA hardware modules. The VCS simulation tool is employed for functional verification, ensuring the correctness of the implementation. Additionally, Design Compiler, a synthesis tool, is utilized for optimizing the design and generating efficient gate-level representations. By incorporating modern tools like VCS, and Design Compiler, along with a modular design technique, the report presents a practical and efficient approach to implementing 128-bit key length of CLEFIA. The use of concurrency and optimized circuitry to carry out high-speed encryption operations is highlighted in the discussion of 128-bit key length of CLEFIA's implementation in hardware. This report outcome has successfully achieved the implementation of 128-bit key length of CLEFIA and successfully reduce the Gate Equivalence (GE) by 76.07% after replacing (96x32)-bit Memory block with Constant Generator and Round Key Generator. This report also examines the possible advantages of CLEFIA implementation in hardware, including improved performance, resource efficiency, and effortless integration with current systems and protocols.
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Ahmed, Abd Ali Abdulkadhim, Nadir George Dena, and Mohammed Radi Arkan. "Subject Review: Data Encryption using Block Cipher Algorithm." International Journal of Computer Science and Mobile Applications (IJCSMA) 10, no. 8 (2022): 42–50. https://doi.org/10.5281/zenodo.6992617.
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<strong><em>The process of “Block ciphering” is basically responsible about encrypting data in blocks; this is done via deterministic and special algorithm with a symmetrical key. Such a cipher is able to encrypts blocks of (128 bit) with a programmed key length of about: 128, 192, or 256 bits. This paper analyses most of the known block cipher algorithms such as, H through two factors (Algorithm specifications, </em></strong><strong><em>function and round).</em></strong>
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Naik, Mahendra Shridhar, Desai Karanam Sreekantha, and Kanduri VSSSS Sairam. "Enabling low-latency IoT communication for resource-constrained devices with the led cipher and decipher protocol." Indonesian Journal of Electrical Engineering and Computer Science 34, no. 2 (2024): 1170. http://dx.doi.org/10.11591/ijeecs.v34.i2.pp1170-1180.
Full textAbstract:
Block cipher algorithms are crucial for securing applications on resource-constrained devices. This paper introduces the modified light encryption device (MLED) cipher-decipher architecture, specifically designed to accommodate both 64-bit and 128-bit key sizes while maintaining a consistent 64-bit block and data size. MLED comprises 8-step and 12-step processes for MLED-64 and MLED-128 modules, respectively. Each stage involves a four-round operation followed by an add-round key operation. The add constant module (ACM) and mixed column modules (MCMs) within the round operation have been optimized for improved latency and throughput. Performance analysis reveals that MLED-64/128 requires less than 1% of the available slices and operates at 125 MHz on the Artix-7 FPGA. It achieves delays of 7.5 and 12.5 clock cycles for MLED-64 and MLED-128, respectively, translating to throughputs of 1366.5 Mbps and 819.89 Mbps. Additionally, MLED-64/128 exhibits hardware efficiencies of 2.373 and 0.986 Mbps/slice, respectively. Comparative evaluations with existing LED and other block ciphers (BCs) demonstrate that MLED-64/128 achieves significant improvements in latency, throughput, and efficiency, making it a compelling choice for securing resource-constrained IoT applications.
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Naik, Mahendra Shridhar, Desai Karanam Sreekantha, and Kanduri VSSSS Sairam. "Enabling low-latency IoT communication for resource-constrained devices with the led cipher and decipher protocol." Indonesian Journal of Electrical Engineering and Computer Science 34, no. 2 (2024): 1170–80. https://doi.org/10.11591/ijeecs.v34.i2.pp1170-1180.
Full textAbstract:
Block cipher algorithms are crucial for securing applications on resource-constrained devices. This paper introduces the modified light encryption device (MLED) cipher-decipher architecture, specifically designed to accommodate both 64-bit and 128-bit key sizes while maintaining a consistent 64-bit block and data size. MLED comprises 8-step and 12-step processes for MLED-64 and MLED-128 modules, respectively. Each stage involves a four-round operation followed by an add-round key operation. The add constant module (ACM) and mixed column modules (MCMs) within the round operation have been optimized for improved latency and throughput. Performance analysis reveals that MLED-64/128 requires less than 1% of the available slices and operates at 125 MHz on the Artix-7 FPGA. It achieves delays of 7.5 and 12.5 clock cycles for MLED-64 and MLED-128, respectively, translating to throughputs of 1366.5 Mbps and 819.89 Mbps. Additionally, MLED-64/128 exhibits hardware efficiencies of 2.373 and 0.986 Mbps/slice, respectively. Comparative evaluations with existing LED and other block ciphers (BCs) demonstrate that MLED-64/128 achieves significant improvements in latency, throughput, and efficiency, making it a compelling choice for securing resource-constrained IoT applications.
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N., B. Hulle, B. Prathiba, R. Khope Sarika, Anuradha K., Borole Yogini, and Kotambka D. "Optimized architecture for SNOW 3G." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (2021): 545–57. https://doi.org/10.11591/ijece.v11i1.pp545-557.
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SNOW 3G is a synchronous, word-oriented stream cipher used by the 3GPP standards as a confidentiality and integrity algorithms. It is used as first set in long term evolution (LTE) and as a second set in universal mobile telecommunications system (UMTS) networks. The cipher uses 128-bit key and 128 bit IV to produce 32-bit ciphertext. The paper presents two techniques for performance enhancement. The first technique uses novel CLA architecture to minimize the propagation delay of the 2 modulo adders. The second technique uses novel architecture for S-box to minimize the chip area. The presented work uses VHDL language for coding. The same is implemented on the FPGA device Virtex xc5vfx100e manufactured by Xilinx. The presented architecture achieved a maximum frequency of 254.9 MHz and throughput of 7.2235 Gbps. 32
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Minh, Nguyen Hieu, Do Thi Bac, Hoang Ngoc Canh, Cong Tran Manh, Duong Phuc Phan, and Nguyen Tuan Khoa. "HYBRID MODEL IN THE BLOCK CIPHER APPLICATIONS FOR HIGH-SPEED COMMUNICATIONS NETWORKS." International Journal of Computer Networks & Communications (IJCNC) 12, july (2020): 55–70. https://doi.org/10.5121/ijcnc.2020.12404.
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The article proposes two different designs for the new block cipher algorithm of 128-bit block size and key lengths of 128-bit or 192-bit or 256-bit. The basic cipher round is designed in a parallel model to help improve the encryption/decryption speed. The differences of this design compared to the previous one developed on Switchable Data Dependent Operations (SDDOs) lies in the hybrid of the controlled elements (CEs) in the structure. Each design has a specific strength that makes the selection more compatible with the objectives of each particular application. The designs all meet the high security standards and possess the ability to fight off the attacks currently known. The designs match the limited environment of the wireless network by integrating effectively when implemented on Field-programmable gate array (FPGA) with both iterative and pipeline architectures for high effective integration.
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Muslih, Muslih, Abdussalam Abdussalam, and Elkaf Rahmawan Pramudya. "Securitary Text on Images with RC-128 Bit Synthric Key Encryption." Journal of Applied Intelligent System 6, no. 2 (2021): 94–102. http://dx.doi.org/10.33633/jais.v6i2.4620.
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The main purpose of using cryptography is to provide the following four basic information security services. One of the purposes of cryptography is secrecy. Confidentiality is the fundamental security service provided by cryptography. This is a security service that stores information from unauthorized persons. Confidentiality can be achieved through a variety of ways ranging from physical security to the use of mathematical algorithms for data encryption. Vernam cipher is a stream cipher where the original data or plain with 8x8 block operation. Experimental results prove that RC4 can perform encryption and decryption with a fast execution process. In this study used a processor with 8GB of RAM. The encryption result of the text used yields the average encryption time and decryption average of 2 second.
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Hulle, N. B., Prathiba B., Sarika R. Khope, K. Anuradha, Yogini Borole, and D. Kotambkar. "Optimized architecture for SNOW 3G." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 1 (2021): 545. http://dx.doi.org/10.11591/ijece.v11i1.pp545-557.
Full textAbstract:
SNOW 3G is a synchronous, word-oriented stream cipher used by the 3GPP standards as a confidentiality and integrity algorithms. It is used as first set in long term evolution (LTE) and as a second set in universal mobile telecommunications system (UMTS) networks. The cipher uses 128-bit key and 128 bit IV to produce 32-bit ciphertext. The paper presents two techniques for performance enhancement. The first technique uses novel CLA architecture to minimize the propagation delay of the 2<sup>32</sup> modulo adders. The second technique uses novel architecture for S-box to minimize the chip area. The presented work uses VHDL language for coding. The same is implemented on the FPGA device Virtex xc5vfx100e manufactured by Xilinx. The presented architecture achieved a maximum frequency of 254.9 MHz and throughput of 7.2235 Gbps.
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Swain, Gandharba, and Saroj Kumar Lenka. "A Dynamic Approach to Image Steganography Using the Three Least Significant Bits and Extended Hill Cipher." Advanced Materials Research 403-408 (November 2011): 842–49. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.842.
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In this paper we propose a technique for secure communication between sender and receiver. We use both cryptography and steganography. We take image as the carrier to use steganography. We have extended the existing hill cipher to increase its robustness and used it as our cryptography algorithm. By using this extended hill cipher (a new block cipher) which uses a 128 bit key, we encrypt the secret message. Then the cipher text of the secret message is embedded into the carrier image in 6th, 7th and 8th bit locations of some of the selected pixels (bytes). The 8th bit in a pixel (byte) is called as the least significant bit (LSB). The pixel selection is done depending on the bit pattern of the cipher text. So for different messages the embedding pixels will be different. That means to know the pixels of the image where the cipher text is embedded we should know the cipher text bits. Thus it becomes a stronger steganography. As the pixels where we embed are chosen during the run time of the algorithm, so we say that it is dynamic steganography. After embedding the resultant image will be sent to the receiver, the receiver will apply the reverse process what the sender has done and get the secret message.
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Omar, A. Dawood. "Fast lightweight block cipher design with involution substitution permutation network (SPN) structure." Indonesian Journal of Electrical Engineering and Computer Science 20, no. 1 (2020): 361–69. https://doi.org/10.11591/ijeecs.v20.i1.pp361-369.
Full textAbstract:
In the present paper, a new cryptographic lightweight algorithm has been developed for the Internet of Things (IoT) applications. The submitted cipher designed with the involution Substitution Permutation Network SPN structure. The involution structure means that the same encryption algorithm is used in the decryption process except the ciphering key algorithm is applied in reverse order. The introduced algorithm encrypts the data with a block size of 128-bit 192-bit or 256-bit, which iterative with 10, 12 and 14- rounds respectively similar to the AES cipher. The design aspect supports an elegant structure with a secure involution round transformation. The main round is built without S-Box stage instead that it uses the on-fly immediate computing stage and the involution of mathematical invertible affine equations. The proposed cipher is adopted to work in a restricted environment and with limited resources pertaining to embedded devices. The proposed cipher introduces an accepted security level and reasonable Gate Equivalent (GE) estimation with fast implementation.
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Indrayani, Lilik Asih, and I. Made Suartana. "Implementasi Kriptografi dengan Modifikasi Algoritma Advanced Encryption Standard (AES) untuk Pengamanan File Document." Journal of Informatics and Computer Science (JINACS) 1, no. 01 (2019): 42–47. http://dx.doi.org/10.26740/jinacs.v1n01.p42-47.
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Abstrak— Algoritma AES (Advanced Encryption Standard) disebut algoritma dengan cipher block symmetric karena untuk memperoleh data yang telah dienkripsi menggunakan kunci rahasia atau cipher key yang sama ketika melakukan proses penyandian data (enkripsi). AES memiliki 3 kategori blok cipher: AES-128, AES-192, dan AES-256 dengan panjang kunci masing-masing 128 bit, 192 bit, dan 256 bit. Perbedaan dari ketiga urutan tersebut adalah panjang kunci yang mempengaruhi jumlah round (putaran). Pada penelitian ini, algoritma AES akan dimodifikasi dengan meningkatkan jumlah putaran bersamaan dengan panjang kunci menjadi 320 bit dengan 16 putaran dengan tujuan meningkatkan keamanan dari algoritma AES. Pengujian dilakukan dengan membandingkan waktu proses enkripsi dan dekripsi antara algoritma AES standar 10 putaran dengan algoritma AES modifikasi 16 putaran. File dokumen yang dapat dienkripsi hanya berupa file dengan format pdf, docx, dan txt. Hasil pengujian menunjukkan bahwa semakin besar putaran dan panjang kunci, maka semakin lama waktu yang digunakan dalam proses enkripsi maupun dekripsi. Hal ini dapat dibuktikan dengan algoritma AES modifikasi yang memiliki nilai waktu proses lebih besar dibanding algoritma AES standar sehingga dapat disimpulkan algoritma AES modifikasi memiliki tingkat keamanan yang lebih tinggi karena berpengaruh pada waktu yang dibutuhkan seorang kriptoanalis untuk memecahkan kode enkripsi. Kata Kunci— Kriptografi; AES (Advanced Encryption Standard); enkripsi; dekripsi; pengamanan file dokumen; modifikasi putaran AES.
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Liu, Ya, Yifan Shi, Dawu Gu, et al. "Improved Meet-in-the-Middle Attacks on Reduced-Round Kiasu-BC and Joltik-BC." Computer Journal 62, no. 12 (2019): 1761–76. http://dx.doi.org/10.1093/comjnl/bxz059.
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Abstract Kiasu-BC and Joltik-BC are internal tweakable block ciphers of authenticated encryption algorithms Kiasu and Joltik submitted to the CAESAR competition. Kiasu-BC is a 128-bit block cipher, of which tweak and key sizes are 64 and 128 bits, respectively. Joltik-BC-128 is a 64-bit lightweight block cipher supporting 128 bits tweakey. Its designers recommended the key and tweak sizes are both 64 bits. In this paper, we propose improved meet-in-the-middle attacks on 8-round Kiasu-BC, 9-round and 10-round Joltik-BC-128 by exploiting properties of their structures and using precomputation tables and the differential enumeration. For Kiasu-BC, we build a 5-round distinguisher to attack 8-round Kiasu-BC with $2^{109}$ plaintext–tweaks, $2^{112.8}$ encrytions and $2^{92.91}$ blocks. Compared with previously best known cryptanalytic results on 8-round Kiasu-BC under chosen plaintext attacks, the data and time complexities are reduced by $2^{7}$ and $2^{3.2}$ times, respectively. For the recommended version of Joltik-BC-128, we construct a 6-round distinguisher to attack 9-round Joltik-BC-128 with $2^{53}$ plaintext–tweaks, $2^{56.6}$ encryptions and $2^{52.91}$ blocks, respectively. Compared with previously best known results, the data and time complexities are reduced by $2^7$ and $2^{5.1}$ times, respectively. In addition, we present a 6.5-round distinguisher to attack 10-round Joltik-BC-128 with $2^{53}$ plaintext–tweaks, $2^{101.4}$ encryptions and $2^{76.91}$ blocks.
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Imdad, Maria, Sofia Najwa Ramli, and Hairulnizam Mahdin. "An Enhanced Key Schedule Algorithm of PRESENT-128 Block Cipher for Random and Non-Random Secret Keys." Symmetry 14, no. 3 (2022): 604. http://dx.doi.org/10.3390/sym14030604.
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The key schedule algorithm (KSA) is a crucial element of symmetric block ciphers with a direct security impact. Despite its undeniable significance, the KSA is still a less focused area in the design of an encryption algorithm. PRESENT is a symmetric lightweight block cipher that provides the optimal balance between security, performance, and minimal cost in IoT. However, the linear functions in KSA lead to a slow and predictable bit transition, indicating the relationship between round keys. A robust KSA should produce random and independent round keys irrespective of the secret key. Therefore, this research aims to improve the KSA PRESENT-128 block cipher with enhanced randomness, round key bit difference, and the avalanche effect. The experiments on round keys and ciphertext with random, low density and high-density secret key datasets endorse the expected improvements. Moreover, the results show that the improved KSA produces random round keys that successfully pass the NIST randomness test. The bit transition from one round key to another is increased from 20% to 40%, where a greater inclination of the avalanche effect has an increased effect with 50% bit change. On the other hand, the improved KSA PRESENT requires an additional 0.001871 s to generate round keys, as a security cost trade-off.
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A. Dawood, Omar. "Fast lightweight block cipher design with involution substitution permutation network (SPN) structure." Indonesian Journal of Electrical Engineering and Computer Science 20, no. 1 (2020): 361. http://dx.doi.org/10.11591/ijeecs.v20.i1.pp361-369.
Full textAbstract:
<p>In the present paper, a new cryptographic lightweight algorithm has been developed for the Internet of Things (IoT) applications. The submitted cipher designed with the involution Substitution Permutation Network SPN structure. The involution structure means that the same encryption algorithm is used in the decryption process except the ciphering key algorithm is applied in reverse order. The introduced algorithm encrypts the data with a block size of 128-bit 192-bit or 256-bit, which iterative with 10, 12 and 14-rounds respectively similar to the AES cipher. The design aspect supports an elegant structure with a secure involution round transformation. The main round is built without S-Box stage instead that it uses the on-fly immediate computing stage and the involution of mathematical invertible affine equations. The proposed cipher is adopted to work in a restricted environment and with limited resources pertaining to embedded devices. The proposed cipher introduces an accepted security level and reasonable Gate Equivalent (GE) estimation with fast implementation.</p>
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Teh, Je Sen, and Azman Samsudin. "A Chaos-Based Authenticated Cipher with Associated Data." Security and Communication Networks 2017 (2017): 1–15. http://dx.doi.org/10.1155/2017/9040518.
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In recent years, there has been a rising interest in authenticated encryption with associated data (AEAD) which combines encryption and authentication into a unified scheme. AEAD schemes provide authentication for a message that is divided into two parts: associated data which is not encrypted and the plaintext which is encrypted. However, there is a lack of chaos-based AEAD schemes in recent literature. This paper introduces a new 128-bit chaos-based AEAD scheme based on the single-key Even-Mansour and Type-II generalized Feistel structure. The proposed scheme provides both privacy and authentication in a single-pass using only one 128-bit secret key. The chaotic tent map is used to generate whitening keys for the Even-Mansour construction, round keys, and random s-boxes for the Feistel round function. In addition, the proposed AEAD scheme can be implemented with true random number generators to map a message to multiple possible ciphertexts in a nondeterministic manner. Security and statistical evaluation indicate that the proposed scheme is highly secure for both the ciphertext and the authentication tag. Furthermore, it has multiple advantages over AES-GCM which is the current standard for authenticated encryption.
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Theda, Flare G. Quilala, M. Sison Ariel, and P. Medina Ruji. "Modified Blowfish Algorithm." Indonesian Journal of Electrical Engineering and Computer Science 12, no. 1 (2018): 38–45. https://doi.org/10.11591/ijeecs.v12.i1.pp38-45.
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Cryptography guarantees security in communication through encryption. This paper proposed a modified Blowfish encryption that uses 128-bit block size and 128-bit key to comply with minimum requirements as an encryption standard. The modification retained the original structure for easy migration but utilized two S-boxes to save memory. A derivation was added to prevent symmetry. The algorithm’s performance was evaluated using time, and avalanche. Upon testing, the modified blowfish is slower with key, encryption, and decryption average of 26.99ms, 1651.83ms, and 2765.04ms compared to blowfish with 21.65ms, 1297.76ms and 2176.59ms due to block size difference. Applying 128-bit block size increases security by decreasing the chances of having duplicate blocks that may leak information. The modified Blowfish is faster compared to Twofish with an encryption and decryption average time of 2418.08ms and 4002.70ms. The added derivation improved the avalanche of the modified blowfish. Blowfish achieved 47.14% while modified Blowfish attained 52.86%.
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Seo, Hwajeong, Hyeokdong Kwon, Hyunji Kim, and Jaehoon Park. "ACE: ARIA-CTR Encryption for Low-End Embedded Processors." Sensors 20, no. 13 (2020): 3788. http://dx.doi.org/10.3390/s20133788.
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In this paper, we present the first optimized implementation of ARIA block cipher on low-end 8-bit Alf and Vegard’s RISC processor (AVR) microcontrollers. To achieve high-speed implementation, primitive operations, including rotation operation, a substitute layer, and a diffusion layer, are carefully optimized for the target low-end embedded processor. The proposed ARIA implementation supports the electronic codebook (ECB) and the counter (CTR) modes of operation. In particular, the CTR mode of operation is further optimized with the pre-computed table of two add-round-key, one substitute layer, and one diffusion layer operations. Finally, the proposed ARIA-CTR implementations on 8-bit AVR microcontrollers achieved 187.1, 216.8, and 246.6 clock cycles per byte for 128-bit, 192-bit, and 256-bit security levels, respectively. Compared with previous reference implementations, the execution timing is improved by 69.8%, 69.6%, and 69.5% for 128-bit, 192-bit, and 256-bit security levels, respectively.
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Ding, Lin, Chenhui Jin, Jie Guan, and Qiuyan Wang. "Cryptanalysis of Loiss Stream Cipher-Revisited." Journal of Applied Mathematics 2014 (2014): 1–7. http://dx.doi.org/10.1155/2014/457275.
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Loiss is a novel byte-oriented stream cipher proposed in 2011. In this paper, based on solving systems of linear equations, we propose an improved Guess and Determine attack on Loiss with a time complexity of 2231and a data complexity of 268, which reduces the time complexity of the Guess and Determine attack proposed by the designers by a factor of 216. Furthermore, a related key chosenIVattack on a scaled-down version of Loiss is presented. The attack recovers the 128-bit secret key of the scaled-down Loiss with a time complexity of 280, requiring 264chosenIVs. The related key attack is minimal in the sense that it only requires one related key. The result shows that our key recovery attack on the scaled-down Loiss is much better than an exhaustive key search in the related key setting.
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Ngo, Chi Trung, Jason K. Eshraghian, and Jong-Phil Hong. "An Area-Optimized and Power-Efficient CBC-PRESENT and HMAC-PHOTON." Electronics 11, no. 15 (2022): 2380. http://dx.doi.org/10.3390/electronics11152380.
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This paper introduces an area-optimized and power-efficient implementation of the Cipher Block Chaining (CBC) mode for an ultra-lightweight block cipher, PRESENT, and the Keyed-Hash Message Authentication Code (HMAC)-expanded PHOTON by using a feedback path for a single block in the scheme. The proposed scheme is designed, taped out, and integrated as a System-on-a-Chip (SoC) in a 65-nm CMOS process. An experimental analysis and comparison between a conventional implementation of CBC-PRESENT/HMAC-PHOTON with the proposed feedback basis is performed. The proposed CBC-PRESENT/HMAC-PHOTON has 128-bit plaintext/text and a 128-bit secret key, which have a gate count of 5683/20,698 and low power consumption of 1.03/2.62 mW with a throughput of 182.9/14.9 Mbps at the maximum clock frequency of 100 MHz, respectively. The overall improvement in area and power dissipation is 13/50.34% and 14.87/75.28% when compared to a conventional design.
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Song, Gyeongju, Kyoungbae Jang, Hyunjun Kim, et al. "SPEEDY Quantum Circuit for Grover’s Algorithm." Applied Sciences 12, no. 14 (2022): 6870. http://dx.doi.org/10.3390/app12146870.
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In this paper, we propose a quantum circuit for the SPEEDY block cipher for the first time and estimate its security strength based on the post-quantum security strength presented by NIST. The strength of post-quantum security for symmetric key cryptography is estimated at the cost of the Grover key retrieval algorithm. Grover’s algorithm in quantum computers reduces the n-bit security of block ciphers to n2 bits. The implementation of a quantum circuit is required to estimate the Grover’s algorithm cost for the target cipher. We estimate the quantum resource required for Grover’s algorithm by implementing a quantum circuit for SPEEDY in an optimized way and show that SPEEDY provides either 128-bit security (i.e., NIST security level 1) or 192-bit security (i.e., NIST security level 3) depending on the number of rounds. Based on our estimated cost, increasing the number of rounds is insufficient to satisfy the security against quantum attacks on quantum computers.
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Tripathy, Alakananda, Sateesh Kumar Pradhan, Ajit Kumar Nayak, Smita Rath, and Alok Ranjan Tripathy. "Integration of PRESENT Cipher Model Using Bit Permutation in Wireless Sensor Network for Data Security." Journal of Computational and Theoretical Nanoscience 17, no. 11 (2020): 5037–45. http://dx.doi.org/10.1166/jctn.2020.9338.
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Security of data has become the biggest concern in recent years, due to the growing number of wireless networks. Accordingly, cryptography is becoming essential in improving data security. Encryption schemes that transforms the data into an incomprehensible shape. It plays an important role in applications such as wireless sensor networks, as most of the data is transmitted through an unsafe channel. Ultra-lightweight cryptography is one the most preferable research areas which having significant contribution towards the security aspects. There is a low power block cipher PRESENT. In this proposed work a PRESENT as reference block cipher is implemented. Here a method called PRESENT block cipher is used with key shuffling and S-Box. This method produces a 64 bits cipher text as result on input text of size 64 bits and key having of 128 bit. This developed method gives better results in comparison to other existing cipher on performance on different hardware and software platforms. With less memory requirement it produces a higher accuracy and confidentiality of the message is maintained. The proposed cipher have the better encryption time, decryption time, throughput. This proposed cipher has better resistance to crypt analysis according to avalanche effect. This proposed cipher can well be applicable for application where small traced area and low power decadence are vital design metrics.
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Tomecek, Jozef. "Hardware optimizations of stream cipher rabbit." Tatra Mountains Mathematical Publications 50, no. 1 (2011): 87–101. http://dx.doi.org/10.2478/v10127-011-0039-8.
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ABSTRACT Stream ciphers form part of cryptographic primitives focused on privacy. Synchronous, symmetric and software-oriented stream cipher Rabbit is member of final portfolio of European Union's eStream project. Although it was designed to perform well in software, employed operations seem to compute efficiently in hardware. 128-bit security, with no known security weaknesses is claimed by Rabbit's designers. Since hardware performance of Rabbit was only estimated in the proposal of algorithm, comparison of direct and optimized FPGA implementations of Rabbit stream cipher is presented, identifying algorithm bottlenecks, discussing optimization techniques applied to algorithm computations, along with key area/time trade-offs.
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Gong, Xue, Xin Zhang, Qianmei Wu, et al. "Practical Opcode-based Fault Attack on AES-NI." IACR Transactions on Cryptographic Hardware and Embedded Systems 2025, no. 3 (2025): 693–716. https://doi.org/10.46586/tches.v2025.i3.693-716.
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AES New Instructions (AES-NI) is a set of hardware instructions introduced by Intel to accelerate AES encryption and decryption, significantly improving efficiency across various cryptographic applications. While AES-NI effectively mitigates certain side-channel attacks, its resilience against faults induced by active or malicious fault injection remains unclear.In this paper, we conduct a comprehensive security analysis of AES-NI. By analyzing the opcodes of AES-NI, we identify six pairs of instructions with only a single-bit difference, making them susceptible to bit-flip-type attacks. This vulnerability allows attackers to recover AES keys in both Electronic Codebook (ECB) and Cipher Block Chaining (CBC) modes. We introduce a novel Opcode-based Fault Analysis (OFA) method, employing Gaussian elimination to reduce the search space of the last round key. In particular, with one pair of correct and faulty ciphertexts, OFA can reduce the key search space to 232 for a 128-bit key length. To further reduce the key space for AES-192 and AES-256, we propose the Enhanced Opcode-based Fault Analysis (EOFA), which, compared to exhaustive search, reduces the key space by factors of 2160 and 2192, respectively.Finally, we demonstrate the feasibility of our findings by conducting physical endto- end attacks. Specifically, Rowhammer is leveraged to flip vulnerable opcodes and OFA as well as EOFA techniques are applied to recover secret keys from AES implementations. Our experimental results for AES-ECB-128, AES-ECB-192, and AES-CBC-128 demonstrate that key recovery can be efficiently achieved within 1.03 to 1.36 hours, varying with the cipher. This work highlights a critical vulnerability in AES-NI and outlines a new and novel pathway for fault-based attacks against modern cryptographic implementations.
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Bansod, Gaurav, Narayan Pisharoty, and Abhijit Patil. "PICO : An Ultra Lightweight and Low Power Encryption Design for Ubiquitous Computing." Defence Science Journal 66, no. 3 (2016): 259. http://dx.doi.org/10.14429/dsj.66.9276.
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<div>An ultra-lightweight, a very compact block cipher ‘PICO’ is proposed. PICO is a substitution and permutation based network, which operates on a 64 bit plain text and supports a key length of 128 bits. It has a compact structure and requires 1877 GEs. Its innovative design helps to generate a large number of active S - boxes in fewer rounds which can thwart the linear and differential attacks on the cipher. PICO shows good performance on both the hardware and the software platforms. PICO consumes only 2504 bytes of Flash memory which is less than the ultra-lightweight cipher PRESENT. PICO has a very strong substitution layer (S-box) which not only makes the design robust but also introduces a great avalanche effect. PICO has a strong and compact key scheduling which is motivated by the latest cipher SPECK designed by NSA. PICO consumes 28 mW of dynamic power which is less than the PRESENT cipher (38 mW). The security analysis of PICO and its performance as an ultra-lightweight cipher are presented. </div><!--[endif]-->
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Ramachandra, Bharathi, and Peter Smitha Elsa. "Secured authentication of radio-frequency identification system using PRESENT block cipher." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 5 (2023): 5462–71. https://doi.org/10.11591/ijece.v13i5.pp5462-5471.
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The internet of things (IoT) is an emerging and robust technology to interconnect billions of objects or devices via the internet to communicate smartly. The radio frequency identification (RFID) system plays a significant role in IoT systems, providing most features like mutual establishment, key establishment, and data confidentiality. This manuscript designed secure authentication of IoT-based RFID systems using the lightweight PRESENT algorithm on the hardware platform. The PRESENT-256 block cipher is considered in this work, and it supports 64-bit data with a 256-key length. The PRESENT-80/128 cipher is also designed along with PRESENT-256 at electronic codebook (ECB) mode for Secured mutual authentication between RFID tag and reader for IoT applications. The secured authentication is established in two stages: Tag recognition from reader, mutual authentication between tag and reader using PRESENT80/128/256 cipher modules. The complete secured authentication of IoTbased RFID system simulation results is verified using the chip-scope tool with field-programmable gate array (FPGA) results. The comparative results for PRESENT block cipher with existing PRESENT ciphers and other lightweight algorithms are analyzed with resource improvements. The proposed secured authentication work is compared with similar RFID-mutual authentication (MA) approaches with better chip area and frequency improvements.
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Ahmed, Fatma, and Dalia H. Elkamchouchi. "A New Modified MARS Cryptosystem Based on Niho Exponent with an Enhanced S-Box Generation." Electronics 11, no. 15 (2022): 2318. http://dx.doi.org/10.3390/electronics11152318.
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As an essential cryptological element, symmetric-key block ciphers have long been utilized to offer information security. Even though they were created to provide data confidentiality, their adaptability grants them to be utilized in the creation of various cryptological techniques, including message authentication protocols, hash functions, and stream cryptograms. MARS is a symmetric shared-key block cryptosystem that supports 128-bit blocks and keys with sizes ranging from 128 to 448 bits. The cryptographic cores of MARS come in a variety of rounds, each constructed to take benefit of the robust outcomes in order to enhance security and performance over earlier ciphers. The MARS cipher is given a new function in this work that uses the operations ROT, XOR, NOP, INV, hash 512, Quotient, and MOD for improving the technique of the cipher. The goal of our modification is attaining a superior confusion level whilst retaining the MARS cryptosystem’s differential and linearity aspects.
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Eum, Siwoo, Minho Song, Sangwon Kim, and Hwajeong Seo. "Efficient GPU Parallel Implementation and Optimization of ARIA for Counter and Exhaustive Key-Search Modes." Electronics 14, no. 10 (2025): 2021. https://doi.org/10.3390/electronics14102021.
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This paper proposes an optimized shared memory access technique to enhance parallel processing performance and reduce memory accesses for the ARIA block cipher in GPU environments. To overcome the limited size of GPU shared memory, we merged ARIA’s four separate S-box tables into a single unified 32-bit table, effectively reducing the total memory usage from 4 KB to 1 KB. This allowed the consolidated table to be replicated 32 times within the limited shared memory, efficiently resolving the memory-bank conflict issues frequently encountered during parallel execution. Additionally, we utilized CUDA’s built-in function __byte_perm() to efficiently reconstruct the desired outputs from the reduced unified table, without imposing additional computational overhead. In exhaustive key-search scenarios, we implemented an on-the-fly key-expansion method, significantly reducing the memory usage per thread and enhancing parallel processing efficiency. In the RTX 3060 environment, profiling was performed to accurately analyze shared memory efficiency and the performance degradation caused by bank conflicts, yielding detailed profiling results. The results of experiments conducted on the RTX 3060 Mobile and RTX 4080 GPUs demonstrated significant performance improvements over conventional methods. Notably, the RTX 4080 GPU achieved a maximum throughput of 1532.42 Gbps in ARIA-CTR mode, clearly validating the effectiveness and practical applicability of the proposed optimization techniques. On the RTX 3060, the performance of 128-bit ARIA-CTR was improved by 2.34× compared to previous state-of-the-art implementations. Furthermore, for exhaustive key searches on the 128-bit ARIA block cipher, a throughput of 1365.84 Gbps was achieved on the RTX 4080 GPU.
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M., Siva Kumar, and Sanjeeva Rayudu T.C. "An Efficient VLSI Implementation of the SMS4 Cipher Using a Twisted BDD S-Box Architecture." Advancement and Research in Instrumentation Engineering 8, no. 1 (2025): 33–40. https://doi.org/10.5281/zenodo.15228942.
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<em>SMS4 is a 128-bit block cipher that plays a key role in the WAP1 standard, primarily used for securing data packets within wireless local area networks (WLANs). This study begins by analyzing multiple S-box circuit designs, ultimately identifying the twisted Binary Decision Diagram (BDD) with m-4 configuration as the most efficient in terms of speed. Building upon this finding, a high-speed VLSI implementation of the SMS4 cipher was developed using the twisted BDD S-box. The resulting design demonstrated maximum operating frequencies exceeding 200 MHz on SMIC 0.18 µm CMOS technology and 100 MHz on Chartered 0.35 µm CMOS technology.</em>
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Ramachandra, Bharathi, and Smitha Elsa Peter. "Secured authentication of radio-frequency identification system using PRESENT block cipher." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 5 (2023): 5462. http://dx.doi.org/10.11591/ijece.v13i5.pp5462-5471.
Full textAbstract:
<span lang="EN-US">The internet of things (IoT) is an emerging and robust technology to interconnect billions of objects or devices via the internet to communicate smartly. The radio frequency identification (RFID) system plays a significant role in IoT systems, providing most features like mutual establishment, key establishment, and data confidentiality. This manuscript designed secure authentication of IoT-based RFID systems using the light-weight PRESENT algorithm on the hardware platform. The PRESENT-256 block cipher is considered in this work, and it supports 64-bit data with a 256-key length. The PRESENT-80/128 cipher is also designed along with PRESENT-256 at electronic codebook (ECB) mode for Secured mutual authentication between RFID tag and reader for IoT applications. The secured authentication is established in two stages: Tag recognition from reader, mutual authentication between tag and reader using PRESENT-80/128/256 cipher modules. The complete secured authentication of IoT-based RFID system simulation results is verified using the chip-scope tool with field-programmable gate array (FPGA) results. The comparative results for PRESENT block cipher with existing PRESENT ciphers and other light-weight algorithms are analyzed with resource improvements. The proposed secured authentication work is compared with similar RFID-mutual authentication (MA) approaches with better chip area and frequency improvements.</span>
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Jiao, Lin, Yongqiang Li, and Yonglin Hao. "A Guess-And-Determine Attack On SNOW-V Stream Cipher." Computer Journal 63, no. 12 (2020): 1789–812. http://dx.doi.org/10.1093/comjnl/bxaa003.
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Abstract The 5G mobile communication system is coming with a main objective, known also as IMT-2020, that intends to increase the current data rates up to several gigabits per second. To meet an accompanying demand of the super high-speed encryption, EIA and EEA algorithms face some challenges. The 3GPP standardization organization expects to increase the security level to 256-bit key length, and the international cryptographic field responds actively in cipher designs and standard applications. SNOW-V is such a proposal offered by the SNOW family design team, with a revision of the SNOW 3G architecture in terms of linear feedback shift register (LFSR) and finite state machine (FSM), where the LFSR part is new and operates eight times the speed of the FSM, consisting of two shift registers and each feeding into the other, and the FSM increases to three 128-bit registers and employs two instances of full AES encryption round function for update. It takes a 128-bit IV, employs 896-bit internal state and produces 128-bit keystream blocks. The result is competitive in pure software environment, making use of both AES-NI and AVX acceleration instructions. Thus, the security evaluation of SNOW-V is essential and urgent, since there is scarcely any definite security bound for it. In this paper, we propose a byte-based guess-and-determine attack on SNOW-V with complexity $2^{406}$ using only seven keystream blocks. We first improve the heuristic guessing-path auto-searching algorithm based on dynamic programming by adding initial guessing set, which is iteratively modified by sieving out the unnecessary guessing variables, in order to correct the guessing path according to the cipher structure and finally launch smaller guessing basis. For the specific design, we split all the computing units into bytes and rewrite all the internal operations correspondingly. We establish a backward-clock linear equation system according to the circular construction of the LFSR part. Then we further simplify the equations to adapt to the input requirements of the heuristic guessing-path auto-searching algorithm. Finally, the derived guessing path needs modification for the pre-simplification and post-reduction. This is the first complete guess-and-determine attack on SNOW-V as well as the first specific security evaluation to the full cipher.
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Yousif, Intisar Abid. "Proposed A Permutation and Substitution Methods of Serpent Block Cipher." Ibn AL- Haitham Journal For Pure and Applied Science 32, no. 2 (2019): 131. http://dx.doi.org/10.30526/32.2.2120.
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Block cipher technique is one of cryptography techniques to encrypt data block by block. The Serpent is one of AES candidates. It encrypts a 128-bit block by using 32 rounds of a similar calculation utilizing permutations and substitutions. Since the permutations and substitutions of it are static. Then this paper proposes dynamic methods for permutation, substitution and key generation based on chaotic maps to get more security. The proposed methods are analyzed and the results showed that they were able to exceed the weakness resulting from the use of static permutations and substitutions boxes in the original algorithm and also can reduce number of rounds and time usage compared with a classical Serpent block cipher algorithm
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Seok, Byoungjin, and Changhoon Lee. "Fast implementations of ARX-based lightweight block ciphers (SPARX, CHAM) on 32-bit processor." International Journal of Distributed Sensor Networks 15, no. 9 (2019): 155014771987418. http://dx.doi.org/10.1177/1550147719874180.
Full textAbstract:
Recently, many lightweight block ciphers are proposed, such as PRESENT, SIMON, SPECK, Simeck, SPARX, GIFT, and CHAM. Most of these ciphers are designed with Addition–Rotation–Xor (ARX)-based structure for the resource-constrained environment because ARX operations can be implemented efficiently, especially in software. However, if the word size of a block cipher is smaller than the register size of the target device, it may process inefficiently in the aspect of memory usage. In this article, we present a fast implementation method for ARX-based block ciphers, named two-way operation. Moreover, also we applied SPARX-64/128 and CHAM-64/128 and estimated the performance in terms of execution time (cycles per byte) on a 32-bit Advanced RISC Machines processor. As a result, we achieved a large amount of improvement in execution time. The cycles of round function and key schedule are reduced by 53.31% and 31.51% for SPARX-64/128 and 41.22% and 19.40% for CHAM-64/128.
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Muhammad Erwanto, Sandi Fajar Rodiansyah, and Yudha Pradita Putra. "PENGAMANAN FILE DIGITAL MENGGUNAKAN METODE ALGORITMA KRIPTOGRAFI RIJNDAEL." Journal of Computation Science and Artificial Intelligence (JCSAI) 2, no. 1 (2025): 1–6. https://doi.org/10.58468/aabjbs17.
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Rijndael termasuk dalam jenis algoritma kriptografi yang sifatnya simetri dan cipher block. Dengan demikian algoritma ini mempergunakan kunci yang sama saat enkripsi dan dekripsi serta masukan dan keluarannya berupa blok dengan jumlah bit tertentu. Rijndael mendukung berbagai variasi ukuran blok dan kunci yang akan digunakan. Namun Rijndael mempunyai ukuran blok dan kunci yang tetap sebesar 128, 192, 256 bit. Pemilihan ukuran blok data dan kunci akan menentukan jumlah proses yang harus dilalui untuk proses enkripsi dan dekripsi. Blok-blok data masukan dan kunci dioperasikan dalam bentuk array. Setiap anggota array sebelum menghasilkan keluaran ciphertext dinamakan dengan state. Setiap state akan mengalami proses yang secara garis besar terdiri dari empat tahap yaitu, AddRoundKey, SubBytes, ShiftRows, dan MixColumns. ABSTRACT Rijndael, including the type of cryptographic algorithms that are symmetry and block cipher. Thus these algorithms use the same key when the encryption and decryption as well as inputs and outputs in the form of a block with a certain number of bits. Rijndael supports a wide variety of block sizes and key to be used. However Rijndael block size and the key has fixed at 128, 192, 256 bits. Selection of data block size and the key will determine the number of processes that must be passed to the encryption and decryption process. Blocks of data input and key operated in the form of an array. Each member of the array before generating the output ciphertext is called the state. Each state will undergo a process generally consists of four phases, namely, AddRoundKey, SubBytes, ShiftRows, and MixColumns.
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N, Bharatesh, and Rohith S. "FPGA Implementation of Park-Miller Algorithm to Generate Sequence of 32-Bit Pseudo Random Key for Encryption and Decryption of Plain Text." International Journal of Reconfigurable and Embedded Systems (IJRES) 2, no. 3 (2013): 99. http://dx.doi.org/10.11591/ijres.v2.i3.pp99-105.
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There are many problems arises in randomized algorithms whose solutions are fundamentally based on assumptions that pure random numbers exist, so pseudo-random number generators can imitate randomness sufficiently well for most applications. The proposed scheme is a FPGA implementation of Park-Miller Algorithm for generating sequence of Pseudo-Random keys. The properties like High speed, low power and flexibility of designed PRNG(Pseudo Random Number Generator) makes any digital circuit faster and smaller. The algorithm uses a PRNG Module, it contains 32-bit Booth Multiplier, 32-bit Floating point divider and a FSM module. After generating a sequence of 32-bit Pseudo-Random numbers we have used these numbers as a key to Encrypt 128-bit plain text to become a cipher text and by using the same key to decrypt the encrypted data to get original Plain text. The Programming is done in Verilog-HDL, successfully synthesized and implemented in XILINX Spartan 3E FPGA kit.
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M, Santhanalakshmi, Ms Lakshana K, and Ms Shahitya G M. "Enhanced AES-256 cipher round algorithm for IoT applications." Scientific Temper 14, no. 01 (2023): 184–90. http://dx.doi.org/10.58414/scientifictemper.2023.14.1.22.
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Objectives: Networks have become a significant mode of communication in recent years. As a result, internet security has become a critical requirement for secure information exchange. Cryptography is used to securely send passwords over large networks. Cryptographic algorithms are sequences of processes used to encipher and decipher messages in a cryptographic system. One of those is the Advanced Encryption Standard (AES), which is a standard for data encryption in hardware and software to hide sensitive and vital information. The main objective is to design an AES system with modifications by the addition of primitive operations which can withstand several attacks and is more efficient.Method: AES works with three different key lengths: 128-bit keys, 192- bit keys, and 256-bit keys. The early rounds of AES have a poor diffusion rate. Better diffusion properties can be brought about by putting in additional operations in the cipher round and key generation algorithm of the conventional AES.Findings: The diffusion characteristics of the conventional AES and the proposed methodology are compared using the avalanche effect. The proposed AES algorithm shows an increased avalanche effect, which proves it to be more secure than the conventional AES. The proposed algorithm is executed on Vivado 2016.2 ISE Design Suite and the results are targeted on Zybo–Zynq Z-7010 AP SoC development board.Novelty: In addition, this paper also proposes an improved AES algorithm that was accomplished by altering the sub-bytes operation. This change was made to make it more reliant on round keys. This algorithm was also extended to a higher key length of 256 bits which makes the algorithm less vulnerable to attacks.
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An, Chunyan, Wei Bai, and Donglei Zhang. "Meet-in-the-middle differential fault analysis on Midori." Electronic Research Archive 31, no. 11 (2023): 6820–32. http://dx.doi.org/10.3934/era.2023344.
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<abstract><p>Midori is a lightweight block cipher designed by Banik et al. and presented at the ASIACRYPT 2015 conference. According to the block size, it consists of two algorithms, denoted as Midori-64 and Midori-128. Midori generates 8-bit S-Boxes from 4-bit S-Boxes and applies almost MDS matrices instead of MDS matrices. In this paper, we introduce the meet-in-the-middle fault attack model in the 4-round cell-oriented fault propagation trail and reduce the key space in the last round by $ 2^{45.71} $ and $ 2^{39.86} $ for Midori-64 and Midori-128, respectively. For Midori-64, we reduce the time complexity from $ 2^{80} $ to $ 2^{28} $, $ 2^{32} $ and $ 2^{56} $ for the different single fault injection approaches. For Midori-128, we provide a 4-round fault attack method, which slightly increases the complexity compared to previous attacks. Our results indicate that the first and last four rounds of Midori must be protected to achieve its security.</p></abstract>
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Wade, Sahil. "Description of Image encryption Using AES-256 bits." International Journal for Research in Applied Science and Engineering Technology 11, no. 5 (2023): 7167–71. http://dx.doi.org/10.22214/ijraset.2023.53365.
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Abstract: Image Encryption using AES Algorithm is a technique to secure the confidentiality of images. One of the most popular and secure encryption algorithms is the AES (Advanced Encryption Standard) algorithm. It is a symmetric encryption algorithm that encrypts data using a 128-bit block cipher. In this process, the image is first converted into a binary format. Then, a random 128-bit key is generated, which is used to create a sequence of subkeys that will be used for each round of encryption. The binary image is then divided into 128-bit blocks, and the encryption algorithm is applied to each block using the subkeys generated earlier. This process ensures that the image is encrypted securely and is only accessible to those who have the key to decrypt it. One of the advantages of using AES is that it provides a high level of security, making it difficult for hackers to decrypt the encrypted data. Additionally, AES is a fast algorithm and can be implemented easily in hardware or software. The use of AES for image encryption ensures that the image is protected against unauthorized access and provides a secure way of transmitting sensitive images over the internet. Thus we can say that Image Encryption using AES Algorithm is a secure and efficient way to protect the confidentiality of images. It uses AES, a widely used encryption algorithm, to encrypt images securely, making it difficult for hackers to decrypt them without the key.
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Kwon, Hyeokdong, SangWoo An, YoungBeom Kim, et al. "Designing a CHAM Block Cipher on Low-End Microcontrollers for Internet of Things." Electronics 9, no. 9 (2020): 1548. http://dx.doi.org/10.3390/electronics9091548.
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As the technology of Internet of Things (IoT) evolves, abundant data is generated from sensor nodes and exchanged between them. For this reason, efficient encryption is required to keep data in secret. Since low-end IoT devices have limited computation power, it is difficult to operate expensive ciphers on them. Lightweight block ciphers reduce computation overheads, which are suitable for low-end IoT platforms. In this paper, we implemented the optimized CHAM block cipher in the counter mode of operation, on 8-bit AVR microcontrollers (i.e., representative sensor nodes). There are four new techniques applied. First, the execution time is drastically reduced, by skipping eight rounds through pre-calculation and look-up table access. Second, the encryption with a variable-key scenario is optimized with the on-the-fly table calculation. Third, the encryption in a parallel way makes multiple blocks computed in online for CHAM-64/128 case. Fourth, the state-of-art engineering technique is fully utilized in terms of the instruction level and register level. With these optimization methods, proposed optimized CHAM implementations for counter mode of operation outperformed the state-of-art implementations by 12.8%, 8.9%, and 9.6% for CHAM-64/128, CHAM-128/128, and CHAM-128/256, respectively.
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Ibrahim, Nahla, and Johnson Agbinya. "Design of a Lightweight Cryptographic Scheme for Resource-Constrained Internet of Things Devices." Applied Sciences 13, no. 7 (2023): 4398. http://dx.doi.org/10.3390/app13074398.
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We propose an ultra-lightweight cryptographic scheme called “Small Lightweight Cryptographic Algorithm (SLA)”. The SLA relies on substitution–permutation network (SPN). It utilizes 64-bit plaintext and supports a key length of 80/128-bits. The SLA cipher includes nonlinear layers, XOR operations, and round permutation layers. The S-box serves to introduce nonlinearity in the entire scheme design. It plays a vital role in increasing the complexity and robustness of the design. The S-box can thwart attacks such as linear and differential attacks. The scheme makes it possible to breed many active S-boxes in a short number of rounds, hindering analytical attacks on the cipher. When compared to other currently used ciphers, SLA has a higher throughput. Additionally, we demonstrate the SLA’s performance as an ultra-lightweight compact cipher, and its security analysis. The SLA cipher’s design is well suited for applications where small-scale embedded system dissipation is critical. The SLA algorithm is implemented using Python.
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Almukhlifi, Reham, and Poorvi L. Vora. "Linear Cryptanalysis of Reduced-Round Simeck Using Super Rounds." Cryptography 7, no. 1 (2023): 8. http://dx.doi.org/10.3390/cryptography7010008.
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The Simeck family of lightweight block ciphers was proposed by Yang et al. in 2015, which combines the design features of the NSA-designed block ciphers Simon and Speck. Previously, we proposed the use of linear cryptanalysis using super-rounds to increase the efficiency of implementing Matsui’s second algorithm and achieved good results on all variants of Simon. The improved linear attacks result from the observation that, after four rounds of encryption, one bit of the left half of the state of the cipher depends on only 17 key bits (19 key bits for the larger variants of the cipher). We were able to follow a similar approach, in all variants of Simeck, with an improvement in Simeck 32 and Simeck 48 by relaxing the previous constraint of a single active bit, using multiple active bits instead. In this paper we present improved linear attacks against all variants of Simeck: attacks on 19-rounds of Simeck 32/64, 28-rounds of Simeck 48/96, and 34-rounds of Simeck 64/128, often with the direct recovery of the full master key without repeating the attack over multiple rounds. We also verified the results of linear cryptanalysis on 8, 10, and 12 rounds for Simeck 32/64.
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Shajarin, S., P. Leelavathi, B. Reddaiah, G. Amrutha Vani, and C. Swetha. "Three Fish Algorithm: T-Mix Cipher using SHA-256." International Journal of Innovative Technology and Exploring Engineering 11, no. 10 (2022): 5–11. http://dx.doi.org/10.35940/ijitee.j9267.09111022.
Full textAbstract:
In every organization, use of online services is increasing. With this the sensitive data is carried over internet on daily basis. Hence, there is a chance of misleading the data by unauthorized parties. So, there is need to provide security for that data and cryptography is the science that helps in providing security. By using cryptography different types of security algorithms have been developed. Three fish is a symmetric-key and tweakable block cipher algorithm designed as a part of the skein hash function. The strength of three fish encryption relies on 128-bit tweak value. The proposed work focuses on strengthening Encryption Process by implementing tweak buffer along with input. Whereas key scheduling is secured by applying SHA-256 algorithm. SHA-256 is a secured hash function which belongs to SHA-2 family. Three Fish is used in providing security on software and hardware. It is also implemented in electronic media such as transactions like banking.
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S., Shajarin, Leelavathi P., Reddaiah B., Amrutha Vani G., and Swetha C. "Three Fish Algorithm: T-Mix Cipher using SHA-256." International Journal of Innovative Technology and Exploring Engineering (IJITEE) 11, no. 10 (2022): 5–11. https://doi.org/10.5281/zenodo.8082529.
Full textAbstract:
<strong>Abstract</strong>: In every organization, use of online services is increasing. With this the sensitive data is carried over internet on daily basis. Hence, there is a chance of misleading the data by unauthorized parties. So, there is need to provide security for that data and cryptography is the science that helps in providing security. By using cryptography ddifferent types of security algorithms have been developed. Three fish is a symmetric-key and tweakable block cipher algorithm designed as a part of the skein hash function. The strength of three fish encryption relies on 128-bit tweak value. The proposed work focuses on strengthening Encryption Process by implementing tweak buffer along with input. Whereas key scheduling is secured by applying SHA-256 algorithm. SHA-256 is a secured hash function which belongs to SHA-2 family. Three Fish is used in providing security on software and hardware. It is also implemented in electronic media such as transactions like banking.
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Shi, Jiali, Guoqiang Liu, and Chao Li. "SAT-Based Security Evaluation for WARP against Linear Cryptanalysis." IET Information Security 2023 (December 6, 2023): 1–14. http://dx.doi.org/10.1049/2023/5323380.
Full textAbstract:
WARP, an efficient lightweight block cipher presented by Banik et al., offers a viable alternative to AES with its 128-bit block and a 128-bit key. It adopts a 32-nibble type-II generalized Feistel network (GFN) structure, incorporating a nibble permutation optimized for both security and efficiency. Notably, WARP has achieved the lowest hardware implementation among 128-bit block ciphers. Its bit-serial encryption-only circuit is only 763 gate equivalents (GEs). Consequently, WARP has received significant attention since its inception. The designers evaluated the number of active Sboxes for linear trails in WARP to establish its security. To further investigate WARP’s resistance against linear attacks, we employed an automated model to analyze the optimal linear trails/hulls of WARP. To achieve this, the problem will be transformed into a Boolean satisfiability problem (SAT). The constraints in conjunctive normal form (CNF) are used to describe the mask propagation of WARP and invoke the SAT solver to find valid solutions. The results allowed us to obtain the optimal correlation of the initial 21-round linear trails for WARP. Furthermore, by enumerating the linear trails within a linear hull, the distribution of linear trails is revealed, and the probability of the linear hull is improved to be more accurate. This work extends the linear distinguisher from 18 to 21 rounds. Additionally, the first independent analysis of WARP’s linear properties is presented, offering a more precise evaluation of its resistance against linear cryptanalysis.
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Shivangi, Wadehra, Goel Shivam, and Sengar Nidhi. "AES Algorithm Encryption and Decryption." International Journal of Trend in Scientific Research and Development 2, no. 3 (2019): 1075–77. https://doi.org/10.31142/ijtsrd11221.
Full textAbstract:
Advanced Encryption Standard AES algorithm is one of the most common and widely used symmetric block cipher algorithm. This algorithm has its own particular structure to encrypt and decrypt sensitive data and is applied in hardware and software, all over the world. It is extremely difficult for hackers to get the real data when encrypting by AES algorithm. In AES algorithm, encryption and decryption involves a number of rounds that depends on the length of the key and the number of block columns. So, to improve the strength of the AES the number of rounds is increased. Till date there is not any evidence to crack this algorithm. AES has the ability to deal with three different key sizes such as AES 128, 192 and 256 bit and each of this ciphers has 128 bit block size. This paper will provide an overview of AES algorithm and explain several crucial features of this algorithm in detail. Shivangi Wadehra | Shivam Goel | Nidhi Sengar "AES Algorithm: Encryption and Decryption" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-3 , April 2018, URL: https://www.ijtsrd.com/papers/ijtsrd11221.pdf