Dissertations / Theses on the topic 'Ring Oscillator Design'

Clock multipliers are among the most critical elements in high speed digital circuits. Power consumption, area, jitter and wide tuning range are key design metrics in these circuits. To provide a wide range of clock frequencies, Digitally Controlled Ring Oscillators (DCROs), whose frequencies are discretely tuned using a Frequency Code Word (FCW), have been investigated in recent studies. They have several advantages over LC-based Voltage Controlled Oscillators (VCO) including simplicity of design, small die area (i.e. no large inductors), better compatibility with deep submicron CMOS processes,ability to offer multiple output phases, and wider tuning range.A compact differential Injection Locked Clock Multiplier (ILCM) based on an injection locked DCRO is implemented in this thesis. As the transistor features continuously shrink and the supply voltage is reduced, ILCMs are becoming more prone to issues such as increased effect of random mismatch, increased device noise, susceptibility of the design to noise coupling and vulnerability to Process Voltage and Temperature (PVT) variations. Furthermore, ILCMs in recent System on a Chip (SoCs) have stringent design requirements including accurate frequency tuning, fine fractional resolution, high levels of integration and better amenability to technology scaling. In the proposed ILCM, multiple techniques were used to address deep submicron CMOS design challenges, as well as modern applications’ requirements. The design is fully digital, synthesizable and automatically placed and routed. All circuit blocks were implemented using digital design flow and designed using a Hardware Description Language (HDL). This allows the design to be more easily ported to deep submicron processes. Online or offline PVT calibration can be performed using a replica oscillator and high speed digital counters to track frequency drifts with PVT variations. A DCRO based on a matrix structure has been utilized to reduce period variations due to random mismatch. The DCRO is built up from pseudo differential delay cells to enhance design immunity to noise coupling. The key thesis contributions are implementing a new DCRO structure using fully syntheziable differential structure, utilizing a novel PVT calibrator that can compensate for frequency mismatch between the main DCRO and its replica, and using a low complexity fractional ILCM technique that achieves a fine fractional resolution with few number of ring oscillator stages.Designed in a TSMC 65 nm GP CMOS process with no analog or RF enhancements, the proposed ILCM frequency ranges from 1.0 to 1.8 GHz and occupies 124:5 m 170 m of chip area. The ILCM can operate in integer or fractional mode for multiplication ratios up to 9. At 1.7 GHz and 1.1 V, the measured integrated RMS jitter (1 kHz to 30 MHz) for the 3rd and 9th multiplication factors are 197 fs and 381 fs, respectively. The ILCM consumes 13.25 mW of power and has a fraction resolution of fref=32. Furthermore, it achieves a jitter-power FOM of −241 dB, when measured at room temperature and 1.1 V. When tested in the presence of switching noise, it provides up to 7 dB improvement in phase noise when compared to a single ended version of the ILCM. In the presence of voltage variations (from 0.9 V to 1.1 V) and temperature variations (from 30 C to 70 C), the maximum integrated RMS jitter variation observed was 50 fs.

Multiple research projects are proposed that utilize low-level knowledge of Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) design processes to enable additional research avenues. In order to accomplish these projects, Tools for Open Reconfigurable Computing (TORC) is utilized to provide a robust environment for circuit analysis and modifications. These projects rely on looking at the low-level constructs of the internals of these microchips. Through this knowledge, techniques for performing supply chain evaluations are proposed utilizing a non-binary comparison of multiple characteristic vectors between different FPGA manufacturing lots, and FPGAs that have been exposed to different environmental conditions. Second, techniques are proposed that look at design recovery by performing fuzzy segmentation and fuzzy matching algorithms to a problem area that has traditionally focused on exact graph sub-isomorphism solutions. Through these projects, additional research vectors are opened to protect and analyze the engineering efforts that are exerted in the design of FPGA and ASIC projects.
Ph. D.

La sensibilité accrue aux variations des procedés de fabrication, de tension, de température et de vieillissement (PVTA) dans les nœuds technologiques avancés d'integration est responsable d'une dégradation significative des spécifications des circuits integrés lors de la fabrication à grand volume. Celle-ci est devenue une préoccupation croissante dans la conception de circuits numériques, qui doit faire face aux exigences de plus en plus strictes des applications modernes en termes d'efficacité énergétique, de fiabilité et de sécurité. Dans ce travail de thèse, les techniques de surveillance de timing intégrée et de compensation sont explorées pour répondre efficacement à ces exigences contradictoires. Dans ce travail de thèse, les techniques proposées ont été étudiés séparément puis combinées dans 3 démonstrateurs SoC numériques fabriqués en technologie 28nm FD-SOI CMOS, dont l'un a été mesuré au moment de la rédaction de ce manuscrit.La surveillance de timing intégrée est proposée comme solution de conception pour permettre la compensation des variations PVTA, la surveillance de la sécurité en operation et la protection contre les attaques hardware en timing. Les moniteurs de timing de l'état de l'art ont été évalués dans la perspective d'une intégration dans des produits industriels, ce qui privilégie des caractéristiques telles que la reusabilité et les faibles coûts d'intégration. Les avantages identifiés de la surveillance de timing de registre à registre ont conduit à la mise en œuvre d'un circuit témoin reconfigurable (Tunable Replica Circuit en langue anglaise) avec une sensibilité de 3 mV/bit en 28nm FD-SOI CMOS, qui démontre un suivi rapide et précis des variations PVTA d'un SoC basé sur un ARM Cortex-R4F à travers des corners lent / typique / rapide, une plage de tension 0.5/1.2 V, une gamme de temperature -40/150°C, et de vieillissement jusqu'a fin de vie. Enfin, ce travail propose un nouveau moniteur de timing qui permet de surmonter les faiblesses des solutions existantes, en obtenant simultanément la reutilisabilité élevée et la large plage de surveillance des oscillateurs en anneau et l'acquisition rapide et précise des circuits témoins reconfigurables.L'exploration des techniques d'adaptation et de compensation commence par la détermination de leur champ d'application dans les produits industriels: l'amélioration des pires cas qui définissent les limites de spécifications du produit lors de la fabrication à grand volume. Dans cette perspective, la région d'application optimale des techniques de voltage scaling et de body biasing a été déterminée et leur impact sur les pires cas des SoC numériques a été évalué. Enfin, ces travaux montrent comment la surconsommation induite par l'application séparée de voltage scaling ou body biasing peut être atténuée par la combinaison des deux, en particulier dans les circuits avec une variété de points de performance opérationnelle (OPPs).Les avantages des techniques proposées ont été démontrés dans un SoC numérique qui optimise son énergie à travers d'une largeur de fréquence de 11X en combinant le voltage scaling adaptatif, body biasing adaptatif et le bias-in-memory-array avec un tunable replica circuit pour la sécurité, la régulation de puissance intégrée et la compensation. Grâce à l'application de ces techniques, le circuit proposé permet de surmonter les limites précédemment signalées et démontre une amélioration des performances de 21X, une Vmin inférieure de 120 mV et une durée de vie de 8X, pour les OPP de faible puissance, de moyenne et de haute performance respectivement.Les études présentées ici ont été incluses dans plusieurs chapitres d'un livre scientifique qui sera publié cette année. En outre, elles ont contribué à une nouvelle plateforme de technologie et de conception. Enfin, 3 publications dans des conférences de l'IEEE et 3 demandes de brevet ont résulté de ce travail de thèse
The increased sensitivity to Process, Voltage, Temperature, and Aging (PVTA) variations in scaled integrated circuits' technology nodes is responsible for a significant degradation in the products' specifications during high volume manufacturing. This has become a growing concern in digital circuit design, which has to cope with the increasingly stringent requirements of modern applications in terms of energy efficiency, reliability, and safety. In this thesis work, embedded timing monitoring and compensation techniques are explored to efficiently address these conflicting requirements. The proposed techniques are studied separately and then combined in 3 digital SoC demonstrators manufactured in 28nm FD-SOI CMOS technology, one of which has been measured at the time of this manuscript's writing.Embedded timing monitoring is proposed as a design solution to enable PVTA compensation, in-field safety monitoring and security protection against hardware timing attacks. The state-of-the-art timing monitors are evaluated from the perspective of an integration into industrial products, emphasizing features such as high reusability and low integration costs. The identified advantages of register-to-register timing monitoring have led to the implementation of a 3mV/bit tunable replica circuit in 28nm FD-SOI CMOS, which demonstrates a fast and accurate PVTA tracking of an ARM Cortex-R4F based SoC across slow/typical/fast process, 0.5/1.2V, -40/150ºC, and End Of Life (EOL) aging. Finally, this work proposes a novel timing monitor that overcomes the weaknesses of existing solutions, simultaneously achieving the high reusability and wide monitoring range of ring oscillators and the fast and accurate timing acquisition of tunable replica circuits.The exploration of adaptive and compensation techniques begins with the determination of their application scope in industrial designs: the improvement of the worst-case limiting corners that set the product's specifications during high volume manufacturing. Following this perspective, the optimal region of application of voltage scaling and body biasing techniques has been determined and their impact on the worst-case specifications of digital SoCs has been assessed. Finally, this work demonstrates how the power overhead induced by the separate application of voltage scaling or body biasing can be mitigated through the combination of both, specially in circuits with a variety of Operational Performance Points (OPPs).The benefits of the proposed techniques have been demonstrated in a digital SoC that optimizes its energy across 11X frequency-wide OPPs by combining adaptive voltage scaling, adaptive body biasing, and bias-in-memory-array with a tunable replica circuit for safety, embedded power regulation and compensation. Through the application of these techniques the proposed design overcomes previously reported limitations and demonstrates an improvement by 21X performance, 120mV lower Vmin, and 8X lifetime, the low-power, mid-, and high-performance OPPs respectively.The studies reported here have been included in several chapters of a scientific book to be published this year. Furthermore, they have contributed to a new technology and design platform. Finally, 3 IEEE conference publications and 3 patent applications have resulted from this thesis' work

The temperature sensor design discussed in this thesis, is meant mainly to monitor temperature at power outlets. Current variations in power cords have a direct impact on the surrounding temperature. Sensing these variations ,enables us to take necessary measures to prevent any hazards due to temperature rise. Thus, for this application we require a sensor with a moderate temperature error (_10C) over a sensing range of -200C to 1500C. Low power consumption and simple digitizing scheme alleviate measurement errors due to self heating effects of the sensor. A current starved inverter based ring oscillator was chosen for the sensor design in 130nm technology. The inverter delay variation with temperature is used for sensing. Linearity and process invariancy of these characteristics are fundamental to the sensor design. We observed through simulations, and confirmed by mathematical analysis, that the sensing characteristics are governed by bias current dependence on temperature. Control voltage for the bias circuitry of the oscillator determines current through the inverter stages. Hence, for linear sensing characteristics, a control voltage(Vc) just above the maximum threshold voltage of bias transistor is used. This enables generation of PTAT saturation current for current starved inverters, due to dominance of threshold voltage decrease with temperature over mobility decrease. I.Another limitation, process dependency of the sensing characteristics, was overcome through the proposed calibration based compensation technique. A changing Vc proportional to threshold voltage variation with process, process independent bias current and current temperature characteristics were obtained. This compensated for the process variation effects on frequency. Thus, a variable Vc was generated using a reference with low temperature sensitivity of 17.6_V=0C, and resistive divider combinations for various processes. Incorporating this compensation technique we achieved good linearity in sensor characteristics and a maximum temperature error of± 1.60C over the sensing range. The sensor consumes a low power of 0.29mW and also occupies minimal area.

The temperature sensor design discussed in this thesis, is meant mainly to monitor temperature at power outlets. Current variations in power cords have a direct impact on the surrounding temperature. Sensing these variations ,enables us to take necessary measures to prevent any hazards due to temperature rise. Thus, for this application we require a sensor with a moderate temperature error (_10C) over a sensing range of -200C to 1500C. Low power consumption and simple digitizing scheme alleviate measurement errors due to self heating effects of the sensor. A current starved inverter based ring oscillator was chosen for the sensor design in 130nm technology. The inverter delay variation with temperature is used for sensing. Linearity and process invariancy of these characteristics are fundamental to the sensor design. We observed through simulations, and confirmed by mathematical analysis, that the sensing characteristics are governed by bias current dependence on temperature. Control voltage for the bias circuitry of the oscillator determines current through the inverter stages. Hence, for linear sensing characteristics, a control voltage(Vc) just above the maximum threshold voltage of bias transistor is used. This enables generation of PTAT saturation current for current starved inverters, due to dominance of threshold voltage decrease with temperature over mobility decrease. I.Another limitation, process dependency of the sensing characteristics, was overcome through the proposed calibration based compensation technique. A changing Vc proportional to threshold voltage variation with process, process independent bias current and current temperature characteristics were obtained. This compensated for the process variation effects on frequency. Thus, a variable Vc was generated using a reference with low temperature sensitivity of 17.6_V=0C, and resistive divider combinations for various processes. Incorporating this compensation technique we achieved good linearity in sensor characteristics and a maximum temperature error of± 1.60C over the sensing range. The sensor consumes a low power of 0.29mW and also occupies minimal area.

碩士
國立勤益科技大學
電子工程系
107
The voltage controlled ring oscillator (VCRO) is widely used in low-power portable electronic systems due to its simplicity. In this thesis, two low power VCROs with 5GHz frequency are proposed for portable electronic applications. The circuit designs are performed based on TSMC 1P6M 0.18μm standard process technology with supply voltage 1.8V. The objective is to fetch smaller layout area and reduced fabrication cost, but to keep its superiority. Simulation results show that the proposed VCRO designs as compared to existing current staved VCRO, the number of transistors is reduced. The layout area of the proposed Type-I VCRO circuit has reduced by 12.4%, and that of Type-II circuit has 38.2% reduced. In fact, the proposed two VCROs suggest higher oscillating frequency with 5 G Hz, however dissipate lower power consumption. Therefore, the two proposed VCROs are superior to other references, and they are practical and feasible for low-power portable electronic applications.

碩士
雲林科技大學
電子與資訊工程研究所
96
This paper presents the design of RF CMOS ring oscillator. It adopts dual-differential delay cell of the three-stage ring oscillator. The internal structure uses dual-differential delay cell. The negative skewed delay path is directly connected to the output of the same stage, and utilizes dual-delay path techniques to obtain a wide tuning range. Voltage controlled ring oscillator is fabricated in a TSMC 0.35 Mixed-Signal 2P4M CMOS technology. After layout the controlled voltage is 1.2V~3.3V, resulting in oscillation frequency ranges of 2.15GHz~0.957GHz, and the tuning range is approximately 75.6%. The power dissipation is 71.33mW~101mW.After layout the phase noise is -100.12dBc/Hz at a 1MHz offset from a 1.53GHz center frequency.

碩士
國立勤益科技大學
電子工程系
103
In this paper, a CMOS differential voltage controlled ring oscillator (DVCRO) is proposed for wireless energy transmission application. Based on TSMC CMOS 0.18um standard process technology with supply voltage 1.8V, the proposed DVCRO has phase noise -94.37 dBc/Hz with 1 MHz offset frequency. Its oscillation frequency ranges from 0.72GHz to 1.02GHz as the control voltage changing from 0.6 to 1.8 V. Compared with five previous works, the proposed DVCRO has better performance including robust sinusoid output waveform, and lower power consumption ranging from 1.6mW to 1.74mW, approximately 4/5 of the referenced works compared with the best one, and figure of merit (FOM) is -151.18 dBc/Hz.

碩士
國立虎尾科技大學
光電與材料科技研究所
98
A ring oscillator, which uses digital codes to control the transmission paths, has been proposed in this thesis. As the transmission paths changes, different output frequencies are generated. Moreover, a current-adjusted inverter is used as the last output stage. Therefore the output frequency can be further calibrated. Comparing to the conventional oscillators, the proposed one can have multiple output frequencies. The proposed digital-code-controlled ring oscillator has been simulated with HSpice where 0.35μm mixed-signal 2P4M polycide 3.3/5V fabricated parameters have been adopted. Simulation results show that, 32 different output frequencies can be obtained. The maximum frequency is 1.05GHz and the minimum frequency is 188.4MHz. As the supply voltage is 3.3 V and the load capacitance is 20 pF, the maximum power consumption is 402.52 mW. Since the oscillator can generate different output frequencies, the low output frequency needs less number of stages of cascaded buffers while the high output frequency needs more. If both the low output frequency and the high output frequency use same stages of cascaded buffers, it will bring extra power consumptions at low output frequency. In this thesis, an adaptive stage cascaded buffer has been proposed. In order to reduce additional power dissipation, the stages of cascaded buffers will be adjusted according to the output frequency. In the proposed circuit, as the input signal frequency varies from 1MHz to 100MHz, the corresponding stage of output buffer can be increased from 1 to 3. The proposed adaptive cascaded buffer has been simulated with HSpice where 0.35μm mixed-signal 2P4M polycide 3.3/5V fabricated parameters have been adopted. As the supply voltage is 3.3V, load capacitance is 15pF, and the input signal frequency is from 1MHz to 100MHz. The post-layout simulation results show that, the power consumption of the proposed circuit can reduce 110.22mW and 105.93mW, respectively, as compared to the conventional buffer.

碩士
明新科技大學
電子工程研究所
100
Periodic dielectric waveguide (PDWG) is a new concept of photonic waveguide in recent years. The main structure of PDWGs is a periodic distribution of dielectric poles. PDWGs propagate lightwave just need one row of dielectric poles so they do not occupy a large area. In addition, PDWGs can achieve low loss of energy propagation in any bending angle. First, we introduce the properties and analysis methods of PDWGs. Then, we design a bend waveguide with PDWGs and explore the propagation of light wave with different bending angles. In this study, we want to design the ring oscillator with PDWGs. There are many structure parameters so we explore the influence of different structure parameters and characteristic relations between them. After that the information can be used to design the ring oscillator. Then, the coupling efficiency of ring oscillator is simulated by finite-difference time-domain (FDTD) method in wavelength range of the usage of communication. Finally, characteristics are compared with the ring oscillator which is designed by conventional waveguides.

碩士
華梵大學
機電工程研究所
88
This paper describes a new voltage-controlled oscillator(VCO) structure based on a ring oscillator. We use five inter-locking ring oscillators to increase the Q value of the VCO. According to simulations, we notice that the phase noise of this new ring oscillator structure is better than the conventional one。 For the purpose of measurement, we design a PLL chip including the new VCO. The PLL circuit has five components, which are the VCO, the phase-frequency detector, the charge pump, the loop filter, and the frequency divider.The loop filter is designed outside the chip, so we can change the loop filter elements easily. This chip will be fabricated in TSMC 1p3m 0.6 m process. Simulation shows that the VCO operates at about 800MHz~1GHz with 2.5V power supply and consumes 21mW power. The PLL lock time is about 10 s, 3dB bandwidth is about 330kHz, and the total power consumpation is about 75mW.

Ring oscillators provide a central role in timing circuits for today?s mobile devices and desktop computers. Increased integration in these devices exacerbates switching noise on the supply, necessitating improved supply resilience. Furthermore, reduced voltage headroom in submicron technologies limits the number of stacked transistors available in a delay cell. Hence, conventional single-loop oscillators offer relatively few design options to achieve desired specifications, such as supply rejection. Existing state-of-the-art supply-rejection- enhancement methods include actively regulating the supply with an LDO, employing a fully differential or current-starved delay cell, using a hi-Z voltage-to-current converter, or compensating/calibrating the delay cell. Multiloop ring oscillators (MROs) offer an additional solution because by employing a more complex ring-connection structure and associated delay cell, the designer obtains an additional degree of freedom to meet the desired specifications. Designing these more complex multiloop structures to start reliably and achieve the desired performance requires a systematic analysis procedure, which we attack on two fronts: (1) a generalized delay-cell viewpoint of the MRO structure to assist in both analysis and circuit layout, and (2) a survey of phase-noise analysis to provide a bank of methods to analyze MRO phase noise. We distill the salient phase-noise-analysis concepts/key equations previously developed to facilitate MRO and other non-conventional oscillator analysis. Furthermore, our proposed analysis framework demonstrates that all these methods boil down to obtaining three things: (1) noise modulation function (NMF), (2) noise transfer function (NTF), and (3) current-controlled-oscillator gain (KICO). As a case study, we detail the design, analysis, and measurement of a proposed multiloop ring oscillator structure that provides improved power-supply isolation (more than 20dB increase in supply rejection over a conventional-oscillator control case fabricated on the same test chip). Applying our general multi-loop-oscillator framework to this proposed MRO circuit leads both to design-oriented expressions for the oscillation frequency and supply rejection as well as to an efficient layout technique facilitating cross-coupling for improved quadrature accuracy and systematic, substantially simplified layout effort.

碩士
國立臺灣科技大學
電子工程系
99
This thesis presents the analysis, design and simulation of two wide tuning voltage range ring oscillators. The proposed VCOs are designed and simulated in TSMC 0.18-?慆 CMOS process technology under 1.8 V power supply. The VCOs architectures this thesis proposed are targeted to operate at 4 GHz with a tuning voltage range from 0 V to 1.8 V. They have lower frequency-to-voltage ratios (Kvco), 0.22 GHz/V and 0.94 GHz/V, respectively. Comparing to other voltage controlled oscillators, this study demonstrates the advantages of wide voltage tuning range and small chip area. The voltage controlled oscillators are designed for applications needing the high operation frequency and wide voltage controlled requirements.

碩士
中原大學
電子工程研究所
99
Nowadays, the communication system was a rapidly developed technology. At the architecture of transceiver and receiver, we need a precise and stable oscillated signal to mix with the radio frequency signal. Thus, the voltage controlled ring oscillator used to produce the local oscillated signal played an important role. This paper presented an analysis on a voltage controlled ring oscillator with dual delay paths with symmetric load、negative skewed delay and PMOS cross coupled pair. The circuit was a three-stage differential ring oscillator, with symmetric load as a variable resistor to improve the linearity of circuit will reduce the noise from power supply. This circuit using negative skewed delay to accelerated the oscillation frequency, at the chapter of analysis will prove it with the equation of oscillation frequency. The VCRO was implemented using a TSMC 0.18 μm RF-CMOS process. All devices in this circuit was 33 RF-MOS transistor, 24 of them were RF-PMOS and rest of them were RF-NOMS. Measurement results demonstrate that the VCRO achieves a frequency tuning range of 2.77 GHZ to 4.55 GHz, the frequency tuning percentage was 49%. The measured phase noise at 1 MHz offset from the carrier frequency 4.55 GHz is -96 dBc/Hz. The VCRO occupies an active area of 0.048 mm2 and consumes 50.76mW for 4.55 GHz carrier frequency from a 1.8 V power supply.

This thesis introduces a multipass loop voltage controlled ring oscillator. The proposed structure uses cross-coupled PMOS transistors and replica bias with coarse/fine control signal. The design implemented in TSMC 90 nm CMOS technology, 0.9V power supply with frequency tuning range 481MHz to 4.08GHz and -94.17dBc/Hz at 1MHz offset from 4.08GHz with 26.15mW power consumption.

Phase locked loops (PLLs) used to generate high precision clocks are integral components in the majority of modern day electronic systems such as Analog-to-Digital Converters (ADC), Digital-to-Analog Converters (DAC), transceivers, processors, etc. The accuracy of this clocks that effects the overall performance of the system is measured in terms of its jitter, phase noise, spurious tones, etc. For example, the jitter in an ADC sampling clock can result in uncertainty of the sampling instant and can result in degradation of the effective number of bits (ENOB) of the ADC, phase noise on the other hand can result in reciprocal mixing in receivers and leakage into adjacent channels in transmitters. Therefore it is very desirable to design PLLs that generate clean clocks with minimal area and power consumption. This thesis discusses two PLL prototypes in 65nm CMOS technology. The first prototype demonstrates a sub-sampling phase detector (SSPD) based feed-forward noise cancellation (FFNC) scheme in a Type-II ring oscillator (RO) PLL. The FFNC technique uses the already available noise information at the SSPD output and cancels it from the PLL output. The proposed FFNC achieves a 1.4x reduction in jitter, 19.5dB power supply induced noise suppression at the PLL output while consuming a small area of 0.022mm2. The second prototype demonstrates a Type-I SSPD based RO PLL. The SSPD sample-and-hold action generates a steady-state voltage to tune the VCO directly. This eliminates the issue of high reference spurs generally associated with a Type-I PLL. Also the Type-I PLL occupies a very low area of 0.008mm2 as it avoids the usage of bulky integrating capacitor generally used in a Type-II PLL. The PLL with 2.4GHz output achieves a phase noise of -122.6dBc/Hz at a 1MHz offset and the power consumption is 6.1mW. It achieves reference spurs of -64.2dBc, RMSjitter of 422fs and FoMjitter of -239.7dB. In addition to the two prototypes, a theoretical discussion on an auxiliary FFNC (AFFNC) cancellation scheme that can work with a generic Type-II RO PLL is also included. The AFFNC technique uses a stand alone SSPD to extract and cancel noise from the VCO output. The SSPD is embedded into an alignment loop for proper noise extraction and cancellation. Along with AFFNC, which uses one reference edge for noise extraction, a Double Sampled AFFNC (DS-AFFNC) which utilizes both the rising and falling edge of the reference for noise extraction is also included. By using both the reference edges, higher cancellation BW is achieved.

碩士
國立彰化師範大學
工業教育學系
89
The demand for more available channels in mobile communication applications has imposed more strict requirements on the phase noise of local oscillators, which brings the importance on the predictions and measurements of phase noise for years. There are many phase noise models of VCO’s that have been proposed. Those are the Lesson’s model, the Hajimiri’s model and the Razavi’s model, etc. However no model including the temperature parameter has been considered. Due to the higher integration density and power dissipation of integrated circuits, the effects of temperature deviation that degrades the performance of VCO’s have become more important. This brings the need for the study of the phase noise model for the temperature stable VCO’s. In this thesis, the phase noise model has been derived based on the technique of an impulse sensitive function (ISF) and some experimental simulations. A new procedure and expression of phase noise estimation is thus proposed. The most important improvement is that the tedious and time consuming simulation for phase noise spectrum can be replaced by an efficient model. The average and standard deviation of the errors between prediction and simulation is 4.32﹪and 7.72﹪, respectively.

In this work, an improved Current-Mode-Logic-based (CML) ring oscillator is designed for use in an on-chip Vernier-based Time-to-Digital Converter (TDC) that could be used to measure timing specifications of high-speed signals, such as period and jitter, in the picoseconds range. The oscillator is designed with two tuning mechanisms to achieve coarse and fine tuning resolutions. The period of the oscillator can either be tuned from 0.5% to 10% or from 0.05% to 2.5% of the oscillator zero-resolution period (550 MHz) during coarse and fine resolutions of operation, respectively. A detailed study and characterization of the impact of the oscillator period variations when it is switched ON (start-up transient) and when the oscillator period is switched from one resolution to another (switching transient) on a Vernier oscillator-based TDC time interval is presented. The impact of oscillator period deviations in steady state and externally introduced random noise on the TDC performance is also shown analytically. A metric to characterize the effects of these transients and jitter on the time interval measurement is derived to benchmark the performance of the ring oscillator. This metric can be used to evaluate performance of any oscillators for its stability. Simulation results from the optimized ring oscillator show that the effects of the start-up transient become negligible after four clock cycles and that of the effects of switching transient become negligible instantaneously. Simulation also shows that the oscillator can achieve a stable steady state period, down to less than 0.5fs, which is the simulator precision. In reality, the oscillator will contain some random jitter due to external noise. This kind of jitter can be eliminated through averaging. Simulations also show that the oscillator could be fine tuned to a resolution of under one picosecond. A Vernier oscillator-based TDC using the modified oscillator was designed and simulated with input timing noise to demonstrate the stability of the ring oscillator and its robustness in TDC applications. Results show that two of these oscillators could be used in such a TDC design to measure timings in the range of picoseconds with the maximum error bound by the fine resolution of the oscillator.
Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate

Thesis (M.S.)--University of Tennessee, Knoxville, 2003.
Title from title page screen (viewed Sept. 16, 2003). Thesis advisor: Syed K. Islam. Document formatted into pages (viii, 105 p. : ill.). Vita. Includes bibliographical references (p. 86-90).

碩士
中原大學
電子工程研究所
95
This thesis presents a Voltage-Controlled Ring Oscillator (VCO) with third-order harmonic cancellation technique for low-band Ultra-Wideband (UWB) system. The VCO consists of three-stage delay cells and an adder load. Use the adder to add the two output signals that have phase delay 60 degrees from ring-oscillator. Then that can effective to make oscillator output signal third harmonic suppress ratio lower than -40dBc. In order to produce the more pure output signal and make it while inputting to Polyphase Filter it is phase error exported can drop by a wide margin . The simulation result shows the operating frequency range from 3924MHz to 4534MHz, center frequency at 4224MHz, and tuning range is 0V ~ 1.8V. The output power is -10.44dBm, the gain of vco(Kvco) is 339MHz/V. The simulated third harmonic rejection is - 43dBc at 4224MHz, phase noise is - 101 dBc/Hz @ 5MHz offset. The power consumption is 11.93 ~ 13.12 mW at 1.8V supply voltage in a 0.18um standard RF CMOS process.

碩士
國立臺灣科技大學
電子工程系
102
The important blocks in the phase locked loop (PLL) are the voltage controlled oscillator (VCO) and the divider circuit. The most power consumption of PLL consumes in VCO and divider. The VCO is requested a low phase-noise to avoid corrupting the mixer-converted signal by close interfering tones for VCO circuit, and the Figure of Merit (FOM) of VCO can be determined by it’s performance. Firstly, this thesis designs complementary Colpitts voltage controlled oscillator, A 0.7GHz Colpitts oscillator is designed and implemented in a 0.18μm CMOS 1P6M process. It consists of a Colpitts negative resistance cell and an open square loop resonator. At the supply voltage of 1.8 V, the output phase noise of the oscillator is -86.28 dBc/Hz at 1MHz offset frequency from the carrier frequency of 0.7 GHz(Using in UHF Band). The FOM(figure of merit) is -135.57dBc/Hz. Total oscillator core power consumption is 5.76 mW. Secondly, a new wide locking range divide-by-3 injection-locked frequency divider (ILFD) using a standard 0.18 μm BiCMOS process is presented. The ILFD uses a cross-coupled nMOSFET oscillator with an HBT tail and it also use two HBT injection SiGe HBTs. The injection HBTs serve as harmonic and nonlinear mixers. The core power consumption of the ILFD core is 8.328 mW. The divider’s free-running frequency is tunable from 4.32 to 3.78 GHz by tuning the varactor’s control bias, and at the incident power of 0 dBm. The maximum locking range is 1.87 GHz (23.71%), The incident frequency from 6.95 to 8.82 GHz. The operation range is 2.85 GHz (36.42%), from 6.4 to 9.25 GHz. In addition, the ILFD uses a cross-coupled nMOSFET oscillator with an HBT tail and it also use two HBT injection SiGe HBTs. The effect of hot-carrier stressed injection HBTs on the performance of the ILFD is studied. The stress induces the shift in oscillation frequency, phase noise and HBT output characteristics. It is found the locking range decreases with stress time at fixed dc injection base-emitter bias. Thirdly , a new wide locking range divide-by-3 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process is presented. The ILFD is based on a class-C capacitive cross-coupled oscillator. By changing the dc gate bias of cross-coupled transistors to below the dc drain voltage, the locking range of ILFD has been improved. At the supply voltage of 1.8 V, the core power consumption of the ILFD core is 10.7 mW. The incident power of 0 dBm the divider’s maximum locking range is 3.3 GHz (24.17%),with the incident frequency from 12 to 15.3 GHz. At incident power of 0 dBm the divider’s operation range is 4.8 GHz (35.2%), from the incident frequency 10.5 to 15.3 GHz. Finally ,a wide locking range divide-by-3 injection-locked frequency dividers (ILFDs) using a standard 0.18 μm CMOS process are presented. The ILFDs are based on a cross-coupled n-core MOS LC-tank oscillator with either injection NMOSFETs or pMOSFETs. The core power consumption of the ILFD core with injection nMOSFETs is 10.8 mW at the supply voltage of 0.9V and with circuit core current of 12mA. At the incident power of 0 dBm the maximum locking range is 4.2 GHz (37.17%), from the incident frequency 9.2 to 13.4 GHz. The core power consumption of the ILFD core with injection pMOSFETs is 13.77 mW at the supply voltage of 0.9V and with circuit core current of 15.3mA. At the incident power of 0 dBm the maximum locking range is 2.4 GHz (25%), from the incident frequency 8.4 to 10.8 GHz.

碩士
國立清華大學
電機工程學系
103
Phase-locked loops are widely used in many applications for clock generation and synchronizations. The signal’s timing quality is of critical importance to the system’s performance. As more and more modules are integrated into the same chip in SoC era, the noise on the supply rails becomes larger and more significant. Many prior works have investigated the performance degradation due to supply noise and proposed techniques for improvement[4], [7], [8], [10]. In this work, we have designed and implemented a PLL using a CMOS ring oscillator for its wide tuning range from 200 MHz to 1.6 GHz. Furthermore, current-starved structure is used for delay cells for its rail-to-rail characteristics. However, ring oscillators are more susceptible to supply noise than the LC counterpart. In this design, the current mirror ratio is changed according to the operating frequency for optimal balance between the signal swing and charging current. This leads to low supply sensitivity over the tuning range. The measured supply sensitivity is from

Amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) constitute the central theme of this thesis. Within this theme, three primary areas of focus are pursued. The first focus is the realization of a transparent three-stage ring oscillator with buffered output and an output frequency in the megahertz range. This leads to the possibility of transparent radio frequency applications, such as transparent RFID tags. At the time of its fabrication, this ring oscillator was the fastest oxide electronics ring oscillator reported, with an output frequency of 2.16 MHz, and a time delay per stage of 77 ns. The second focus is to ascertain whether a three-terminal device (i.e., a TFT) is an appropriate structure for conducting space-charge-limited-current (SCLC) measurements. It is found that it is not appropriate to use a diode-tied or gate-biased TFT configuration for conducting a SCLC assessment since square-law theory shows that transistor action alone gives rise to I proportional to V² characteristics, which can easily be mistakenly attributed to a SCLC mechanism. Instead, a floating gate TFT configuration is recommended for accomplishing SCLC assessment of AOS channel layers. The final focus of this work is to describe an assessment procedure appropriate for determining if a dielectric is suitable for use as a TFT gate insulator. This is accomplished by examining the shape of a MIM capacitor's log(J)-ξ curve, where J is the measured current density and ξ is the applied electric field. An appropriate dielectric for use as a TFT gate insulator will have a log(J)-ξ curve that expresses a clear breakover knee, indicating a high-field conduction mechanism dominated by Fowler-Nordheim tunneling. Such a dielectric produces a TFT with a minimal gate leakage which does not track with the drain current in a log(I[subscript D])-V[subscript GS] transfer curve. An inappropriate dielectric for use as a TFT gate insulator will have a log(J)-ξ curve that does not express a clear breakover knee, indicating that the dominate conduction mechanism is defect driven (i.e., pin-hole like shunt paths) and, therefore, the dielectric is leaky. It is shown that experimental log(J)-ξ leakage curves can be accurately simulated using Ohmic, space-charge-limited current (SCLC), and Fowler-Nordheim tunneling conduction mechanisms.
Graduation date: 2010

A comprehensive and scalable solution for high-performance switched capacitor amplification is presented. Central to this discussion is the concept of ring amplification. A ring amplifier is a small modular amplifier derived from a ring oscillator that naturally embodies all the essential elements of scalability. It can amplify with accurate rail-to-rail output swing, drive large capacitive loads with extreme efficiency using slew-based charging, naturally scale in performance according to process trends, and is simple enough to be quickly constructed from only a handful of inverters, capacitors, and switches. In addition, the gain-enhancement technique of Split-CLS is introduced, and used to extend the efficacy of ring amplifiers in specific and other amplifiers in general. Four different pipelined ADC designs are presented which explore the practical implementation options and design considerations relevant to ring amplification and Split-CLS, and are used to establish ring amplification as a new paradigm for scalable amplification.
Graduation date: 2012
Access restricted to the OSU Community, at author's request, from July 19, 2012 - July 19, 2013

碩士
崑山科技大學
電子工程研究所
94
Phase-locked loop (PLL) is the component broadly used in various field of integrated circuits. Phase-locked loop is generally used in clock recovery of communication system and frequency synthesizer of wireless communication system. Recently, owing to the broadly use of the mobile electronic systems, low power consumption has become the main concern in the modern VLSI design. With the progress of VLSI technology, phase locked loop is necessarily designed in system on a chip (SoC). Thus, PLL has wide applications as well as operational amplifier does. The nucleus is a voltage-controlled oscillator in the circuit of phase-locked loop. In this thesis, we use the high input resistance, high output resistance and high voltage gain characteristics of differential amplifier to create voltage controlled oscillator (VCO) and low power consumption, low stating voltage characteristics of negative differential resistance device (NDR) to create another voltage controlled oscillator (VCO) in phase-locked loop. In this thesis, the phase-locked loop contains Phase Detector, Charge Pump, Low Pass Filter, Voltage Controlled Oscillator and Frequency Divider. Phase locked loop working properly with 3.3 volts power supply based on UMC 0.35um technology. According to the HSPICE simulation results, we implement two chips of the phase locked loop. The reference clock is from 10MHz to 50MHz. The VCO output-frequency is between 80MHz to 800MHz. Others show great reductions in all kinds of performances.

碩士
國立臺灣科技大學
電子工程系
99
The important blocks in the phase locked loop (PLL) are the voltage controlled oscillator (VCO) and the divider circuit. The most power consumption of PLL consumes in VCO and divider. The VCO is requested a low phase-noise to avoid corrupting the mixer-converted signal by close interfering tones for VCO circuit, and the Figure of Merit (FOM) of VCO can be determined by it’s performance. First, this thesis describes a differential cross-coupled complementary Colpitts CMOS voltage-controlled oscillator (VCO). Adopts a pair of cross-coupled PMOS transistors to achieve faster start-up oscillation. The VCO operates from 6.16 GHz to 6.5 GHz with 5.3 % tuning range. The measured phase noise at 1 MHz offset is -121.12 dBc/Hz at 6.417 GHz. The power consumption of the VCO core is 6.16 mW. The figure of merit is -189.37 dBc/Hz. Second, this thesis describes a new fully integrated CMOS voltage-controlled oscillator (VCO) is presented. The VCO is composed of cross-coupled Colpitts negative resistance cell in shunt with a parallel-tunerd LC resonator and the negative resistance cell uses bias-free pMOS tail for low-phase noise design. With the supply voltage of 1.15 V, the VCO is tunable from 18 GHz to 20.25 GHz. while the tuning voltage varies from 0 V to 1.4 V. The phase noise of the VCO operating at 18 GHz is -117.34 dBc/Hz at 1 MHz offset, while the VCO draws 7.07 mA and uses 8.13 mW consumption. The figure of merit is -193.24 dBc/Hz. Finally, a novel quadrature VCO (QVCO) is showed, This design presents a new quadrature voltage-controlled oscillator (QVCO), which consists of two n-core cross-coupled voltage-controlled oscillators (VCOs) with a bottom-series pMOSFET LC ring. At the supply voltage of 1.24 V, the output phase noise of the QVCO is -119.54 dBc/Hz at 1MHz offset frequency from the carrier frequency of 9.25 GHz, and the figure of merit (FOM) is -189.1 dBc/Hz. The power consumption of QVCO core is 9.47 mW. The free-running frequency of the QVCO is tunable from 9.01 GHz to 9.34 GHz as the tuning voltage is varied from 0.0 V to 1.1 V.

碩士
國立高雄應用科技大學
電子工程系
98
The voltage-controlled oscillator (VCO) is an important component of clock and data recovery (CDR) in the optical receiver module of optical communication system. In this thesis, the ring VCOs are designed using the TSMC 0.35 m complementary metal-oxide-semiconductor (CMOS) process with 3.3 V power supply voltage. A conventional two-stage ring VCO chip is implemented. The frequency tuning range of the ring VCO is from 1.1 GHz to 1.7GHz. The measured range of the phase noise is from -82.47 dBc/Hz to -46.35 dBc/Hz at 600 kHz offset. Since the output amplitude of the two-stage ring VCO is small, the immunity from electromagnetic interference is low. We first present the ring VCO with multiple loops. The output amplitude of the ring VCO can be increased, and its phase noise performance can be improved. A six-stage ring VCO with multiple loops has been also achieved. The frequency tuning range of the VCO is from 1.2 GHz to 2.5 GHz. The phase noise range is from -93.88 dBc/Hz to -72.92 dBc/Hz at 600 kHz offset. In addition, a simple 1.25 Gbps full-rate CDR is also designed. When a 625 MHz square wave is applied, the locking time of the CDR is about 4 s, and the ripple of control voltage is within 10 mV.

碩士
國立臺灣大學
電子工程學研究所
96
Ring oscillators and frequency synthesis are widely employed in communication systems, such as clock generators or in-loop modulators. In this thesis, a dual-delay path ring oscillator and a multiphase compensation method for fractional-N frequency synthesizer are covered. Ring oscillators are widely used in clock generators and frequency synthesis. To increase the oscillation frequencies, dual-delay path ring oscillators are often implemented to explore the maximum frequency levels. Two oscillation modes have been found in differential four-stage dual-delay path ring oscillators, one named differential mode oscillation and the other named common mode oscillation. In differential mode oscillation, a single delay cell contains differential output waveforms, but in common mode, the output waveforms are in-phased. In addition, the oscillation frequencies of the two oscillation modes are not the same either. These problems might spoil the function of the clock generators and frequency synthesis. For more insight of dual-path ring oscillators, mathematical analysis and demonstrations including the two oscillation mode in a differential four-stage dual-delay path ring oscillator is presented. A differential four-stage dual-delay path ring oscillator is fabricated in a 0.18-um CMOS technology with an active area of 58×41 um2. The measured tuning range is from 1.77 GHz to 1.92 GHz in differential mode oscillation which consumes 13 mW from a 1.8-V power supply, and from 1.01 GHz to 1.055 GHz in common mode oscillation that consumes 10 mW from a 1.8-V power supply. High performance frequency synthesis is required in communication systems such as WCDMA transceivers or in-loop modulation systems. In this thesis, a S-D fractional-N frequency synthesizer with a multiphase compensation method is proposed. To resolve the problem brought by nonidea effect such as delay unit mismatch and gain error, a proposed delay line structure and a digital control circuit including dynamic element matching techniques and a re-quantized S-D modulator is presented. A frequency synthesizer operating from 2.11 GHz to 2.17 GHz, is fabricated in a 0.18-um CMOS technology with an area of 0.92×1.15 mm2. Power consumption is 27.2 mW from 1.8-V power supply. The proposed architecture suppresses the quantization noise of 2.4-GHz output at 10-MHz frequency offset by 10 dB. The settling time is less than 25 usec.