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Journal articles on the topic 'Ring Oscillator Design'

Author: Grafiati

Published: 4 June 2021

Last updated: 6 September 2023

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1

Zainol Murad, Sohiful Anuar, Rizalafande Che Ismail, Mohamad Shahimin Mukhzeer, Ahmad Mohd Fairus, and Sapawi Rohana. "Development of Varied CMOS Ring Oscillator Topologies in 0.13-μm CMOS Technology." Applied Mechanics and Materials 446-447 (November 2013): 882–86. http://dx.doi.org/10.4028/www.scientific.net/amm.446-447.882.

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This paper presents varied CMOS ring oscillator topologies using Silterra 0.13-µm Process. Three topologies of ring oscillators have been designed which is the single-ended ring oscillator, differential ring oscillator and ring oscillator based variable resistor for 2.4 GHz wireless applications. The proposed designs consist of five stages delay cell. The simulation results show that a single-ended ring oscillator obtained the lowest power consumption of 0.41 mW, while differential oscillator achieves phase noise of −64.44 dBc/Hz at 1 MHz offset frequency. However, ring oscillator based variable resistor did not achieve any significant improvement. The proposed design is oscillates at 2.4 GHz.

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2

H, Thejusraj, Prithivi Raj, J. Selvakumar, and S. Praveen Kumar. "Design of High frequency Voltage Controlled Oscillators for Phase Locked Loop." International Journal of Engineering & Technology 7, no. 3.12 (July 20, 2018): 871. http://dx.doi.org/10.14419/ijet.v7i3.12.16553.

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This paper presents the analysis of various oscillators that generate high frequency of oscillation for high speed communication, clock generation and clock recovery. The Ring oscillator and the Current Starved Voltage Controlled Oscillator(CSVCO) (for 5-stagewithout resistor and with resistor) have been implemented using the Cadence Virtuoso tool in 90 nm technology. The generated frequency of oscillation and the power consumption values of the voltage controlled oscillators have been calculated after inclusion in the PLL, and were also compared to identify the most suitable voltage controlled oscillator for a given application.

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3

I'msaddak, Lobna, Dalenda Ben Issa, Abdennaceur Kachouri, Mounir Samet, and Hekmet Samet. "Infrared Oscillators in Conventional Carbon Nanotube FET Technology." Journal of Circuits, Systems and Computers 24, no. 04 (March 4, 2015): 1550053. http://dx.doi.org/10.1142/s021812661550053x.

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This paper presents the design of C-CNTFET oscillator's arrays for infrared 'IR' technology. These arrays are contained by both of the LC-tank and the voltage control 'coupled N- and P-type C-CNTFET LC-tank' oscillators. In this paper, the analysis of the impact of CNT diameter variations and the nonlinear capacitances (C GD and C GS ) were introduced, especially on propagation time, oscillation frequency and power consumption. The C-CNTFET inverter, ring oscillator, LC-tank and coupled N- and P-type C-CNTFET LC-tank oscillator structures were designed and their speeding and performances have been investigated with the proposed n-type of C-CNTFET model supplied by a 0.5 V power voltage. Simulation results show that the n- and p-types LC-tank oscillator circuit designs achieved an approximately equal oscillation frequency, response time and power consumption. Whereas the coupled N- and P-type C-CNTFET LC-tank oscillator has the lowest power consumption equal to 0.13 μW, the highest oscillation frequency (10.08 THz) and the fastest response time (1.81 ps).

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4

Priyanka Kumari, B. S., and Sobhit Saxena. "Design and Implementation of Efficient MOSFET’s Utilization Based Proposed Voltage Controlled Oscillator." Journal of Physics: Conference Series 2089, no. 1 (November 1, 2021): 012073. http://dx.doi.org/10.1088/1742-6596/2089/1/012073.

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Abstract Ring oscillator is a device which consists of NOT gates connected in the form of ring. This ring oscillator’s output oscillates between the true and false stages controlled by applied voltage. Now days this voltage controlled oscillator (VCO) becomes the heart of modern electronic devices and communication systems. Earlier five-stage complementary metal oxide semiconductor (CMOS) based VCO for the Phase Locked Loop (PLL) was implemented. High frequency oscillations are required for many applications and further it is observed that a very general technique is normally adopted by researchers to achieve high frequency that if number of transistors is increased then the frequency can be increased. But the consequences of increase in number of transistors are the increase in delay and more number of MOSFET occupies more area and more power dissipation. So, in this paper VCO is designed with efficient utilization of MOSFETs. There is a balance between frequency and number of transistors, so that the area and power dissipation can be reduced. From the obtained results it can observed that the number of MOSFET’s, Independent Nodes, boundary nodes total nodes and power are reduced compared to five stage VCO and VCO based Ring oscillator.

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5

Loong Teo, Julius Han, Noor Alia Nor Hashim, Azrul Ghazali, and Fazrena Azlee Hamid. "Ring oscillator physically unclonable function using sequential ring oscillator pairs for more challenge-response-pairs." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 3 (March 1, 2019): 892. http://dx.doi.org/10.11591/ijeecs.v13.i3.pp892-901.

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<span>The ring oscillator physically unclonable function (ROPUF) is one of the several types of PUF that has great potential to be used for security purposes. An alternative ROPUF design is proposed with two major differences. Firstly, the memristor is included in the ring oscillators as it is claimed to produce a more random oscillation frequency. Other reasons are its memory-like properties and variable memristance, relative compatibility with CMOS, and small size. Secondly, a different method of generating the response is implemented whereby a sequence of selection of ring oscillator pairs are used to generate a multiple bit response, rather than using only one ring oscillator pair to generate a single bit response. This method significantly expands the set of challenge-response pairs. The proposed memristor-based ROPUF shows 48.57%, 51.43%, and 51.43% for uniqueness, uniformity, and bit-aliasing, respectively. Also, modelling by support vector machine (SVM) on the proposed memristor-based ROPUF only shows 61.95% accuracy, thereby indicating strong resistance against SVM.</span>

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6

Pal, Reena, Najbeen Bano, Dr Shiksha Jain, and Er Deepika Verma. "Literature Review on Ring Oscillator for Biomedical Application Using CMOS." International Journal for Research in Applied Science and Engineering Technology 11, no. 5 (May 31, 2023): 4858–62. http://dx.doi.org/10.22214/ijraset.2023.52724.

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Abstract: In this paper we have been studies on various design techniques of oscillator for biomedical application. The major subject of this research study is oscillators, which are electronic circuits that generate periodic signals with a constant frequency. A comprehensive review of various oscillator topologies and their characteristics, including stability, frequency range, and phase noise, is provided in this article. The project's objective is to review contemporary oscillator design approaches and consider how they might be applied in a variety of sectors, such as instrumentation, control, and communication systems. Oscillators are electronic circuits that generate repeated waves at set frequency. It is the foundation of numerous electrical gadgets, such as radios, televisions, and computers. Oscillators are used in measurement, control, and communication systems. Science routinely examines the behavior and characteristics of oscillators, such as their stability, frequency range, and phase noise. Researchers may also look at novel oscillator topologies and design approaches to improve performance or enable new applications. Oscillator research is essential for the development of cutting-edge electrical technologies and systems.

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7

Zhang, Zhao-hua, Rui-feng Yue, and Li-tian Liu. "Accelerometer Design Using MOS Ring Oscillator." Frontiers of Electrical and Electronic Engineering in China 1, no. 1 (January 2006): 77–81. http://dx.doi.org/10.1007/s11460-005-0015-7.

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8

Sharma, Prakash. "Performance Analysis of Ring Oscillators and Current-Starved VCO in 45-nm CMOS Technology." International Journal for Research in Applied Science and Engineering Technology 10, no. 1 (January 31, 2022): 732–37. http://dx.doi.org/10.22214/ijraset.2022.39908.

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Abstract: This paper presents a relative study among two Ring oscillators architecture (CMOS, NMOS) and current-starved Voltage-controlled oscillator (CS-VCO) on the basis of different parameters like power dissipation ,phase noise etc. All the design has been done in 45- nm CMOS technology node and 2.3 GHz Centre frequency have been taken for the comparison because of their applications in AV Devices and Radio control. An inherent idea of the given performance parameters has been realize by thecomparative study. The comparative data shows that NMOS based Ring oscillator is good option in terms of the phase noise performance. In this study NMOS Ring Oscillator have attain a phase noise -97.94 dBc/Hz at 1 MHz offset frequency from 2.3 GHz center frequency. The related data also shows that CMOS Ring oscillator is the best option in terms of power consumption. In this work CMOS Ring oscillator evacuatea power of 1.73 mW which is quite low. Keywords: Voltage controlled oscillator (VCO), phase noise, power consumption, Complementary metal-oxide-semiconductor (CMOS), Current Starved Voltage-Controlled Oscillator (CS- VCO), Pull up network (PUN), Pull down network (PDN)

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9

Song, Ming Xin, Shan Shan Wang, and Guo Dong Sun. "CMOS Low Power Ring VCO Design." Advanced Materials Research 981 (July 2014): 70–73. http://dx.doi.org/10.4028/www.scientific.net/amr.981.70.

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A design project of voltage controlled oscillator which is the central component of the low voltage phase locked loop (PLL) is proposed in this paper. The VCO adopted the folding differential voltage controlled oscillator.Simulation results in Cadence Hspice indicate that the VCO proposed behaves in good linearity, simple structure, small phase noise.The frequency range from 125 to 787 MHz, the power consumption of this oscillator is only 6mW at central frequency is 480MHz with 3V power supply.

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10

Tlelo-Cuautle, Esteban, Perla Rubi Castañeda-Aviña, Rodolfo Trejo-Guerra, and Victor Hugo Carbajal-Gómez. "Design of a Wide-Band Voltage-Controlled Ring Oscillator Implemented in 180 nm CMOS Technology." Electronics 8, no. 10 (October 12, 2019): 1156. http://dx.doi.org/10.3390/electronics8101156.

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The design of a wide-band voltage-controlled oscillator (VCO) modified as a VCO with programmable tail currents is introduced herein. The VCO is implemented by using CMOS current-mode logic stages, which are based on differential pairs that are connected in a ring topology. SPICE simulation results show that the VCO operates within the frequency ranges of 2.65–5.65 GHz, and when it is modified, the VCO with programmable tail currents operates between 1.38 GHz and 4.72 GHz. The design of the CMOS differential stage is detailed along with the symbolic approximation of its dominant pole, which is varied to increase the frequency response in order to achieve a higher oscillation frequency when implementing the ring oscillator structure. The layout of the VCO is described and pre- and post-layout simulations are provided, which are in good agreement using CMOS technology of 180 nm. Finally, process, voltage and temperature variations are performed to guarantee robustness of the designed CMOS ring oscillator.

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11

Drost, Brian, Mrunmay Talegaonkar, and Pavan Kumar Hanumolu. "Analog Filter Design Using Ring Oscillator Integrators." IEEE Journal of Solid-State Circuits 47, no. 12 (December 2012): 3120–29. http://dx.doi.org/10.1109/jssc.2012.2225738.

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12

Zhao, Zhi Gang. "The Design of Ring Oscillator Accelerometer Low-Frequency Signal Measurement Circuits." Applied Mechanics and Materials 170-173 (May 2012): 3635–38. http://dx.doi.org/10.4028/www.scientific.net/amm.170-173.3635.

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The basic principle of Ring Oscillator Accelerometer is analyzed in this paper. On the basic of simulation and analysis of the structure of the Ring Oscillator Accelerometer, a four-silicon beam structure is put up . Then the mixer- principle of the dual-gate MOS mixer is analyzed in theory. Finally, We have simulated the ring oscillator circuit and the dual-gate MOS mixer circuit using the PSpice. The result of the simulation fits theory well.

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13

Voicu, Marius, Domenico Pepe, and Domenico Zito. "Performance and Trends in Millimetre-Wave CMOS Oscillators for Emerging Wireless Applications." International Journal of Microwave Science and Technology 2013 (March 28, 2013): 1–6. http://dx.doi.org/10.1155/2013/312618.

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This paper reports the latest advances on millimeter-wave CMOS voltage-controlled oscillators (VCOs). Current state-of-the-art implementations are reviewed, and their performances are compared in terms of phase noise and figure of merit. Low power and low phase noise LC-VCO and ring oscillator designs are analyzed and discussed. Design and performance trends over the last decade are provided and discussed. The paper shows how for the higher range of millimeter-waves (>60 GHz) the performances of ring oscillators become comparable with those of LC-VCOs.

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14

Prof. Nikhil Surkar. "Design and Analysis of Optimized Fin-FETs." International Journal of New Practices in Management and Engineering 4, no. 04 (December 31, 2015): 01–06. http://dx.doi.org/10.17762/ijnpme.v4i04.39.

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Semiconductor industry greatly depends on CMOS technology and now needs competent technology with handful benefits. This paper examines and analyzes the modern FINFET technology. This analysis is performed through 9 stages Ring Oscillator equipped with FINFET. Performance is analyzed by comparing the proposed structure with CMOS based 9 stage Ring Oscillator at the nano-scale level of abstraction.

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15

Xu, Chen, Xiang Ning Fan, Zai Jun Hua, and Zhou Yu. "Design of a CMOS Voltage-Controlled Ring Oscillator with Bandgap Voltage Reference." Applied Mechanics and Materials 618 (August 2014): 558–62. http://dx.doi.org/10.4028/www.scientific.net/amm.618.558.

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Voltage controlled oscillator has been used in every field of the electronics industry, and plays an indispensable role. In the fractional divider, in order to reduce the product size, voltage controlled ring oscillator is used to meet the design requirements, at the same time as much as possible to reduce the area. The design of wide tuning voltage-controlled ring oscillator was designed with the reference voltage source. This design not only could reduce the error brought by the external voltage reference, and was also very good realization structure innovation in the film. This design used 0.5 μ m CMOS Hua technology. The post simulation results show: when the coarse voltage and fine voltage are respectively 1V and 2V, voltage waveform oscillator output swing is 2.4V; when the coarse voltage and fine voltage are respectively 1.13V and 2V, voltage waveform oscillator output swing is 2.8V; when the coarse voltage and fine voltage are respectively 1.3V and 2V, voltage waveform oscillator output swing is 3V. After simulations, the frequency range of the voltage-controlled ring oscillator adjustment is 100 ~ 200MHz.

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16

Soltani, Masoud, Farzan Khatib, and Seyyed Javad Seyyed Mahdavi Chabok. "High-performance combined ring oscillators." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 39, no. 3 (April 16, 2020): 535–50. http://dx.doi.org/10.1108/compel-01-2020-0039.

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Purpose The purpose of this paper is to investigate a more robust ring oscillator. Less sensitivity to power supply variations is a target. This is important since low-quality ring oscillators could be exploited in numerous systems to reduce die costs. Design/methodology/approach The method in this work is large signal analysis. Delay time as the large signal parameter is calculated symbolically to explore dependency on a power supply voltage. Then simulations are performed to make a comparison. In this work, mathematical justifications are verified via HSPICE circuit simulator outputs, while 0.18 µm TSMC CMOS technology is exploited. Findings At least two combined configurations are presented with higher robustness. These circuits are more appropriate in noisy conditions. Both theoretical calculations and simulation results verify less sensitive oscillation against supply voltage ripples and temperature variations. Originality/value Introducing a band-switched inverter in combined configurations is contribution. In this way, three structures are presented which both show higher stability in oscillation frequency. The band switched delay time calculations are quite new and also the validity of the symbolical delay time approach is verified by circuit simulations.

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17

Liu, Rui Hong, and Chih Hsiung Shen. "A High Resolution Vernier Ring Oscillator with Ultra-Low Temperature Drift." Advanced Materials Research 542-543 (June 2012): 795–99. http://dx.doi.org/10.4028/www.scientific.net/amr.542-543.795.

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Nowadays, the precise measurement of the time interval between two events with very fine timing resolution is common challenge in the test and measurement instrumentation. This paper present a new high resolution vernier ring oscillator(VRO), which can measures the clock jitter as the operation temperature rises.The goal of this work focuses on the design of a TDC of temperature stable oscillator and we propose an ultra-low temperature drift of a differential delay cell oscillator based on a proportional to absolute temperature(PTAT) compensation methodology. It is very desirable to have a single integrated circuit producing a stable high resolution timing circuit over a wide temperature range developed in a standard CMOS process. By the simple concept of vernier delay line and two ring oscillators, the proposed can achieve a fine time resolution with wide working temperature. For each channel of ring oscillator, the relative delay time is fine tuned by an external VBIAS input. From 25°Cto 45°C, the maximum error percent of delay time without compensation circuits is more than 2.9%, but it with compensation circuits is less than 0.3%. The different operating temperature will affect entire circuit and the delay time of ring oscillator. A compensation circuit to reduce the variety of ring oscillator is also added. The new architecture of high resolution TDC with temperature compensated circuit is proven to be applicable in high precision clock applications which is analyzed and implemented in a CMOS 0.18μm 1P6M process.

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18

Yan, Wei, and John Chandy. "Phase Calibrated Ring Oscillator PUF Design and Application." Computers 7, no. 3 (July 26, 2018): 40. http://dx.doi.org/10.3390/computers7030040.

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A Ring Oscillator Physical Unclonable Function (RO PUF) is an application-constrained hardware security primitive that can be used for authentication and key generation. PUFs depend on variability during the fabrication process to produce random outputs that are nevertheless stable across multiple measurements. Though industry has a growing need for PUF implementations on Field Programmable Gate Arrays (FPGA) and Application-Specific Integrated Circuits (ASIC), the bit errors in PUF responses become a bottleneck and limit the usage. In this work, we comprehensively evaluate the RO PUF’s stability on FPGAs, and we propose a phase calibration process to improve the stability of RO PUFs. We also make full use of the instability of PUFs to provide a novel solution for authentication. The results show that the bit errors in our PUFs are reduced to less than 1%.

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19

Choi, Jin-Ho. "Design of CMOS Temperature Sensor Using Ring Oscillator." Journal of the Korea Institute of Information and Communication Engineering 19, no. 9 (August 20, 2015): 2081–86. http://dx.doi.org/10.6109/jkiice.2015.19.9.2081.

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20

Anitha, D., K. Manjunatha Chari, and P. Satish Kumar. "Design of PVT compensated current starved ring oscillator." International Journal of Circuits and Architecture Design 2, no. 2 (2016): 169. http://dx.doi.org/10.1504/ijcad.2016.082146.

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Anitha, D., K. Manjunatha Chari, and P. Satish Kumar. "Design of PVT compensated current starved ring oscillator." International Journal of Circuits and Architecture Design 2, no. 2 (2016): 169. http://dx.doi.org/10.1504/ijcad.2016.10003051.

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22

Shiyamala, S., and T. Kavitha. "Design of Low Delay Ring Oscillator Using CMOS." International Journal of Engineering & Technology 7, no. 3.6 (July 4, 2018): 334. http://dx.doi.org/10.14419/ijet.v7i3.6.15126.

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In the Era of digital World, low power applications are the needs of the market to save the resources. Delay elements (e.g. digital clock) are essential parts of such digital applications. Ring oscillators have been used because of their ease of implementation, wide tuning ranges, operating at low voltages and existing possibility of complete integration in standard CMOS processes. It desires at identifying the best possible configuration for the hoop oscillators having the least strength intake and precise delay with lesser sensitivity to the variations inside the temperature and deliver voltage for frequencies of few KHz. while N = 7, for 0.18 µm generation , put off is 0.07ns simplest. Compare with N = 3, 14.2 % delay time reduced and 12.6 % lower when N= 7 taken into account.

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23

Dash, Sandeep, Satya Mishra, and Nirmal Rout. "Design of efficient delay block for low frequency application." Facta universitatis - series: Electronics and Energetics 33, no. 3 (2020): 489–98. http://dx.doi.org/10.2298/fuee2003489d.

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In recent years researchers have been focusing on the design of low power and small size oscillator for emerging areas of interest such as the internet of things (IoT) and biomedical applications. In this paper a new delay block for ring oscillator is proposed using CMOS inverter cascaded with inverted current starved inverter (CICSI). The designed delay block provides approximately 50% more delay with a smaller number of transistors than the conventionally designed circuits. Furthermore, a ring oscillator and a non-overlapping clock (NOC) generator are designed using it. The designed circuits can be used in switched capacitor (SC) circuits, analog mixed signal circuits to meet the need for low frequency portable biomedical applications. The designed circuits are simulated on Generic 90nm 1.2V Process Design Kit (GPDK90) using Cadence Virtuoso Design Environment. The simulation result shows the delay of the CICSI delay block is 592ps. The ring oscillator using 101 stages of delay block is designed and it is shown that it operates at a frequency of 17MHz with a power consumption of 420?W.

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24

Rai, Manish Kumar, and Sanjeev Rai. "Impact of Negative Capacitance Junctionless Nanowire (NCJLNW) MOSFET on Ring Oscillator Design and Analysis." International Journal of Innovative Technology and Exploring Engineering 12, no. 4 (March 30, 2023): 1–7. http://dx.doi.org/10.35940/ijitee.d9464.0312423.

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This work presents the analysis of NCJLNW for low power analog/RF applications; this device shows reduced power consumption, reduced SCEs, smaller leakage and higher Ion/Ioff ratio. The results indicate that the proposed device improves the intrinsic gain, cut-off frequency, transconductance and reduces DIBL. The analysis of band-energy, surface-potential and electric-field has also shown promising results. Ring oscillator has been designed using this device; the analysis of the oscillator presents lower voltage of operation resulting into reduced power consumption, and high noise immunity. The frequency of oscillation is found to be higher at 172.1 GHz at a channel length of 20 nm.

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Yaacob, Nor Samida. "Low Power Ring Oscillator Design in 130nm CMOS Technology." Journal of Engineering and Science Research 3, no. 3 (June 28, 2019): 14–18. http://dx.doi.org/10.26666/rmp.jesr.2019.3.3.

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A temperature-stable, low-power ring oscillator design for implementation in an Application-Specific Integrated Circuit (ASIC) is presented. In this work, the design uses a new arrangement of chain delay elements consisting of a current-starved inverter and a CMOS capacitor. This power consumption improvement ring oscillator design was built in the environment of 130nm CMOS process technology using Mentor Graphics environment with voltage supply 1V. The simulation results show a maximum power consumption of 1.036 nW and it shows that the presented design is applicable in low power advanced sensing systems application including biomedical, chemical, and other sensors.

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Selvaraj, Santthosh, Erkan Bayram, and Renato Nega. "Comparison of System-Level Design Approaches on Different Types of Digitally-Controlled Ring-Oscillator." Technologies 9, no. 2 (May 19, 2021): 38. http://dx.doi.org/10.3390/technologies9020038.

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This paper presents a comparative study between two different implementations of digitally-controlled-oscillators (DCOs), whcih is the DAC-based and the digital controller-based DCO in TSMC 65 nm CMOS technology. This paper focuses on ring-oscillator architectures due to their high stability against PVT. The DAC-based oscillator implements a differential architecture, and the digital controller-based architecture operates in a single-ended signal. The SFDR of the DAC-based DCO is 77.2 dBc and controller-based DCO is 56.8 dBc at 125 MHz offset. The Monte-Carlo simulation gives a deviation of 7.4% and 8.5% for the DAC-based and controller-based DCO, respectively. The phase noise performance of the DAC-based DCO and controller-based DCO is −78.9 dBc/Hz and −81.3 dBc/Hz at 1 MHz offset, respectively. The implementations are given and compared according to their performance based on post-layout simulation results.

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Mukherjee, Sagar, Swarnil Roy, Kalyan Koley, Arka Dutta, and Chandan Kumar Sarkar. "Design and study of programmable ring oscillator using IDUDGMOSFET." Solid-State Electronics 117 (March 2016): 193–98. http://dx.doi.org/10.1016/j.sse.2015.11.009.

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Mondal, Abir J., J. Talukdar, and Bidyut K. Bhattacharyya. "Variation aware design of controlled voltage swing ring oscillator." International Journal of Electronics 107, no. 1 (July 10, 2019): 99–124. http://dx.doi.org/10.1080/00207217.2019.1636307.

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Sakka, Zied, Nadia Gargouri, and Mounir Samet. "A Temperature-Stable Low-Power Wide-Range CMOS Voltage Controlled Oscillator Design for Biomedical Applications." Journal of Circuits, Systems and Computers 29, no. 08 (October 11, 2019): 2050128. http://dx.doi.org/10.1142/s0218126620501285.

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This paper presents a low power temperature compensated CMOS ring oscillator for biomedical applications across a wide temperature range. The proposed circuit deploys an IPTAT (inversely proportional to absolute temperature) bias current by generating an adaptive control voltage in each stage of the oscillator to compensate the overall oscillator’s temperature coefficient (TC). Simulations using TSMC 0.18[Formula: see text][Formula: see text]m CMOS technology show that this configuration can achieve a frequency variation less than 0.25%, leading to an average frequency drift of 20.83[Formula: see text]ppm/∘C. Monte Carlo simulations have also been performed and demonstrate a 3[Formula: see text] deviation of about 2.15%. The power dissipated by the proposed circuit is only 8.48[Formula: see text]mW at 25∘C.

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Ma, Chaofang, Jing Ye, Xiaowei Li, Huawei Li, and Yu Hu. "Adjustable and Configurable Ring Oscillator Physical Unclonable Function." Journal of Computer-Aided Design & Computer Graphics 33, no. 3 (March 1, 2021): 340–45. http://dx.doi.org/10.3724/sp.j.1089.2021.18561.

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31

MohamedAliHassen, Ashraf. "Analysis and Design of High Performance Ring Voltage Controlled Oscillator." International Journal of Computer Applications 70, no. 20 (May 31, 2013): 5–10. http://dx.doi.org/10.5120/12181-7923.

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Guler, Ulkuhan, Ali Emre Pusane, and Günhan Dundar. "Design of efficient CMOS ring oscillator-based random number generator." International Journal of Electronics 104, no. 9 (April 10, 2017): 1465–82. http://dx.doi.org/10.1080/00207217.2017.1312704.

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33

Mishra, Vivek, Anurag Yadav, and Subodh Wairya. "Design of Compensated Supply Circuit Topology for a Ring Oscillator." International Journal of Computing and Digital Systems 12, no. 4 (October 31, 2022): 1006–17. http://dx.doi.org/10.12785/ijcds/120181.

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34

Cao, Fu Yi, Zhi Li, and Xiang Feng Wang. "Research on Signal Processing Circuits of Ring Oscillator Accelerometer." Applied Mechanics and Materials 263-266 (December 2012): 287–91. http://dx.doi.org/10.4028/www.scientific.net/amm.263-266.287.

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In this paper, the basic principle of the ring oscillator accelerometer has been analysed. According to the characteristics of low-frequency signal of ring oscillator accelerometer output, the methods to measure the low frequency of the sensor output signal by measure period is proposed and simulated the comparator circuit. Finally, we design and simulate all measure circuits and the results and theory in line with the good.

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35

Kumar, Manoj. "A Low Power Voltage Controlled Oscillator Design." ISRN Electronics 2013 (May 15, 2013): 1–6. http://dx.doi.org/10.1155/2013/987179.

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The performance of voltage controlled oscillator (VCO) is of great importance for any telecommunication or data transmission network. Here, voltage controlled oscillators (VCOs) using three-transistor NAND gates have been designed. New delay cell with three-transistor NAND gate has been used for designing the ring based VCO circuits. Three-, five-, and seven-stage VCOs have been proposed. Output frequency has been controlled with supply voltage variation from 1.8 V to 2.4 V. Three stage VCO shows output frequency variation in the range of 3.2909 GHz to 4.2280 GHz whereas power consumption varies in the range of 335.4071 μW to 486.1816 μW. Five-stage VCO depicts frequency in the range of 1.9406 GHz to 2.5769 GHz with power consumption variation from 559.0118 μW to 810.3027 μW. Moreover a seven-stage VCO shows frequency variation from 1.3984 GHz to 1.8077 GHz. Power consumption of seven-stage VCO varies from 782.6165 μW to 1134.400 μW. Phase noise results for these VCOs have also been obtained. Power consumption, output frequency, and phase noise results of proposed circuits have been compared with earlier reported circuits, and the proposed circuits show significant improvements.

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36

Brandl, Martin, and Lisa-Marie Wagner. "Microwave Oscillator Design for a SRR Based Biosensor Platform." Proceedings 2, no. 13 (November 21, 2018): 865. http://dx.doi.org/10.3390/proceedings2130865.

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A sensor for biomedical markers based on a split ring microwave resonator (SRR) was developed. The surface of the microwave resonator is covered with receptors that specifically bind to the target proteins where the local permittivity is changed. The resonator is part of a microwave oscillator circuit. Changes in the local permittivity caused by coupling of the target proteins result in a change of oscillator frequency which can be easily and accurate measured with high sensitivity.

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37

Moon, Dongwoo, Milim Lee, Changhyun Lee, Joung-Hu Park, and Changkun Park. "Wireless Transceiver for Three-Dimensional Integrated Circuits Using a Ring Oscillator." Journal of Circuits, Systems and Computers 29, no. 10 (December 9, 2019): 2050161. http://dx.doi.org/10.1142/s0218126620501613.

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In this paper, we propose an oscillation-type transceiver for wireless chip-to-chip communication (WCC). The proposed transceiver is composed of a ring oscillator, coils, inverter-type amplifier, voltage multiplier and comparator. The ring oscillator itself acts as the on–off keying (OOK) modulator. The envelope of the transferred OOK-modulated signal is detected in the voltage multiplier of the receiver. Given that the proposed transceiver uses an OOK-modulated oscillating signal, the noise immunity is improved compared to the typical pulse-type transceiver. To verify the functionality of the proposed transceiver, we design the transceiver using the 180-nm complementary metal-oxide-semiconductor process. From the measured results, we verify that the proposed transceiver recovers the entered digital signal up to a distance of 0.2[Formula: see text]mm between the primary and secondary coils. Additionally, the sensitivity to the bias voltage of the latch is nonexistent by virtue of removing the latch in the proposed transceiver.

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38

Miao, Tian-ze, Ren-zhen Xiao, Yan-chao Shi, Kun Chen, Yu-chuan Zhang, Jun Sun, Dong-yang Wang, and Jia-ru Shi. "Efficiency improvement by a beam filtering ring in a relativistic backward wave oscillator at low magnetic field." Physics of Plasmas 29, no. 4 (April 2022): 043302. http://dx.doi.org/10.1063/5.0082447.

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This paper presents a design method of the relativistic backward wave oscillator at low magnetic field, which can improve the efficiency by 29% in the particle in cell simulation. The core of this method is to introduce a beam filtering ring. The beam filtering ring takes the characteristic of the radial position change as the electron oscillates. The structure manipulates the axial current, so that a large proportion of the electrons expected to be in the accelerated phase in the slow-wave structure is absorbed by the structure. It greatly enhances the bunching of the beam in the RF field and improves the beam-wave conversion efficiency significantly. The particle in cell simulation results reveal that at a permanent magnet with a magnetic induction intensity of 0.68 T, the output microwave power of the relativistic backward wave oscillator with a beam filtering ring is 5.9 GW, and the conversion efficiency can be up to 54% when the diode voltage is 890 kV and the beam current is 12.2 kA.

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39

Kodýtek, Filip, and Róbert Lórencz. "Proposal and Properties of Ring Oscillator-Based PUF on FPGA." Journal of Circuits, Systems and Computers 25, no. 03 (December 28, 2015): 1640016. http://dx.doi.org/10.1142/s0218126616400168.

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This paper deals with design of physical unclonable functions (PUFs) based on field-programmable gate array (FPGA). The goal was to propose a cheap, efficient and secure device identification or even a cryptographic key generation based on PUFs. Therefore, a design of a ring oscillator (RO)-based PUF producing more output bits from each RO pair is presented. 24 Digilent Basys 2 FPGA boards (Spartan-3E) and 6 Digilent Nexys 3 FPGA boards (Spartan-6) were tested and statistically evaluated indicating suitability of the proposed design for device identification. A stable PUF output is required for generating cryptographic keys. As post-processing technique to further improve the efficiency of this PUF design, we used Gray code on the obtained bits from RO pairs. Ultimately, the PUF design is combined with error correction code and together with Gray code is able to generate cryptographic keys of sufficient length.

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40

Lee, Ju-Heun, Min-Cheol Hong, Jeong-Taek Oh, and Won-Sang Yoon. "Design of a S-band Oscillator Using Vertical Split Ring Resonator." Journal of Korean Institute of Information Technology 17, no. 3 (March 31, 2019): 43–50. http://dx.doi.org/10.14801/jkiit.2019.17.3.43.

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41

Mohammadi, Ali, Mohammad Mohammadi, and Seyed Hamid Zahiri. "Design of optimal CMOS ring oscillator using an intelligent optimization tool." Soft Computing 22, no. 24 (August 8, 2017): 8151–66. http://dx.doi.org/10.1007/s00500-017-2759-4.

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42

Kumar, Sushil. "Design and Performance Analysis of Nine Stages CMOS Based Ring Oscillator." International Journal of VLSI Design & Communication Systems 3, no. 3 (June 30, 2012): 57–69. http://dx.doi.org/10.5121/vlsic.2012.3306.

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43

Lei, Xuemei, Zhigong Wang, and Lianfeng Shen. "Design and analysis of a three-stage voltage-controlled ring oscillator." Journal of Semiconductors 34, no. 11 (November 2013): 115003. http://dx.doi.org/10.1088/1674-4926/34/11/115003.

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44

Chan, Tuck-Boon, Puneet Gupta, Andrew B. Kahng, and Liangzhen Lai. "Synthesis and Analysis of Design-Dependent Ring Oscillator (DDRO) Performance Monitors." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, no. 10 (October 2014): 2117–30. http://dx.doi.org/10.1109/tvlsi.2013.2282742.

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45

Sharma, Gaurav Kumar, Arun Kishor Johar, Tangudu Bharat Kumar, and Dharmendar Boolchandani. "Effectiveness of Taguchi and ANOVA in design of differential ring oscillator." Analog Integrated Circuits and Signal Processing 104, no. 3 (June 15, 2020): 331–41. http://dx.doi.org/10.1007/s10470-020-01671-4.

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46

R, Swetha, J. Manjula, and A. Ruhan bevi. "Design of All Digital Phase Locked Loop for Wireless Applications." International Journal of Engineering & Technology 7, no. 3.12 (July 20, 2018): 836. http://dx.doi.org/10.14419/ijet.v7i3.12.16513.

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This paper presents a design of All Digital Phase Locked Loop (ADPLL) for wireless applications. It is designed using master and slave Dflipflop for linear phase detector, counter based loop filter and ring oscillator based Digital controlled oscillator(DCO). The programmable divider is used in the feed-back loop which is used has a frequency synthesizer for wireless applications. It is implemented in 180nm CMOS technology in Cadence EDA tool. The proposed ADPLL has locking period of 50ps and the operating frequency range of 4.7GHz and power consumption of 26mW.

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47

Dash, Sandeep K., Bishnu Prasad De, Pravin K. Samanta, Bhargav Appasani, Rajib Kar, Durbadal Mandal, and Nicu Bizon. "Optimal Design of Voltage Reference Circuit and Ring Oscillator Circuit Using Multiobjective Differential Evolution Algorithm." Journal of Electrical and Computer Engineering 2023 (August 8, 2023): 1–11. http://dx.doi.org/10.1155/2023/7621594.

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This paper deals with the optimal design of different VLSI circuits, namely, the CMOS voltage reference circuit and the CMOS ring oscillator (RO). The optimization technique used here is the multiobjective differential evolution algorithm (MDEA). All the circuits are designed for 90 nm technology. The main objective of the CMOS voltage reference circuit is to minimize the voltage variation at the output. The targeted value of the reference voltage is 550 mV. A CMOS ring oscillator (RO) is designed depending on the performance parameters such as power consumption and phase noise. The optimal transistor sizing of each circuit is obtained from MDEA. Each circuit is implemented in SPICE by taking the optimal dimensions of the transistors, and the performance parameters are achieved. The designed voltage reference circuit achieves a reference voltage of 550 mV with 600 nW power dissipation. The reference voltage variation of 8.18% is observed due to temperature variation from −40°C to + 125°C. The MDEA-based optimal design of RO oscillates at 2.001 GHz frequency, has a phase noise of −87 dBc/Hz at 1 MHz offset frequency, and consumes 71 μW power. This work mainly aims to optimize the MOS transistors’ sizes using MDEA for better circuit performance parameters. SPICE simulation has been carried out by using the optimal values of MOS transistor sizes to exhibit the performance parameters of the circuit. Simulation results establish that design specifications are closely met. SPICE results show that MDEA is a better technique for the optimal design of the above-mentioned VLSI circuits.

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48

Kitagawa, Akio. "Design and Characterization of Nano-Displacement Sensor with High-Frequency Oscillators." Journal of Sensors 2011 (2011): 1–5. http://dx.doi.org/10.1155/2011/360173.

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The circuitry of a capacitive nanometer displacement sensor using the ring oscillator has been analyzed and characterized. We focus on the sensitivity of the sensor to detect the nanometer displacement or strain. The displaced target object must be conductive and the medium around the target object must be an insulator or a vacuum. The sensitivity in the range ofL< 1 μm is enhanced with decreases in the size of the sensor electrode, and using a higher free-running oscillation frequency can increase sensitivity. The proposed sensor, which converts the displacement of the target object to the oscillation frequency, was fabricated with CMOS 350 nm technology, and the sensitivity was estimated at 8.16 kHz/nm. The results of our study indicated that the presented sensor has enough sensitivity to detect the nanometer displacement of the target object at a distance within 1 μm from the surface of the sensor electrode.

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Lanni, Luigia, Bengt Gunnar Malm, Mikael Östling, and Carl Mikael Zetterling. "ECL-Based SiC Logic Circuits for Extreme Temperatures." Materials Science Forum 821-823 (June 2015): 910–13. http://dx.doi.org/10.4028/www.scientific.net/msf.821-823.910.

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Integrated digital circuits, fabricated in a bipolar SiC technology, have been successfully tested up to 600 °C. Operated with-15 V supply voltage from 27 up to 600 °C OR-NOR gates exhibit stable noise margins of about 1 or 1.5 V depending on the gate design, and increasing delay-power consumption product in the range 100 - 200 nJ. In the same temperature range an oscillation frequency of about 1 MHz is also reported for an 11-stage ring oscillator.

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YAMAPI, R., and M. A. AZIZ-ALAOUI. "STABILITY OF THE CONTROLLED SYNCHRONIZATION MANIFOLD IN A RING OF MUTUALLY COUPLED CHAOTIC SYSTEMS." International Journal of Bifurcation and Chaos 18, no. 08 (August 2008): 2397–414. http://dx.doi.org/10.1142/s0218127408021774.

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The active control of the unstable synchronization manifold in a shift-invariant ring of N mutually coupled chaotic oscillators is investigated. After deriving the bifurcation structures and chaotic states in the single oscillator, we find the regime of coupling parameters leading to stable and unstable synchronization phenomena in the ring, using the Master stability function approach with the transverse Lyapunov exponents. The active control technique is applied on the mutually coupled chaotic systems to suppress unstable synchronization states. We derive the range of control gain parameters which leads to a successful control and the stability of the control design. The effects of the amplitude of the parametric perturbations on the stability boundaries of the controlled unstable synchronization process are also studied.

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