Relevant bibliographies by topics / Ripple carry

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  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Academic literature on the topic 'Ripple carry'

Author: Grafiati
Published: 4 June 2021
Last updated: 12 February 2022

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Journal articles on the topic "Ripple carry"

1

Chang, T. Y., and M. J. Hsiao. "Carry-select adder using single ripple-carry adder." Electronics Letters 34, no. 22 (1998): 2101. http://dx.doi.org/10.1049/el:19981706.

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THOMSEN, MICHAEL KIRKEDAL, and HOLGER BOCK AXELSEN. "PARALLELIZATION OF REVERSIBLE RIPPLE-CARRY ADDERS." Parallel Processing Letters 19, no. 02 (June 2009): 205–22. http://dx.doi.org/10.1142/s0129626409000171.

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The design of fast arithmetic logic circuits is an important research topic for reversible and quantum computing. A special challenge in this setting is the computation of standard arithmetical functions without the generation of garbage. Here, we present a novel parallelization scheme wherein m parallel k-bit reversible ripple-carry adders are combined to form a reversible mk-bit ripple-block carry adder with logic depth [Formula: see text] for a minimal logic depth [Formula: see text], thus improving on the mk-bit ripple-carry adder logic depth [Formula: see text]. The underlying mechanisms of the parallelization scheme are formally proven correct. We also show designs for garbage-less reversible comparison circuits. We compare the circuit costs of the resulting ripple-block carry adder with known optimized reversible ripple-carry adders in measures of circuit delay, width, gate, transistor count, and relative power efficiency, and find that the parallelized adder offers significant speedups at realistic word sizes with modest parallelization overhead.
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J, Lakshmesha, and K. R. Usha Rani. "A Novel Ripple/Carry Lookahead Hybrid Carry Select Adder Architecture." International Journal of Computer Applications 70, no. 27 (May 31, 2013): 5–9. http://dx.doi.org/10.5120/12237-8416.

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Ibrahim, Atef, and Fayez Gebali. "Optimized structures of hybrid ripple carry and hierarchical carry lookahead adders." Microelectronics Journal 46, no. 9 (September 2015): 783–94. http://dx.doi.org/10.1016/j.mejo.2015.06.008.

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Al-Smadi, Takialddin A., and Yasir K. Ibrahim . "Design of Speed Independent Ripple Carry Adder." Journal of Applied Sciences 7, no. 6 (March 1, 2007): 848–54. http://dx.doi.org/10.3923/jas.2007.848.854.

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AradhyaH.V, Ravish, Lakshmesha J, and Muralidhara K. N. "Reduced Complexity Hybrid Ripple Carry Lookahead Adder." International Journal of Computer Applications 70, no. 28 (May 31, 2013): 13–16. http://dx.doi.org/10.5120/12254-8202.

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., Y. Anil Kumar. "A HIGH SPEED DYNAMIC RIPPLE CARRY ADDER." International Journal of Research in Engineering and Technology 04, no. 08 (August 25, 2015): 438–42. http://dx.doi.org/10.15623/ijret.2015.0408075.

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V. Pavan Kumar, B., P. Sri Ashish, K. Sai Harshitha, G. Sai Krishna, and T. Anil chowdary. "Testing ripple carry adder using bist architecture." International Journal of Engineering & Technology 7, no. 2.7 (March 18, 2018): 834. http://dx.doi.org/10.14419/ijet.v7i2.7.11077.

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Very Large-Scale Integration has a greater impact on the developing circuit technology. The Cost and Size has been gradually reducing since years but increased the circuit complexity, there are problems which may affect the growth of VLSI technology. Among them one of major problem is circuit testing. To resolve this issue, we implement Built in Self-Test (BIST). BIST architecture is used to test the circuit itself. Engineers Design BIST to achieve high reliability and low repair cycle times. We implement Linear Feedback Shift Registers (LFSR) to generate the pseudo random test pattern and implement a ripple carry adder as circuit under test and Multiple Input Signature Register(MISR) as output response analyzer and test patterns are given to circuit under test and outputs are obtained these are compared with the actual outputs to test whether the circuit is faulty or not. To check whether the circuit is faulty or fault free we check the obtained outputs with actual outputs using Signature Analysis.
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SUZUKI, H., W. JEONG, and K. ROY. "Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders." IEICE Transactions on Electronics E90-C, no. 4 (April 1, 2007): 865–76. http://dx.doi.org/10.1093/ietele/e90-c.4.865.

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FAGHIH MIRZAEE, Reza, and Keivan NAVI. "Optimized Adder Cells for Ternary Ripple-Carry Addition." IEICE Transactions on Information and Systems E97.D, no. 9 (2014): 2312–19. http://dx.doi.org/10.1587/transinf.2013lop0007.

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Dissertations / Theses on the topic "Ripple carry"

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Jang, Yi-Feng. "On the design of reconfigurable ripple carry adders and carry save multipliers." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-06162009-063006/.

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Wei, Lan. "Implementation of Pipelined Bit-parallel Adders." Thesis, Linköping University, Department of Electrical Engineering, 2003. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1943.

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Bit-parallel addition can be performed using a number of adder structures with different area and latency. However, the power consumption of different adder structures is not well studied. Further, the effect of pipelining adders to increase the throughput is not well studied. In this thesis four different adders are described, implemented in VHDL and compared after synthesis. The results give a general idea of the time-delay-power tradeoffs between the adder structures. Pipelining is shown to be a good technique for increasing the circuit speed.

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Åslund, Anders. "Power Estimation of High Speed Bit-Parallel Adders." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2390.

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Fast addition is essential in many DSP algorithms. Various structures have been introduced to speed up the time critical carry propagation. For high throughput applications, however, it may be necessary to introduce pipelining. In this report the power consumption of four different adder structures, with varying word length and different number of pipeline cuts, is compared.

Out of the four adder structures compared, the Kogge-Stone parallel prefix adder proves to be the best choice most of the time. The Brent-Kung parallel prefix adder is also a good choice, but the maximal throughput does not reach as high as the maximal throughput of the Kogge-Stone parallel prefix adder.

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Fang, Chih-Jen, and 方智仁. "Fast and Compact Dynamic Ripple Carry Adder Design." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/30444709334677092076.

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碩士
國立中正大學
電機工程研究所
90
Adders are fundamental building blocks and often constitute part of the critical path. The maximum operating speed of a Ripple Carry Adder (RCA) is limited by the carry propagation delay, and the penalty of the propagation delay depends on the number of primary input bits. In this paper, we propose four high-speed and compact ripple carry adder designs. The key techniques of these novel designs are race-free dynamic CMOS logic technique for high-speed and compact designs. We demonstrate these designs approach using a 32-bit ripple carry adder built with the TSMC 0.25-um CMOS technology. The adder operates at 2.5V. The SPICE simulation shows that the proposed Dynamic Ripple Carry Adders (DRCAs) are at least 2.38 times faster than the conventional static ripple carry adder (SRCA). Further all of the proposed designs compare much favorably to the previous DRCA design that employs the DCVS logic.
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Book chapters on the topic "Ripple carry"

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Weik, Martin H. "ripple carry." In Computer Science and Communications Dictionary, 1497. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_16426.

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Mohan, Shoba, and Nakkeeran Rangaswamy. "Design of Ripple Carry Adder Using GDI Logic." In Proceedings of the International Conference on Soft Computing Systems, 529–35. New Delhi: Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2671-0_51.

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Sridharan, K., and Vikramkumar Pudi. "Design of Ripple Carry and Prefix Adders in QCA." In Studies in Computational Intelligence, 27–55. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-16688-9_4.

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Johansson, Kenny, Oscar Gustafsson, and Lars Wanhammar. "Power Estimation for Ripple-Carry Adders with Correlated Input Data." In Lecture Notes in Computer Science, 662–74. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30205-6_68.

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Kishore, Pinninti, P. V. Sridevi, and K. Babulu. "Low Power and Optimized Ripple Carry Adder and Carry Select Adder Using MOD-GDI Technique." In Lecture Notes in Electrical Engineering, 159–71. New Delhi: Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2728-1_15.

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Mewada, Manan, Mazad Zaveri, and Anurag Lakhlani. "Estimating the Maximum Propagation Delay of 4-bit Ripple Carry Adder Using Reduced Input Transitions." In Communications in Computer and Information Science, 15–23. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-7470-7_2.

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Datta, Kakali, Debarka Mukhopadhyay, and Paramartha Dutta. "Design of Ripple Carry Adder Using 2-Dimensional 2-Dot 1-Electron Quantum-Dot Cellular Automata." In Advances in Intelligent Systems and Computing, 263–70. New Delhi: Springer India, 2016. http://dx.doi.org/10.1007/978-81-322-2755-7_27.

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Roy, Rupsa, Swarup Sarkar, and Sourav Dhar. "Physical Design and Implementation of Multibit Multilayer 3D Reversible Ripple Carry Adder Using “QCA-ES” Nanotechnique." In Advances in Communication, Devices and Networking, 37–50. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-2911-2_5.

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Saxena, Naman, Shruti Dutta, Neeta Pandey, and Kirti Gupta. "Implementation and Performance Comparison of a Four-Bit Ripple-Carry Adder Using Different MOS Current Mode Logic Topologies." In Computational Science and Its Applications – ICCSA 2017, 299–313. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-62407-5_21.

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Gupta, Priya, Anu Gupta, and Abhijit Asati. "Detailed Analysis of Ultra Low Power Column Compression WALLACE and DADDA Multiplier in Sub-Threshold Regime." In Advances in Computational Intelligence and Robotics, 78–123. IGI Global, 2016. http://dx.doi.org/10.4018/978-1-4666-9474-3.ch004.

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In this chapter, the design and comparative analysis is done in between the most well-known column compression multipliers by Wallace and Dadda in sub-threshold regime. In order to reduce the hardware which ultimately reduces area, power and overall power delay product, an energy efficient basic modules of the multipliers like AND gates, half adders, full adders and partial product generate units have been analyzed for sub-threshold operation. At the last stage ripple carry adder is used in both multipliers. The performance metrics considered for the analysis of the multipliers are: power, delay and PDP. Simulation studies are carried out for 8x8-bit and 16x16-bit input data width. The proposed circuits show energy efficient results with Spectre simulations for the TSMC 180nm CMOS technology at 0.4V supply voltage. The proposed multipliers so implemented outperform its counterparts exhibiting low power consumption and lesser propagation delay as compared to conventional multipliers.
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Conference papers on the topic "Ripple carry"

1

Balasubramanian, P., C. Dang, D. L. Maskell, and K. Prasad. "Approximate ripple carry and carry lookahead adders — A comparative analysis." In 2017 IEEE 30th International Conference on Microelectronics (MIEL). IEEE, 2017. http://dx.doi.org/10.1109/miel.2017.8190125.

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Guckert, Lauren, and Earl Swartzlander. "Optimized memristor-based ripple carry adders." In 2016 50th Asilomar Conference on Signals, Systems and Computers. IEEE, 2016. http://dx.doi.org/10.1109/acssc.2016.7869644.

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Lau, Mark S. K., Keck Voon Ling, Yun Chung Chu, and Arun Bhanu. "Modeling of Probabilistic Ripple-Carry Adders." In 2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications. IEEE, 2010. http://dx.doi.org/10.1109/delta.2010.14.

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Bishnoi, Bhupesh, M. Giridhar, Bahniman Ghosh, and M. Nagaraju. "Ripple carry adder using five input majority gates." In 2012 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC). IEEE, 2012. http://dx.doi.org/10.1109/edssc.2012.6482894.

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Fawaz, Mohammad, Nader Kobrosli, Jessica Rizakallah, Mohammad Mansour, Ali Chehab, Ayman Kayssi, and Hazem Hajj. "Energy minimization feedback loop for ripple carry adders." In 2010 International Conference on Energy Aware Computing (ICEAC). IEEE, 2010. http://dx.doi.org/10.1109/iceac.2010.5702297.

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PAVLIDIS, V., D. SOUDRIS, and A. THANAILAKIS. "THE DESIGN OF A RIPPLE CARRY ADIABATIC ADDER." In Papers Presented at MMN 2000. WORLD SCIENTIFIC, 2001. http://dx.doi.org/10.1142/9789812810861_0075.

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Lau, Mark S. K., Keck-Voon Ling, Yun-Chung Chu, and Arun Bhanu. "A general mathematical model of probabilistic ripple-carry adders." In 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010). IEEE, 2010. http://dx.doi.org/10.1109/date.2010.5456973.

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Burgess, Neil. "Fast Ripple-Carry Adders in Standard-Cell CMOS VLSI." In 2011 IEEE 20th Symposium on Computer Arithmetic (ARITH). IEEE, 2011. http://dx.doi.org/10.1109/arith.2011.23.

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Bose, Avishek, Hafiz Md Hasan Babu, and Shalini Gupta. "Design of compact reversible online testable ripple carry adder." In 2015 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE). IEEE, 2015. http://dx.doi.org/10.1109/wiecon-ece.2015.7443992.

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Somani, Neelam, Chitrita Chaudhary, and Sharad Yadav. "Reversible adder design for ripple carry and carry look ahead (4, 8, 16, 32-bit)." In 2016 International Conference on Computing, Communication and Automation (ICCCA). IEEE, 2016. http://dx.doi.org/10.1109/ccaa.2016.7813935.

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