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Journal articles on the topic 'Ripple carry adder (RCA)'

Author: Grafiati

Published: 2 June 2025

Last updated: 31 July 2025

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1

Alkurwy, Salah Hasan, and Isam Salah Hameed. "A novel pipelined carry adder design based on half adder." Indonesian Journal of Electrical Engineering and Computer Science 25, no. 2 (2022): 763–70. https://doi.org/10.11591/ijeecs.v25.i2.pp763-770.

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A new design of binary parallel adder circuit is presented in this paper. The pipeline technique is applied to implement a group of a half adder (HA) blocks to architect the proposed adder. The pipelined carry adder (PCA) method is suitable for carrying out the desired adder by using the HA circuits of XOR and AND gates. The applied technique reduces the critical path delay by 27% compared with the ripple carry adder (RCA) and relatively lowers logic gates by 55% compared with the carry look-ahead adder (CLA). The coded design of the proposed circuit is implemented and simulated on the Cyclone

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2

Dr., Anuradha M. Sandi. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (2019): 40–50. https://doi.org/10.5281/zenodo.3245207.

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In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increas

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3

Joseph, Neenu, Ashker Assis, Arjun Bibin, Aromal A., and Thanzeel A R. "FPGA Based 32-Bit Hybrid Ripple Ling Carry Adder." Journal of Electronics and Informatics 7, no. 2 (2025): 177–90. https://doi.org/10.36548/jei.2025.2.008.

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The 32-bit Hybrid Ripple Ling carry adder uses a Ling-based parallel prefix adder for the upper 16 bits and a ripple-carry adder (RCA) for the lower 16 bits to optimize performance, power, and area efficiency for VLSI designs. While the Ling adder speeds up carry propagation for larger bits, the RCA minimizes area and power for smaller bit-widths. This hybrid structure offers high-speed, low-power operation while saving 12% power, 30%–40% area, and a worst-case delay of 0.182 ns in a 28 nm process. The adder employs a Ling-based parallel prefix topology for the higher-order bits. A re-expressi

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4

Kamaraju, M., P. Ashok Babu, P. Himasri, and S. Akshitha. "Power and Area Efficient Four-Bit Vedic Multiplier Implemented Using a Modified Five-Bit Adder with CMOS and TG Configuration." Journal of Controller and Converters 9, no. 1 (2024): 27–36. http://dx.doi.org/10.46610/jcc.2024.v090i01.005.

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Vedic multipliers are incredibly fast, efficient, and flexible, perfect for efficiently handling tasks like signal processing. Vedic multipliers are the go-to choice for maximizing performance and efficiency in digital designs, as the existing method adders like Carry Look-Ahead Adder (CLA), a Carry Skip Adder (CSA), or a Ripple Carry Adder (RCA) have more delay, area and power. The project proposal presents a novel 4-bit Vedic multiplier essential to system functionality. Optimizing the balancing area and delay is necessary for improving the system as a whole. This project aims to strike this

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5

Maroju, SaiKumar, and P. Samundiswary Dr. "Design and Performance Analysis of Various Adders using Verilog." International Journal of Computer Science and Mobile Computing 2, no. 9 (2013): 128–38. https://doi.org/10.5281/zenodo.32564.

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Adders are one of the most widely digital components in the digital integrated circuit design and are the necessary part of Digital Signal Processing (DSP) applications. With the advances in technology, researchers have tried and are trying to design adders which offer either high speed, low power consumption, less area or the combination of them. In this paper, the design of various adders such as Ripple Carry Adder (RCA), Carry Skip Adder (CSkA), Carry Increment Adder (CIA), Carry Look Ahead Adder (CLaA), Carry Save Adder (CSA), Carry Select Adder (CSlA), Carry Bypass Add

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6

Sandi, Anuradha. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (2020): 40–50. http://dx.doi.org/10.29121/ijetmr.v6.i6.2019.392.

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In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increas

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7

Ali, Mohamed Syed. "Cascaded Ripple Carry Adder Based SRCSA for Efficient FIR Filter." Indonesian Journal of Electrical Engineering and Computer Science 9, no. 2 (2018): 253. http://dx.doi.org/10.11591/ijeecs.v9.i2.pp253-256.

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<p>Filter is one of the key components of all signals processing elements. Both the FIR and IIR filter are used to reduce the unwanted signal in the original signal. Here discussing the FIR filter and design the efficient FIR filter using Dual Ripple Carry Adder (RCA) based SQRT-carry select adder (CSLA). Many components present in the FIR filter, one of the main component is Adder. Adder is used to combine the signal for avoid the noise occurring in the output. Proposed a Dual RCA based SQRT-CSLA for speed up the filtering process. The filter performance can be analyzed by Xilinx simula

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8

Mohamed, Syed Ali. "Cascaded Ripple Carry Adder based SRCSA for Efficient FIR Filter." Indonesian Journal of Electrical Engineering and Computer Science 9, no. 2 (2018): 253–56. https://doi.org/10.11591/ijeecs.v9.i2.pp253-256.

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Filter is one of the key components of all signals processing elements. Both the FIR and IIR filter are used to reduce the unwanted signal in the original signal. Here discussing the FIR filter and design the efficient FIR filter using Dual Ripple Carry Adder (RCA) based SQRT-carry select adder (CSLA). Many components present in the FIR filter, one of the main component is Adder. Adder is used to combine the signal for avoid the noise occurring in the output. Proposed a Dual RCA based SQRT-CSLA for speed up the filtering process. The filter performance can be analyzed by Xilinx simulation envi

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9

Hoe, David H. K., L. P. Deepthi Bollepalli, and Chris D. Martinez. "FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders." VLSI Design 2013 (November 7, 2013): 1–10. http://dx.doi.org/10.1155/2013/382682.

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This paper examines fault tolerant adder designs implemented on FPGAs which are inspired by the methods of modular redundancy, roving, and gradual degradation. A parallel-prefix adder based upon the Kogge-Stone configuration is compared with the simple ripple carry adder (RCA) design. The Kogge-Stone design utilizes a sparse carry tree complemented by several smaller RCAs. Additional RCAs are inserted into the design to allow fault tolerance to be achieved using the established methods of roving and gradual degradation. A triple modular redundant ripple carry adder (TMR-RCA) is used as a point

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10

Alkurwy, Salah Hasan, and Isam Salah Hameed. "A novel pipelined carry adder design based on half adder." Indonesian Journal of Electrical Engineering and Computer Science 25, no. 2 (2022): 763. http://dx.doi.org/10.11591/ijeecs.v25.i2.pp763-770.

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<span lang="EN-US">A new design of binary parallel adder circuit is presented in this paper. The pipeline technique is applied to implement a group of a half adder (HA) blocks to architect the proposed adder. The pipelined carry adder (PCA) method is suitable for carrying out the desired adder by using the HA circuits of XOR and AND gates. The applied technique reduces the critical path delay by 27% compared with the ripple carry adder (RCA) and relatively lowers logic gates by 55% compared with the carry look-ahead adder (CLA). The coded design of the proposed circuit is implemented and

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11

S., Sandeep, and Kiran V. "SYNTHESIS AND FPGA VALIDATION OF PARALLEL PREFIX ADDERS." International Journal of Advanced Research 10, no. 10 (2022): 708–17. http://dx.doi.org/10.21474/ijar01/15539.

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In this work, the design implementation, functionality testing, design synthesis and bitstream generation of various n-bit adder architecture of RCA, CLA, CSkA and KSA. And addresses various forms of adders which include Ripple-carry (RCA), Carry-lookahead (CLA), Carry-skip (CSkA), and Kogge-stone (KSA) adders. Certain design restrictions for digital VLSI circuits, such speed and area, can be satisfied using these adders. All the mentioned adder are designed using Verilog HDL, implemented the same on Xilinx Vivado 2018.2, functionality test is carried out by writing testbench, bitstream genera

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12

Akbar, Muhammad Ali, Bo Wang, and Amine Bermak. "A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization." Electronics 10, no. 15 (2021): 1791. http://dx.doi.org/10.3390/electronics10151791.

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Ripple-carry adder (RCA) is among the most common type of adder. However, it is not preferred in many applications because of its high latency. In this paper, two architectures of high-speed parallel RCA (PRCA) along with fault detection and localization are proposed, with reduced overhead as compared with carry look-ahead adder (CLA). In the proposed approach, RCA is divided into blocks, where the initial carry input for each block will be generated by a carry look-ahead logic unit. The delay is reduced by 43.81% as compared with the conventional 64-bit RCA design. The delay is further reduce

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13

Venkat, D., Tanya Mendez, Rashmi Samanth, and Subramanya G. Nayak. "Novel Design of Ripple Carry Adder using High Speed 12T Hybrid MOS Transistors." Journal of Physics: Conference Series 2571, no. 1 (2023): 012025. http://dx.doi.org/10.1088/1742-6596/2571/1/012025.

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Abstract This paper designs and extends a high speed full adder using 12 MOS Transistors to a ripple carry adder (RCA). The proposed design reduces delay and is effective for Power Delay Product (PDP). Using both complementary MOSFET (CMOS) logic and complementary pass transistor logic(CPL), a new 6T XNOR full adder(FA) is created. CPL is used in the design for Carry and Sum logic in order to minimise circuit delay. The proposed work has a delay of 11.86 ps and a PDP of 0.368fj. By using a newly proposed single bit adder, a 4-bit Ripple Carry Adder(RCA) is designed with 1.2 v supply yielding a

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14

M. B., Veena, and Shreya S. K. "Implementation of Ripple Carry Adder and Carry Save Adder using 7nm FinFET Technology." WSEAS TRANSACTIONS ON ELECTRONICS 14 (December 31, 2023): 163–69. http://dx.doi.org/10.37394/232017.2023.14.20.

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The semiconductor industry’s continuous effort to miniaturize and be more powerful to increase the overall performance. This has led to the use of FinFET technology for packing more transistors into a smaller space and using power more efficiently compared to planner MOS technologies. Compared to the MOS technology, FinFET technology provides better advantages such as improved transistor performance, lower leakage currents, and enhanced power efficiency. The proposed work includes integrating fundamental components like the NAND gate, 2:1 MUX, and full adder (FA). These components are combined

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15

T, Raju, Pradeep Kumar A, Venkata Thriveni S, Pallavi T, and G. Mani. "Design and Implementation of Hybrid Full Adder-Based Ripple Carry Adder for Low Power Applications." International Journal for Modern Trends in Science and Technology 11, no. 03 (2025): 207–13. https://doi.org/10.5281/zenodo.15093734.

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<em>Full adders are fundamental components in various applications, including Digital Signal Processors (DSPs) and microprocessors. In modern circuit design, reducing supply voltage has become a key approach to minimizing energy consumption. Since the full adder serves as a primary arithmetic unit in many computational tasks, it plays a crucial role in the efficiency of the Arithmetic Logic Unit (ALU). This project introduces novel hybrid full adder designs aimed at achieving low Power-Delay Product (PDP). Additionally, a Ripple Carry Adder (RCA) is proposed using a chain structure to enhance

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16

E.Kumar, M.Surekha, B.Jagadeesh, P.Venkata Sai Ramakrishna, N.V.S.S Sujith, and B.Manjunadha. "Design and Implementation of Area Efficient 16-bit Carry Skip Adder." international journal of engineering technology and management sciences 7, no. 2 (2023): 339–44. http://dx.doi.org/10.46647/ijetms.2023.v07i02.041.

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Adders are fundamental unit in many computer systems. One of the most efficient adder architectures in terms of delay and area is the carry-skip adder. In this paper an area efficient 16-bit carry-skip adder to achieve high speed and low area were designed. CSA is a rapid adder that is used in data processing systems to execute quick arithmetic operations. As a result, a Modified Carry Skip Adder (MCSA) is developed using a single Ripple Carry Adder (RCA) and a Binary to Excess-1 Converter (BEC) instead of twin RCAs to save size while sacrificing speed. The design is coded in VHDL and its area

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17

Cheng, Wei, and jianping Hu. "A Structured Approach for Optimizing 4-Bit Carry-Lookahead Adder." Open Electrical & Electronic Engineering Journal 8, no. 1 (2014): 133–42. http://dx.doi.org/10.2174/1874129001408010133.

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This paper presents a comparative research of low-power and high-speed 4-bit full adder circuits. The representative adders used are a ripple carry adder (RCA) and a carry-lookahead adder (CLA). We also design a proposed carrylookahead adder (PCLA) using a new method that uses NAND gate for modification which helps in reducing the powerdelay product (PDP) for high performance applications. To yield more realistic rise and fall times in the simulations, layouts have been made in a 0.13 􀀁m process for the RCA circuit, CLA circuit and PCLA circuit. The layouts designed were simulated by HSPICE ba

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18

Rupsa Roy, Swarup Sarkar,. "QCA based Novel Reversible Reconfigurable Ripple Carry Adder with Ripple Borrow Subtractor in Electro-Spin Technology." Psychology and Education Journal 58, no. 2 (2021): 813–23. http://dx.doi.org/10.17762/pae.v58i2.1916.

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An important arithmetic component of “Arithmetic and Logic Unit” or ALU is reconfigured in this paper, known as “Full-Adder-Subtractor”, where an advance low-power, high-speed nano technology “QCA” with electro-spin criterion is used with reversibility and the advancement of multilayer 3D circuitry. In this modern digital world, this selected nano-sized technology is an effective alternative of widely used “CMOS Technology” because all the limitations, mainly limitation due to the presence of high power dissipation at the time of device-density increment in a “CMOS” based integrated circuit, c

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19

Gharajeh, Mohammad, and Majid Haghparast. "Novel reversible CLA, optimized RCA and parallel adder/subtractor circuits." Serbian Journal of Electrical Engineering 17, no. 3 (2020): 259–83. http://dx.doi.org/10.2298/sjee2003259g.

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This paper proposes reversible circuit designs of the three most commonly used adders: carry look-ahead adder (CLA adder), ripple carry adder (RCA adder), and parallel adder/subtractor. The n-bit reversible CLA adder, called CLA-GH, is designed using the Peres and Fredkin gates. The n-bit optimized reversible RCA adder, called ORCA-GH, is designed using the reversible circuit of a parity-preserving reversible full adder. Both circuits reduce the quantum cost. However, the ORCA-GH circuit also improves the number of constant inputs. Furthermore, the n-bit reversible parallel adder/subtractor, c

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20

Balasubramanian, Padmanabhan, and Nikos Mastorakis. "Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions." Electronics 7, no. 12 (2018): 369. http://dx.doi.org/10.3390/electronics7120369.

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Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing bi

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21

Saini, Vikas K., Shamim Akhter, and Tanuj Chauhan. "Implementation, Test Pattern Generation, and Comparative Analysis of Different Adder Circuits." VLSI Design 2016 (June 8, 2016): 1–8. http://dx.doi.org/10.1155/2016/1260879.

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Addition usually affects the overall performance of digital systems and an arithmetic function. Adders are most widely used in applications like multipliers, DSP (i.e., FFT, FIR, and IIR). In digital adders, the speed of addition is constrained by the time required to propagate a carry through the adder. Various techniques have been proposed to design fast adders. We have derived architectures for carry-select adder (CSA), Common Boolean Logic (CBL) based adders, ripple carry adder (RCA), and Carry Look-Ahead Adder (CLA) for 8-, 16-, 32-, and 64-bit length. In this work we have done comparativ

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22

Rout, Shasanka Sekhar, Rajesh Kumar Patjoshi, Sarmila Garnaik, and Ranjita Rout. "Comparative Analysis of Heterogeneous Adders: Evaluating Performance across 12-bit, 14-bit, and 16-bit Configurations." Journal of Information Assurance and Security 19, no. 4 (2024): 136–45. https://doi.org/10.2478/ias-2024-0010.

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Abstract Digital Signal Processing (DSP) heavily relies on repetitive addition and multiplication operations, making adders a crucial component in DSP systems. Likewise, in processor design, an efficient adder circuit is essential for optimizing compactness, achieving high speed, and minimizing power consumption, particularly when utilizing Xilinx technology. This study delves into the exploration and design of an effective adder architecture by examining various parallel, synchronous adders and proposing a novel combination. The presented research introduces heterogeneous adders composed of c

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23

Eppili, Jaya, Sri B. Sai, Kumar P. Akshay, Kumar O. Hem, D. Sunil, and R. Rajesh. "VLSI implementation of Kogge-Stone Adder for low-power applications." i-manager's Journal on Digital Signal Processing 11, no. 1 (2023): 9. http://dx.doi.org/10.26634/jdp.11.1.19372.

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The adder is a vital part of the Central Processing Unit (CPU) that can perform computational operations. It is used in digital components, mainly in the design of integrated circuits. Recent decades have seen a sharp rise in demand for mobile electronics, which has increased the need for highly efficient Very Large-Scale Integration (VLSI) structures. All operations must be computed using low-power, space-efficient designs that run faster. The Kogge-Stone adder (KSA) is an extension of the carry look-ahead adder which is used for performing fast addition in high-performance computing systems.

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24

Pallavi, Saxena, Purohit Urvashi, and Joshi Priyanka. "Design of Low Power, Area-Efficient Carry Select Adder." International Journal of Engineering Research & Technology 2, no. 10 (2013): 3582–86. https://doi.org/10.5281/zenodo.32569.

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Design of low power and area-efficient logic systems forms an integral part and largest areas of research in the field of VLSI Design. Addition is the most fundamental arithmetic operation. In this paper, a low power, area-efficient carry select adder is proposed. CSA is one of the fastest adders used in dataprocessing systems to perform fast arithmetic operation. Secondly, structure of carry select adder is such that there is scope of reducing the area and power consumption. Thirdly, there is scope to reduce the area by using some add-one scheme. So, a Modified Carry Select Adder(MCSA) is des

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25

Pallavi, Saxena, Purohit Urvashi, and Joshi Priyanka. "Design of Low Power, Area-Efficient Carry Select Adder." International Journal of Engineering Research & Technology 2, no. 10 (2013): 3582–86. https://doi.org/10.5281/zenodo.33081.

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Design of low power and area-efficient logic systems forms an integral part and largest areas of research in the field of VLSI Design. Addition is the most fundamental arithmetic operation. In this paper, a low power, area-efficient carry select adder is proposed. CSA is one of the fastest adders used in dataprocessing systems to perform fast arithmetic operation. Secondly, structure of carry select adder is such that there is scope of reducing the area and power consumption. Thirdly, there is scope to reduce the area by using some add-one scheme. So, a Modified Carry Select Adder(MCSA) is des

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26

Balasubramanian, Padmanabhan, and Douglas L. Maskell. "Monotonic Asynchronous Two-Bit Full Adder." Electronics 13, no. 9 (2024): 1717. http://dx.doi.org/10.3390/electronics13091717.

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Monotonic circuits are a class of input–output mode (IOM) asynchronous circuits that are relaxed compared to quasi-delay-insensitive (QDI) IOM asynchronous circuits in terms of signaling the completion of internal processing. Some recent works have demonstrated the superiority of monotonic logic over QDI logic for arithmetic circuits such as adders and multipliers. This paper presents a new monotonic asynchronous two-bit full adder (TFA) that can be duplicated and cascaded to form a ripple-carry adder (RCA). While an RCA is a slow adder with respect to synchronous design, with respect to IOM a

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27

Sana, Khan Anum, and Wairya Subodh. "Design and Analysis of Hybrid full adder Topology using Regular and Triplet Logic Design." International Journal of Innovative Technology and Exploring Engineering (IJITEE) 9, no. 12 (2020): 348–54. https://doi.org/10.35940/ijitee.L8024.1091220.

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In the recent era, voltage reduction procedure is gaining most attention for achieving minimum energy consumption. Full adder is the primary computational arithmetic block in numerous of the computing executions and hence is the critical component of ALU. Various existing full adders proposed in literature fail to accomplish low power delay product (PDP) and lacks driving strength when used in chains structure. In this paper two new hybrid full adders have been proposed with an aim to achieve low PDP. Further the paper proposes ripple carry adder (RCA) in chain structure using triplet design a

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28

Bhavani, M., M. Siva Kumar, and K. Srinivas Rao. "Delay Comparison for 16x16 Vedic Multiplier Using RCA and CLA." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 3 (2016): 1205. http://dx.doi.org/10.11591/ijece.v6i3.9457.

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<p>In any integrated chip compulsory adders are required because first they are fast and second are the less power consumption and delay. And at the same time multiplication process is also used in various applications. So as the speed of multiplier increases then the speed of processor also increases. And hence we are proposing the Vedic multiplier using these adders. Vedic multiplier is an ancient mathematics which uses mainly 16 sutras for its operation. In this project we are using “urdhva triyagbhyam” sutra to do our process. This paper proposes the Vedic multiplier using the adders

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Bhavani, M., M. Siva Kumar, and K. Srinivas Rao. "Delay Comparison for 16x16 Vedic Multiplier Using RCA and CLA." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 3 (2016): 1205. http://dx.doi.org/10.11591/ijece.v6i3.pp1205-1212.

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<p>In any integrated chip compulsory adders are required because first they are fast and second are the less power consumption and delay. And at the same time multiplication process is also used in various applications. So as the speed of multiplier increases then the speed of processor also increases. And hence we are proposing the Vedic multiplier using these adders. Vedic multiplier is an ancient mathematics which uses mainly 16 sutras for its operation. In this project we are using “urdhva triyagbhyam” sutra to do our process. This paper proposes the Vedic multiplier using the adders

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30

Mokhtari, Dariush, Abdalhossein Rezai, Hamid Rashidi, Faranak Rabiei, Saeid Emadi, and Asghar Karimi. "Design of novel efficient full adder architecture for Quantum-dot Cellular Automata technology." Facta universitatis - series: Electronics and Energetics 31, no. 2 (2018): 279–85. http://dx.doi.org/10.2298/fuee1802279m.

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In this paper the novel coplanar circuits for full adder implementation in Quantum-dot Cellular Automata (QCA) technology are presented. We propose a novel one-bit full adder circuit and then utilize this new circuit to implement novel four-bit Ripple Carry Adder (RCA) circuit in the QCA technology. The QCA Designer tool version 2.0.1 is utilized to implement the designed QCA full adder circuits. The implementation results show that the designed QCA full adder circuits have an improvement compared to other QCA full adder circuits.

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31

Bhati, Satyandra, Neeraj Sharma, and Meetu Nag. "Performance Analysis of High Speed and Low Power Binary Adders." IOP Conference Series: Materials Science and Engineering 1224, no. 1 (2022): 012026. http://dx.doi.org/10.1088/1757-899x/1224/1/012026.

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Abstract In all the arithmetic operations, addition is one of the most important and initial operations used in most of the mathematical equations. The operation is performed by many adders present in the digital world. These adders give us carries with preferred delay and power. The three main features like structure, logic, and compact circuit layout help design a better adder. This Paper aims to analyse and compare various additions for high-speed, low-power and fast calculation. The various adder designs seen in digital signal processing applications require computationally efficient addin

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32

Mei, Ong Shi, Thikra S. Dhahi, Siti Fatimah Abd Rahman, M. F. M. Fathil, Mohd Rosydi Zakaria, and Mohamad Adzhar Md Zawawi. "Improved Ripple Carry Adder with Reduced Delay and Low Power Consumption at Circuit Level using 180 nm Technology." Journal of Physics: Conference Series 3020, no. 1 (2025): 012001. https://doi.org/10.1088/1742-6596/3020/1/012001.

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Abstract Full adder (FA) is a crucial building block in very-large-scale integration and digital signal processing applications, serving as a versatile component for addition, multiplication, arithmetic logic unit construction, etc. Its importance necessitates the development of an efficient adder block. To achieve high speed and low power consumption, various approaches can be employed. This study aims to implement a 4-bit ripple carry adder (RCA) using conventional, Boolean simplification, Boolean simplification with transistor sizing, and modified-gate diffusion input (m-GDI) logic in Caden

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33

Balasubramanian, Padmanabhan, Douglas Maskell, and Nikos Mastorakis. "Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic." Electronics 7, no. 10 (2018): 243. http://dx.doi.org/10.3390/electronics7100243.

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Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-pha

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K N, Hemalatha, Aishwarya Kamakodi, A. Soppia, A. Poornima, and Sangeetha B G. "Design And Implementation Of 64-Bit Ripple Carry Adder And Ripple Borrow Subtractor Using Reversible Logic Gates." International Journal of Advanced Networking and Applications 13, no. 06 (2022): 5215–19. http://dx.doi.org/10.35444/ijana.2022.13607.

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Minimal power design is desirable for a range of applications, including the Internet of Things (IoT), quantum computing, and so on. The reversible logic approach is at the foundation of a new technique for designing minimal power digital logic circuits for quantum computing applications. The reversible logic circuit offers a whole new approach to quantum computer processing. Reversible logic gates-based devices will be in high demand for future computer technologies since they require less power. Reversible logic gates were used to design a ripple carry adder (RCA) and a ripple borrow subtrac

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Balasubramanian, Padmanabhan, and Douglas L. Maskell. "A Monotonic Early Output Asynchronous Full Adder." Technologies 11, no. 5 (2023): 126. http://dx.doi.org/10.3390/technologies11050126.

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This article introduces a novel asynchronous full adder that operates in an input–output mode (IOM), displaying both monotonicity and an early output characteristic. In a monotonic asynchronous circuit, the intermediate and primary outputs exhibit similar signal transitions as the primary inputs during data and spacer application. The proposed asynchronous full adder ensures monotonicity for processing data and spacer, utilizing dual-rail encoding for inputs and outputs, and corresponds to return-to-zero (RtZ) and return-to-one (RtO) handshaking. The early output feature of the proposed full a

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Hossain, Muhammad Saddam, and Farhadur Arifin. "Design and Evaluation of a 32-bit Carry Select Adder using 4-bit Hybrid CLA Adder." AIUB Journal of Science and Engineering (AJSE) 20, no. 2 (2021): 1–7. http://dx.doi.org/10.53799/ajse.v20i2.119.

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Adder circuits play a remarkable role in modern microprocessor. Adders are widely used in critical paths of arithmetic operation such as multiplication and subtraction. A Carry Select Adder (CSA) design methodology using a modified 4-bit Carry Look-Ahead (CLA) Adder has been proposed in this research. The proposed 4-bit CLA used hybrid logic style based logic circuits for Carry Generate (Gi) and Carry Propagate (Pi) functions in order to improve performance and reduce the number of transistor used. The modified 4-bit CLA is used as the basic unit for implementation of 32-bit CSA. The proposed

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Suguna, T., and M. Janaki Rani. "Analysis of Adiabatic Hybrid Full Adder and 32-Bit Adders for Portable Mobile Applications." International Journal of Interactive Mobile Technologies (iJIM) 14, no. 05 (2020): 73. http://dx.doi.org/10.3991/ijim.v14i05.13343.

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In VLSI, power optimization is the main criteria for all the portable mobile applications and developments because of its impact on system performance. The performance of an adder has significant impact on overall performance of a digital system. Adiabatic logic (AL), a new emerging research domain for optimizing the power in VLSI circuits with high switching activity is discussed, in this paper, for implementing the adder circuits. Various adiabatic logic styles full adder designs are reviewed and multiplexer based hybrid full adder topology is designed and implemented with ECRL and 2PASCL AL

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Vahabi, Mohsen, Ali Newaz Bahar, Akira Otsuki, and Khan A. Wahid. "Ultra-Low-Cost Design of Ripple Carry Adder to Design Nanoelectronics in QCA Nanotechnology." Electronics 11, no. 15 (2022): 2320. http://dx.doi.org/10.3390/electronics11152320.

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Due to the development of integrated circuits and the lack of responsiveness to existing technology, researchers are looking for an alternative technology. Quantum-dot cellular automata (QCA) technology is one of the promising alternatives due to its higher switch speed, lower power dissipation, and higher device density. One of the most important and widely used circuits in digital logic calculations is the full adder (FA) circuit, which actually creates the problem of finding its optimal design and increasing performance. In this paper, we designed and implemented two new FA circuits in QCA

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Sadeghi, Mohsen, Mahya Zahedi, and Maaruf Ali. "The Cascade Carry Array Multiplier – A Novel Structure of Digital Unsigned Multipliers for Low-Power Consumption and Ultra-Fast Applications." Annals of Emerging Technologies in Computing 3, no. 3 (2019): 19–27. http://dx.doi.org/10.33166/aetic.2019.03.003.

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This article presents a low power consumption, high speed multiplier, based on a lowest transistor count novel structure when compared with other traditional multipliers. The proposed structure utilizes 4×4-bit adder units, since it is the base structure of digital multipliers. The main merits of this multiplier design are that: it has the least adder unit count; ultra-low power consumption and the fastest propagation delay in comparison with other gate implementations. The figures demonstrate that the proposed structure consumes 32% less power than using the bypassing Ripple Carry Array (RCA)

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B Gowda, Ranjith, and R. M Banakar. "Design of high speed low power optimized square root BK adder." International Journal of Engineering & Technology 7, no. 2.12 (2018): 240. http://dx.doi.org/10.14419/ijet.v7i2.12.11289.

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Adder is a basic building block in almost all the digital circuits used in todays digital world. Adders are used for address calculation, incrementing operation, table indices calculations and many other operations in digital processors. These operations require fast adders with reasonable design cost. Ripple carry adder (RCA) is the cheapest and most straight forward design but takes more computation time. For high speed applications Carry Look-ahead Adder (CLA) is preferred, but it has the limitation of increase in the total area of the design. Hence an adder which compromise between these t

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Venkata Sudhakar, Chowdam, Suresh Babu Potladurty, and Prasad Reddy Karipireddy. "Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications." International Journal of Reconfigurable and Embedded Systems (IJRES) 14, no. 2 (2025): 398. https://doi.org/10.11591/ijres.v14.i2.pp398-411.

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<p>The multiplier is an essential component in real-time applications. Even though approximation arithmetic affects output accuracy in multipliers, it offers a realistic avenue to constructing power area and speed-efficient digital circuits. The approximation computing technique is commonly used in error-tolerant applications such as signal, image, and video processing. In this paper, approximate multipliers (AMs) are designed using both conventional and approximate half adders (A-HA) and full adders (A-FA), which are strategically placed to add partial products at the most significant b

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Mukunthan, P., N. C. Sendhilkumar, and R. Pitchai. "Design of New Reconfigurable Architecture for Implementing a Least Mean Square Finite Impulse Response Filter Using Borrow Select Subtraction (BSLS)." Journal of Computational and Theoretical Nanoscience 17, no. 4 (2020): 1943–48. http://dx.doi.org/10.1166/jctn.2020.8471.

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A design of reconfigurable architecture of FIR filter has been implemented using a Least Mean Square (LMS) adaptive filter. LMS adaptive filter is mainly sued for reducing the coefficients of the filter. Generally, a LMS filter contains normal adder, subtractor, mixer and a delay part. Most of the concepts deal with an adder namely Full Adder (FA), Ripple Carry Adder (RCA), Carry Select Adder (CSLA), etc., Instead of using CSLA; Borrow Select Subtractor (BSLS) is used in LMS filter architecture. By using BSLA LMS adaptive filter in a reconfigurable FIR filter architecture in the proposed schem

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Ahmed Khan, Imran. "Design and Implementation of Carbon Nano-tube based Full Adder at 32nm Technology for High Speed and Power Efficient Arithmetic Applications." Journal of Physics: Conference Series 2161, no. 1 (2022): 012050. http://dx.doi.org/10.1088/1742-6596/2161/1/012050.

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Abstract Due to physical, material, technological, power-thermal and economical difficulties, scaling of CMOS transistors will stop very soon. Due to efficiency of power and speed compared to CMOS transistors, Carbon Nano-tube transistors are best suitable element to design logic circuits. So, CNTFETS have been utilized in designing of proposed full adder (FA) and 4-bit ripple carry adder (RCA) in this paper. Proposed FA and RCA have been compared to rival designs on bases of power, speed and power-delay-product (PDP). FA and RCA circuits have been analysed with the variation of temperature fr

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Abbas, Abdulkareem Dawah. "Review of high-speed phase accumulator for direct digital frequency synthesizer." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 4 (2020): 4008. http://dx.doi.org/10.11591/ijece.v10i4.pp4008-4014.

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A review of high-speed pipelined phase accumulator (PA) is proposed in this paper. The detail explanation of ideas, methods and techniques used in previous researches to improve the PA throughput designs were surveyed. The Brent–Kung (BK) adder was modified in this paper to be applied in pipelined PA architecture. A comparison of different adder circuits, includes a modified BK, ripple carry adder (RCA), Kogge-Stone adder (KS) and other prefix adders were applied to architect the PA based on Pipeline technique. The presented pipelined PA design circuit with multiple frequency control word (FCW

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Abdulkareem, Dawah Abbas. "Review of high-speed phase accumulator for direct digital frequency synthesizer." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 4 (2020): 4008–14. https://doi.org/10.11591/ijece.v10i4.pp4008-4014.

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A review of high-speed pipelined phase accumulator (PA) is proposed in this paper. The detail explanation of ideas, methods and techniques used in previous researches to improve the PA throughput designs were surveyed. The Brent-Kung (BK) adder was modified in this paper to be applied in pipelined PA architecture. A comparison of different adder circuits, includes a modified BK, ripple carry adder (RCA), Kogge-Stone adder (KS) and other prefix adders were applied to architect the PA based on Pipeline technique. The presented pipelined PA design circuit with multiple frequency control word (FCW

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Seyedi, Saeid, and Hatam Abdoli. "Efficient design and implementation of approximate FA, FS, and FA/S circuits for nanocomputing in QCA." PLOS ONE 19, no. 9 (2024): e0310050. http://dx.doi.org/10.1371/journal.pone.0310050.

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Recently, there has been a lot of research in Quantum Cellular Automata (QCA) technology because it promises low power consumption, low complexity, low latency, and compact space. Simultaneously, approximate arithmetic, a new paradigm in computing, streamlines the computational process and emerges as a low-power, high-performance design approach for arithmetic circuits. Furthermore, the XOR gate has been widely used in digital design and is a basic building block that can be used in many upcoming technologies. The full adder (FA) circuit is a key component of QCA technology and is utilized in

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Kim, Aeyoung, Seong-Min Cho, Chang-Bae Seo, Sokjoon Lee, and Seung-Hyun Seo. "Quantum Modular Adder over GF(2n − 1) without Saving the Final Carry." Applied Sciences 11, no. 7 (2021): 2949. http://dx.doi.org/10.3390/app11072949.

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Addition is the most basic operation of computing based on a bit system. There are various addition algorithms considering multiple number systems and hardware, and studies for a more efficient addition are still ongoing. Quantum computing based on qubits as the information unit asks for the design of a new addition because it is, physically, wholly different from the existing frequency-based computing in which the minimum information unit is a bit. In this paper, we propose an efficient quantum circuit of modular addition, which reduces the number of gates and the depth. The proposed modular

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Swetha, Tarigoppula, Sravan K. Vittapu, Ravichand Sankuru, Balla Hindupriya, Bairagoni Anand, and Gangadi Chandra Vardhan Reddy. "Implementation of Area Efficient Carry Select Adder using Binary to Excess1 Code." Journal of VLSI Design and Signal Processing 9, no. 3 (2023): 29–36. http://dx.doi.org/10.46610/jovdsp.2023.v09i03.004.

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Adders are widely used as essential parts in the design of digital integrated circuits. The Carry Select Adder (CSA) is unique among conventional adder topologies in that it operates quickly. There is a need for speedier arithmetic units as well as ones that use less power and take up less space as the mobile sector grows quickly. The Carry-Select method for adder design with carry propagation achieves a good trade-off between performance and cost. However, because it uses two ripple carry adders (RCA), the traditional CSA design still has a significant area overhead. A Binary to Excess-1 code

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Sato, Tomoaki, Sorawat Chivapreecha, Phichet Moungnoul, and Kohji Higuchi. "RCA on FPGAs Designed by RTL Design Methodology and Wave-Pipelined Operation." ECTI Transactions on Computer and Information Technology (ECTI-CIT) 11, no. 1 (2017): 10–19. http://dx.doi.org/10.37936/ecti-cit.2017111.65680.

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Field-programmable gate arrays (FPGAs) are used in various systems with reconfigurable functions. Conventional FPGAs have been developed using a transistor level description for minimizing routing delay. Although FPGAs developed with a register transfer level (RTL) design methodology provide various benefits to the designers of a system-on-a-chip (SoC), they have not been realized. Therefore, the authors advanced their development. They should be shown to operate with practical throughput. For this purpose, circuits on these device need to be designed and evaluated. In this paper, a ripple-car

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Malti, Aryanan, and Singh Chauhan Jaikaran. "Design Area-Efficient and high speed 32bit CSLA." International Journal of advancement in electronics and computer engineering 4, no. 8 (2015): 555–59. https://doi.org/10.5281/zenodo.45401.

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Modern applications demand extremely less area budgets and enhanced speed in computer architectures for battery-operated devices like Laptop and others. In this thesis, the main focus is on the area and provides high speed to the processors. Less area and high speed circuits are becoming more desirable due to growing portable device markets and they are also becoming more applicable today in processors. The main focus in this work is to improve the speed of the 32-bit processor and in this case the carry select adder is the better choice. The second concern in the design of this carry select a

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