Journal articles: 'Ripple carry'

1

Chang, T. Y., and M. J. Hsiao. "Carry-select adder using single ripple-carry adder." Electronics Letters 34, no. 22 (1998): 2101. http://dx.doi.org/10.1049/el:19981706.

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THOMSEN, MICHAEL KIRKEDAL, and HOLGER BOCK AXELSEN. "PARALLELIZATION OF REVERSIBLE RIPPLE-CARRY ADDERS." Parallel Processing Letters 19, no. 02 (June 2009): 205–22. http://dx.doi.org/10.1142/s0129626409000171.

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The design of fast arithmetic logic circuits is an important research topic for reversible and quantum computing. A special challenge in this setting is the computation of standard arithmetical functions without the generation of garbage. Here, we present a novel parallelization scheme wherein m parallel k-bit reversible ripple-carry adders are combined to form a reversible mk-bit ripple-block carry adder with logic depth [Formula: see text] for a minimal logic depth [Formula: see text], thus improving on the mk-bit ripple-carry adder logic depth [Formula: see text]. The underlying mechanisms of the parallelization scheme are formally proven correct. We also show designs for garbage-less reversible comparison circuits. We compare the circuit costs of the resulting ripple-block carry adder with known optimized reversible ripple-carry adders in measures of circuit delay, width, gate, transistor count, and relative power efficiency, and find that the parallelized adder offers significant speedups at realistic word sizes with modest parallelization overhead.

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J, Lakshmesha, and K. R. Usha Rani. "A Novel Ripple/Carry Lookahead Hybrid Carry Select Adder Architecture." International Journal of Computer Applications 70, no. 27 (May 31, 2013): 5–9. http://dx.doi.org/10.5120/12237-8416.

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Ibrahim, Atef, and Fayez Gebali. "Optimized structures of hybrid ripple carry and hierarchical carry lookahead adders." Microelectronics Journal 46, no. 9 (September 2015): 783–94. http://dx.doi.org/10.1016/j.mejo.2015.06.008.

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Al-Smadi, Takialddin A., and Yasir K. Ibrahim . "Design of Speed Independent Ripple Carry Adder." Journal of Applied Sciences 7, no. 6 (March 1, 2007): 848–54. http://dx.doi.org/10.3923/jas.2007.848.854.

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AradhyaH.V, Ravish, Lakshmesha J, and Muralidhara K. N. "Reduced Complexity Hybrid Ripple Carry Lookahead Adder." International Journal of Computer Applications 70, no. 28 (May 31, 2013): 13–16. http://dx.doi.org/10.5120/12254-8202.

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., Y. Anil Kumar. "A HIGH SPEED DYNAMIC RIPPLE CARRY ADDER." International Journal of Research in Engineering and Technology 04, no. 08 (August 25, 2015): 438–42. http://dx.doi.org/10.15623/ijret.2015.0408075.

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V. Pavan Kumar, B., P. Sri Ashish, K. Sai Harshitha, G. Sai Krishna, and T. Anil chowdary. "Testing ripple carry adder using bist architecture." International Journal of Engineering & Technology 7, no. 2.7 (March 18, 2018): 834. http://dx.doi.org/10.14419/ijet.v7i2.7.11077.

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Very Large-Scale Integration has a greater impact on the developing circuit technology. The Cost and Size has been gradually reducing since years but increased the circuit complexity, there are problems which may affect the growth of VLSI technology. Among them one of major problem is circuit testing. To resolve this issue, we implement Built in Self-Test (BIST). BIST architecture is used to test the circuit itself. Engineers Design BIST to achieve high reliability and low repair cycle times. We implement Linear Feedback Shift Registers (LFSR) to generate the pseudo random test pattern and implement a ripple carry adder as circuit under test and Multiple Input Signature Register(MISR) as output response analyzer and test patterns are given to circuit under test and outputs are obtained these are compared with the actual outputs to test whether the circuit is faulty or not. To check whether the circuit is faulty or fault free we check the obtained outputs with actual outputs using Signature Analysis.

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9

SUZUKI, H., W. JEONG, and K. ROY. "Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders." IEICE Transactions on Electronics E90-C, no. 4 (April 1, 2007): 865–76. http://dx.doi.org/10.1093/ietele/e90-c.4.865.

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FAGHIH MIRZAEE, Reza, and Keivan NAVI. "Optimized Adder Cells for Ternary Ripple-Carry Addition." IEICE Transactions on Information and Systems E97.D, no. 9 (2014): 2312–19. http://dx.doi.org/10.1587/transinf.2013lop0007.

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O'DONNELL, JOHN T., and GUDULA RÜNGER. "FUNCTIONAL PEARL Derivation of a logarithmic time carry lookahead addition circuit." Journal of Functional Programming 14, no. 6 (October 27, 2004): 697–713. http://dx.doi.org/10.1017/s0956796804005180.

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Using Haskell as a digital circuit description language, we transform a ripple carry adder that requires $O(n)$ time to add two $n$-bit words into a parallel carry lookahead adder that requires $O(\log n)$ time. The ripple carry adder uses a scan function to calculate carry bits, but this scan cannot be parallelized directly since it is applied to a non-associative function. Several techniques are applied in order to introduce parallelism, including partial evaluation and symbolic function representation. The derivation given here constitutes a semi-formal correctness proof, and it also brings out explicitly each of the ideas underlying the algorithm.

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12

Saravanakumar, Saravanakumar, Vijeyakumar Vijeyakumar, and Sakthisudhan Sakthisudhan. "FPGA Implementation of High Speed Hardware Efficient Carry Select Adder." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 1 (May 30, 2018): 43. http://dx.doi.org/10.11591/ijres.v7.i1.pp43-47.

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This paper presents a novel architecture for high speed and hardware efficient carry select addition. We modify the two operand ripple carry addition followed in conventional Carry SeLect Adder(CSLA) with a simple and efficient gate level circuit to reduce area and delay significantly. For this, we use an increment 1 block for generating the sum outputs with carry input 1 instead of second pair ripple carry adder as in conventional CSLA. The novelty of the proposed approach is that it reduces area, and the delay due to carry propagation in second pair of adder cells. The proposed CSLA adder has been designed using structural VHDL code and synthesized using Altera Quartus II. Experimental results show that the proposed design outperform the previous approaches in terms of delay and area reduction.

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TRISETYARSO, AGUNG, and RODNEY VAN METER. "CIRCUIT DESIGN FOR A MEASUREMENT-BASED QUANTUM CARRY-LOOKAHEAD ADDER." International Journal of Quantum Information 08, no. 05 (August 2010): 843–67. http://dx.doi.org/10.1142/s0219749910006496.

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We present the design and evaluation of a quantum carry-lookahead adder (QCLA) using measurement-based quantum computation (MBQC), called MBQCLA. QCLA was originally designed for an abstract, concurrent architecture supporting long-distance communication, but most realistic architectures heavily constrain communication distances. The quantum carry-lookahead adder is faster than a quantum ripple-carry adder; QCLA has logarithmic depth while ripple adders have linear depth. MBQCLA utilizes MBQC's ability to transfer quantum states in unit time to accelerate addition. MBQCLA breaks the latency limit of addition circuits in nearest neighbor-only architectures: compared to the Θ(n) limit on circuit depth for linear nearest-neighbor architectures, it can reach Θ(log n) depth. MBQCLA is an order of magnitude faster than a ripple-carry adder when adding registers longer than 100 qubits, but requires a cluster state that is an order of magnitude larger. The cluster state resources can be classified as computation and communication; for the unoptimized form, ≈ 88% of the resources are used for communication. Hand optimization of horizontal communication costs results in a ≈ 12% reduction in spatial resources for the in-place MBQCLA circuit. For comparison, a graph state quantum carry-lookahead adder (GSQCLA) uses only ≈ 9% of the spatial resources of the MBQCLA.

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Thangasamy, Veeraiyah, Noor Ain Kamsani, Mohd Nizar Hamidon, Shaiful Jahari Hashim, Zubaida Yusoff, and Muhammad Faiz Bukhori. "Low power 18T pass transistor logic ripple carry adder." IEICE Electronics Express 12, no. 6 (2015): 20150176. http://dx.doi.org/10.1587/elex.12.20150176.

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15

Suresh, Kandula, and Bahniman Ghosh. "Ripple Carry Adder Using Two XOR Gates in QCA." Applied Mechanics and Materials 467 (December 2013): 531–35. http://dx.doi.org/10.4028/www.scientific.net/amm.467.531.

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Quantum-dot Cellular Automata (QCA) is a very recent technology which can be used for developing new digital circuits which use very less power [1-2]. This paper mainly aims at using XOR gates to implementation of adder circuit in lesser number of cells and with a higher density.

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Kathiresan, R., and M. Thangavel. "Design of Ripple Carry Adder Using Constant Delay Logic." i-manager's Journal on Electronics Engineering 4, no. 3 (May 15, 2014): 29–34. http://dx.doi.org/10.26634/jele.4.3.2678.

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17

Burignat, Stéphane, and Alexis De Vos. "A Review on Performances of Reversible Ripple-Carry Adders." International Journal of Electronics and Telecommunications 58, no. 3 (September 2012): 205–12. http://dx.doi.org/10.2478/v10177-012-0028-0.

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Abstract Quantum computing and circuits are of growing interest and so is reversible logic as it plays an important role in the synthesis of quantum circuits. Moreover, reversible logic provides an alternative to classical computing machines, that may overcome many of the power dissipation problems in the near future. Some ripple-carry adders based on a do-spy-undo structure have been designed and tested reversibly. This paper presents a brief overview of the performances obtained with such chips processed in standard 0.35 μm CMOS technology and used in true reversible calculation (computations are performed forwards and backwards such that addition and subtraction are made reversibly with the same chip). Adiabatic signals used are known to allow the signal energy stored on the various capacitances of the circuit to be redistributed rather than being dissipated as heat while allowing to avoid calculation errors introduced by the use of conventional rectangular pulses. Through the example of both simulations and experimental results, this paper aims at providing a base of knowledge and knowhow in physical implementation of reversible circuits.

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18

Sasamal, Trailokya Nath, Ashutosh Kumar Singh, and Umesh Ghanekar. "Efficient design of coplanar ripple carry adder in QCA." IET Circuits, Devices & Systems 12, no. 5 (May 10, 2018): 594–605. http://dx.doi.org/10.1049/iet-cds.2018.0020.

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19

Shylashree, N., and D. S. Mahesh. "Latency and throughput analysis of a pipelined GDI ripple carry adder." International Journal of Engineering & Technology 7, no. 2.21 (April 20, 2018): 123. http://dx.doi.org/10.14419/ijet.v7i2.21.11848.

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Latency and Throughput are deemed parameters of prime importance that determine the speed of an Adder Circuit. Ongoing research in the field of Digital Signal Processing involves optimizing an Adder regarding these parameters. This article picks up the study of a ripple carry adder and presents the use of two methods towards ameliorating the performance of an adder – viz., the use of GDI (Gate Diffusion Input) technology for reduced Latency, and implementation of a pipelined architecture towards increasing the throughput. In this paper, we have dileneated the function of a basic GDI cell, with which a 1-bit ripple carry full adder was designed, which in turn formed the basic building blocks of 8-bit and 32-bit ripple carry adders. These full adders were designed using GDI technology while employing the concept of pipelining resulting in a novel structure optimizing both latency and throughput. This paper also presents a comparison among CMOS and GDI RCAs of 8 and 32bits with and without pipelining.On simulating 32-bit RCAs in Cadence virtuoso tool using gpdk 180nm technology ,those with pipelining had a 4.5 times increase in throughput with 42.8% increase in latency.

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20

Rupsa Roy, Swarup Sarkar,. "QCA based Novel Reversible Reconfigurable Ripple Carry Adder with Ripple Borrow Subtractor in Electro-Spin Technology." Psychology and Education Journal 58, no. 2 (February 10, 2021): 813–23. http://dx.doi.org/10.17762/pae.v58i2.1916.

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An important arithmetic component of “Arithmetic and Logic Unit” or ALU is reconfigured in this paper, known as “Full-Adder-Subtractor”, where an advance low-power, high-speed nano technology “QCA” with electro-spin criterion is used with reversibility and the advancement of multilayer 3D circuitry. In this modern digital world, this selected nano-sized technology is an effective alternative of widely used “CMOS Technology” because all the limitations, mainly limitation due to the presence of high power dissipation at the time of device-density increment in a “CMOS” based integrated circuit, can be optimized by “QCA” nano technology with electro-spin criterion and this technology also supports reversible logic in multilayer 3D platform with less complexity. This paper, primarily presents two novel “QCA” based 3-layered “Adder-Subtractor” designs using the collaboration of multilayer inverter gates, reversible modified 3-input Feynman-Gate and 3-input MG (Majority Gate) with very less cell-complexity, area-occupation, delay and energy-dissipation and high output-strength, temperature-tolerance and accuracy. A clear parametric investigation on presented designs are shown clearly in this paper through a comparative manner with some previous published related structures. Additionally, another parametric-experiment on a novel multibit reversible multilayer “QCA” based “Full-Adder-Subtractor” circuitry using the working phenomenon of “Ripple Carry Adder” (RCA) and multibit subtractor (“ripple borrow subtractor” or RBS) is presented in this proposed work in a proper way and this combination of RCA and multibit subtraction operation converts the proposed circuitry into a hybrid form, which is more effective compare to some other advanced adders in parametric-optimization field.

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21

Mohammadi, Hassan Ghasemzadeh, Pierre-Emmanuel Gaillardon, Jian Zhang, Giovanni De Micheli, Ernesto Sanchez, and Matteo Sonza Reorda. "A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors." ACM Journal on Emerging Technologies in Computing Systems 13, no. 2 (March 10, 2017): 1–13. http://dx.doi.org/10.1145/2988234.

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22

Ali, Mohamed Syed. "Cascaded Ripple Carry Adder Based SRCSA for Efficient FIR Filter." Indonesian Journal of Electrical Engineering and Computer Science 9, no. 2 (February 1, 2018): 253. http://dx.doi.org/10.11591/ijeecs.v9.i2.pp253-256.

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<p>Filter is one of the key components of all signals processing elements. Both the FIR and IIR filter are used to reduce the unwanted signal in the original signal. Here discussing the FIR filter and design the efficient FIR filter using Dual Ripple Carry Adder (RCA) based SQRT-carry select adder (CSLA). Many components present in the FIR filter, one of the main component is Adder. Adder is used to combine the signal for avoid the noise occurring in the output. Proposed a Dual RCA based SQRT-CSLA for speed up the filtering process. The filter performance can be analyzed by Xilinx simulation environment.</p>

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23

Babu, M. Ramesh, D. Mahendra, and S. Rambabu. "An Efficient Low Power Ripple Carry Adder for Ultra Applications." IOSR Journal of Electronics and Communication Engineering 9, no. 2 (2014): 38–42. http://dx.doi.org/10.9790/2834-09273842.

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24

Larasati, Harashta Tatimma, Janghyun Ji, Jeonghwan Park, and Howon Kim. "Performance Evaluation of Ripple-Carry Adders in Quantum Factoring Algorithm." Journal of Korean Institute of Communications and Information Sciences 46, no. 2 (February 28, 2021): 333–44. http://dx.doi.org/10.7840/kics.2021.46.2.333.

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Taheri Tari, Hani, Arezoo Dabaghi Zarandi, and Mohammad Reza Reshadinezhad. "Design of a high performance CNTFET-based full adder cell applicable in: Carry ripple, carry select and carry skip adders." Microelectronic Engineering 215 (July 2019): 110980. http://dx.doi.org/10.1016/j.mee.2019.110980.

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Takahashi, Y., and N. Kunihiro. "A linear-size quantum circuit for addition with no ancillary qubits." Quantum Information and Computation 5, no. 6 (September 2005): 440–48. http://dx.doi.org/10.26421/qic5.6-2.

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We construct a quantum circuit for addition of two $n$-bit binary numbers that uses no ancillary qubits. The circuit is based on the ripple-carry approach. The depth and size of the circuit are $O(n)$. This is an affirmative answer to the question of Kutin \cite{Kutin} as to whether a linear-depth quantum circuit for addition can be constructed without ancillary qubits using the ripple-carry approach. We also construct quantum circuits for addition modulo $2^n$, subtraction, and comparison that use no ancillary qubits by modifying the circuit for addition.

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Gnilenko, Alexey. "LAYOUT DESIGN OF 4-BIT RIPPLE CARRY ADDER BASED ON PASS TRANSISTOR LOGIC." System technologies 1, no. 126 (March 27, 2020): 46–53. http://dx.doi.org/10.34185/1562-9945-1-126-2020-05.

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The full adder is a key element of any arithmetic logic units used in microprocessor systems. For microprocessor components created for modern mobile digital devices, compact layout design on the silicone chip is of great importance. In this paper an area effective layout design on the chip is proposed for 4-bit ripple carry adder based on pass transistor logic. The full adder is simulated using EDA tool and output signal waveforms are obtained to demonstrate the functionality of the design. It is shown that 1-bit full adder based on pass transistor logic and composed of two 3T XOR gates and one 2T multiplexer allows us to obtain area effective layout design on the chip for 4-bit ripple carry adder providing acceptable characteristics for output signals.

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28

Papachatzopoulos, Kleanthis, and Vassilis Paliouras. "Static Delay Variation Models for Ripple-Carry and Borrow-Save Adders." IEEE Transactions on Circuits and Systems I: Regular Papers 66, no. 7 (July 2019): 2546–59. http://dx.doi.org/10.1109/tcsi.2019.2900151.

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Burignat, Stéphane, and Alexis De Vos. "A Technology Based Complexity Model for Reversible Cuccaro Ripple-Carry Adder." Journal of Low Power Electronics 10, no. 4 (December 1, 2014): 584–92. http://dx.doi.org/10.1166/jolpe.2014.1353.

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30

Draper, T. G., S. A. Kutin, E. M. Rains, and K. M. Svore. "A logarithmic-depth quantum carry-lookahead adder." Quantum Information and Computation 6, no. 4&5 (July 2006): 351–69. http://dx.doi.org/10.26421/qic6.4-5-4.

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We present an efficient addition circuit, borrowing techniques from classical carry-lookahead arithmetic. Our quantum carry-lookahead (\QCLA) adder accepts two n-bit numbers and adds them in O(\log n) depth using O(n) ancillary qubits. We present both in-place and out-of-place versions, as well as versions that add modulo 2^n and modulo 2^n - 1. Previously, the linear-depth ripple-carry addition circuit has been the method of choice. Our work reduces the cost of addition dramatically with only a slight increase in the number of required qubits. The \QCLA\ adder can be used within current modular multiplication circuits to reduce substantially the run-time of Shor's algorithm.

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BALASUBRAMANIAN, P., D. A. EDWARDS, and W. B. TOMS. "SELF-TIMED SECTION-CARRY BASED CARRY LOOKAHEAD ADDERS AND THE CONCEPT OF ALIAS LOGIC." Journal of Circuits, Systems and Computers 22, no. 04 (April 2013): 1350028. http://dx.doi.org/10.1142/s021812661350028x.

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This paper makes two important contributions to the domain of self-timed computer arithmetic. Firstly, a gate-level synthesis of self-timed carry lookahead (CLA) adders based on the notion of section-carry is discussed. Three types of CLA adder architectures have been conceived and both homogeneous and heterogeneous delay-insensitive (DI) data encoding schemes are considered. In general, for higher-order additions, the self-timed CLA adder is found to result in reduced latency than the carry ripple version by 38.6%. However, the latter occupies less area and dissipates less power than the former by 37.8% and 17.4%, respectively. Secondly, a new concept of alias logic is introduced in this work which is useful for delay optimization of iterative circuit specifications — here; this concept is applied to effect latency reduction in self-timed CLA adders. By incorporating alias logic, the propagation delay of the intermediate carries in a CLA structure is further minimized to the tune of 27.2% on average, whilst accompanied by marginal area and power penalties of the order of just 2% and 1.5%, respectively.

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Lin, Yu Shen, and Damu Radhakrishnan. "Delay Efficient 32-Bit Carry-Skip Adder." VLSI Design 2008 (April 2, 2008): 1–8. http://dx.doi.org/10.1155/2008/218565.

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The design of a 32-bit carry-skip adder to achieve minimum delay is presented in this paper. A fast carry look-ahead logic using group generate and group propagate functions is used to speed up the performance of multiple stages of ripple carry adders. The group generate and group propagate functions are generated in parallel with the carry generation for each block. The optimum block sizes are decided by considering the critical path into account. The new architecture delivers the sum and carry outputs in lesser unit delays than existing carry-skip adders. The adder is implemented in 0.25 m CMOS technology at 3.3 V. The critical delay for the proposed adder is 3.4 nanoseconds. The simulation results show that the proposed adder is 18 faster than the current fastest carry-skip adder.

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Hoe, David H. K., L. P. Deepthi Bollepalli, and Chris D. Martinez. "FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders." VLSI Design 2013 (November 7, 2013): 1–10. http://dx.doi.org/10.1155/2013/382682.

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This paper examines fault tolerant adder designs implemented on FPGAs which are inspired by the methods of modular redundancy, roving, and gradual degradation. A parallel-prefix adder based upon the Kogge-Stone configuration is compared with the simple ripple carry adder (RCA) design. The Kogge-Stone design utilizes a sparse carry tree complemented by several smaller RCAs. Additional RCAs are inserted into the design to allow fault tolerance to be achieved using the established methods of roving and gradual degradation. A triple modular redundant ripple carry adder (TMR-RCA) is used as a point of reference. Simulation and experimental measurements on a Xilinx Spartan 3E FPGA platform are carried out. The TMR-RCA is found to have the best delay performance and most efficient resource utilization for an FPGA fault-tolerant implementation due to the simplicity of the approach and the use of the fast-carry chain. However, the superior performance of the carry-tree adder over an RCA in a VLSI implementation makes this proposed approach attractive for ASIC designs.

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Wu-Tung Cheng and Patel. "A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders." IEEE Transactions on Computers C-36, no. 7 (July 1987): 891–95. http://dx.doi.org/10.1109/tc.1987.1676985.

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Ying, Zhoufeng, Shounak Dhar, Zheng Zhao, Chenghao Feng, Rohan Mital, Chi-Jui Chung, David Z. Pan, Richard A. Soref, and Ray T. Chen. "Electro-Optic Ripple-Carry Adder in Integrated Silicon Photonics for Optical Computing." IEEE Journal of Selected Topics in Quantum Electronics 24, no. 6 (November 2018): 1–10. http://dx.doi.org/10.1109/jstqe.2018.2836955.

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Sun, De-Gui, and Zhao-Heng Weng. "Butterfly interconnection implementation for an n-bit parallel ripple carry full adder." Applied Optics 30, no. 14 (May 10, 1991): 1781. http://dx.doi.org/10.1364/ao.30.001781.

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Pudi, Vikramkumar, and K. Sridharan. "Low Complexity Design of Ripple Carry and Brent–Kung Adders in QCA." IEEE Transactions on Nanotechnology 11, no. 1 (January 2012): 105–19. http://dx.doi.org/10.1109/tnano.2011.2158006.

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Haruehanroengra, Sansiri, and Wei Wang. "Efficient Design of QCA Adder Structures." Solid State Phenomena 121-123 (March 2007): 553–56. http://dx.doi.org/10.4028/www.scientific.net/ssp.121-123.553.

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Optimizing arithmetic primitives such as quantum-dot cellular automata (QCA) adders is important for investigating high-performance QCA computers in this emerging nano-technological paradigm. In this paper, we demonstrate that QCA ripple carry adder and bit-serial adder designs actually outperform carry-look-ahead and carry-select adder designs because of the increase in required interconnects. Simulation results obtained by using the QCADesigner tool for the proposed adder designs are also presented.

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Balasubramanian, Padmanabhan, Douglas Maskell, and Nikos Mastorakis. "Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic." Electronics 7, no. 10 (October 9, 2018): 243. http://dx.doi.org/10.3390/electronics7100243.

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Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.

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Balasubramanian, Padmanabhan, and Nikos Mastorakis. "Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions." Electronics 7, no. 12 (December 2, 2018): 369. http://dx.doi.org/10.3390/electronics7120369.

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Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing binary-to-excess-1 code (BEC) converters. In the literature, the designs of many CLAs and CSLAs were described separately. It would be useful to have a direct comparison of their performances based on the design metrics. Hence, we implemented homogeneous and hybrid CLAs, and CSLAs with and without the BEC converters by considering 32-bit accurate and approximate additions to facilitate a comparison. For the gate-level implementations, we considered a 32/28 nm complementary metal-oxide-semiconductor (CMOS) process targeting a typical-case process–voltage–temperature (PVT) specification. The results show that the hybrid CLA/RCA architecture is preferable among the CLA and CSLA architectures from the speed and power perspectives to perform accurate and approximate additions.

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Samyuktha, S., and D. L. Chaitanya. "VLSI design of efficient FIR filters using Vedic Mathematics and Ripple Carry Adder." Materials Today: Proceedings 33 (2020): 4828–32. http://dx.doi.org/10.1016/j.matpr.2020.08.391.

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., Gulivindala Suresh. "PERFORMANCE EVALUATION OF FULL ADDER AND ITS IMPACT ON RIPPLE CARRY ADDER DESIGN." International Journal of Research in Engineering and Technology 03, no. 16 (May 25, 2014): 23–28. http://dx.doi.org/10.15623/ijret.2014.0316005.

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Ghosh, Bahniman, M. Giridhar, M. Nagaraju, and Akshaykumar Salimath. "Ripple Carry Adder Using Five Input Majority Gates in Quantum Dot Cellular Automata." Quantum Matter 3, no. 6 (December 1, 2014): 495–98. http://dx.doi.org/10.1166/qm.2014.1152.

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Akbar, Muhammad Ali, Bo Wang, and Amine Bermak. "A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization." Electronics 10, no. 15 (July 26, 2021): 1791. http://dx.doi.org/10.3390/electronics10151791.

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Ripple-carry adder (RCA) is among the most common type of adder. However, it is not preferred in many applications because of its high latency. In this paper, two architectures of high-speed parallel RCA (PRCA) along with fault detection and localization are proposed, with reduced overhead as compared with carry look-ahead adder (CLA). In the proposed approach, RCA is divided into blocks, where the initial carry input for each block will be generated by a carry look-ahead logic unit. The delay is reduced by 43.81% as compared with the conventional 64-bit RCA design. The delay is further reduced by replacing the last blocks with a single RCA-based CSeA design and becomes equal to CLA if the last three blocks are replaced with CSeA. The proposed 64-bit design of PRCA and PRCA-CSeA requires 20.31% and 22.50% area overhead as compared with the conventional RCA design. Whereas, the delay-power-area product of our proposed designs is 24.66%, and 30.94% more efficient than conventional RCA designs. With self-checking, the proposed architecture of PRCA and PRCA-CSeA with multiple-fault detection requires 42.36% and 44.35% area overhead as compared with a 64-bit self-checking RCA design.

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Hossain, Muhammad Saddam, and Farhadur Arifin. "Design and Evaluation of a 32-bit Carry Select Adder using 4-bit Hybrid CLA Adder." AIUB Journal of Science and Engineering (AJSE) 20, no. 2 (May 15, 2021): 1–7. http://dx.doi.org/10.53799/ajse.v20i2.119.

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Adder circuits play a remarkable role in modern microprocessor. Adders are widely used in critical paths of arithmetic operation such as multiplication and subtraction. A Carry Select Adder (CSA) design methodology using a modified 4-bit Carry Look-Ahead (CLA) Adder has been proposed in this research. The proposed 4-bit CLA used hybrid logic style based logic circuits for Carry Generate (Gi) and Carry Propagate (Pi) functions in order to improve performance and reduce the number of transistor used. The modified 4-bit CLA is used as the basic unit for implementation of 32-bit CSA. The proposed design of hybrid CLA based 32-bit CSA has been compared with conventional static CMOS based 32-bit CSA and 32-bit Ripple Cary Adder (RCA) by conducting simulation using Cadence Virtuoso. Power consumption and delay in the proposed 32-bit CSA found 322.6 (uW) and 0.556 (ns) whereas power and delay in the conventional 32-bit CSA was 455.4 (uW) and 0.667 (ns) respectively. We have done all the simulation using Cadence Virtuoso 90 nm tool.

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Dam, Minh Tung, Van Toan Nguyen, and Jeong-Gun Lee. "A Carry Chain-Based ADMFC Design on an FPGA for EMI Reduction and Noise Compensation." Journal of Circuits, Systems and Computers 28, no. 01 (October 15, 2018): 1950018. http://dx.doi.org/10.1142/s021812661950018x.

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An all-digital multi-frequency clocking (ADMFC) circuit is proposed to reduce electromagnetic interference (EMI) on a field-programmable gate array (FPGA) architecture, while supporting dynamic adaptation to voltage noises. The proposed ADMFC uses dedicated high-speed carry chain paths in an FPGA to finely adjust the clock frequency by controlling the number of carry propagations on the carry chain logics (CARRY4 cells) in the delay line of a ring oscillator. Moreover, supply voltage variation and noise caused by circuit switchings can be compensated by dynamically adjusting the length of ripple carry propagations on the cascaded CARRY4 cells in response to the detected voltage variation. Finally, a selectable modulation profile is devised to provide a much suitable profile between two different profiles at run-time for the given noise constraints and working environment of a chip. Measurement results show that at the frequency of 44.6[Formula: see text]MHz, the ADMFC can obtain 17[Formula: see text]dB and 19.4[Formula: see text]dB EMI attenuations with a 7.5% spreading ratio when using triangular and sawtooth profiles, respectively. The proposed ADMFC is suitable for applications such as biological sensor nodes or IoT related systems which typically operate at a low-frequency band.

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Anand, B., and V. V. Teresa. "Improved Modified Area Efficient Carry Select Adder (MAE-CSLA) Without Multiplexer." Journal of Computational and Theoretical Nanoscience 14, no. 1 (January 1, 2017): 269–76. http://dx.doi.org/10.1166/jctn.2017.6316.

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The Carry Select Adder (CSLA) is the fastest adders that perform arithmetic operations in many processors. There are lot of modifications that are proposed to reduce the area of CSLA one such efficient technique is presented in this paper. Here the area is reduced by eliminating the multiplexer that selects the carry in of regular CSLA by using a simple XOR gate. Here the XOR gate is used to generate the first sum output of the ripple carry adders in the second stage of the CSLA adder. Then the XOR gate is implemented with AOI. This AOI implementation will further reduce the area consumption of the adder. The proposed Modified Area Efficient Carry Select Adder (MAE-CSLA) is designed and analyzed in XILINX ISE design suite 14.5 tools. By this analysis it is clear that the modifications effect adversely in the area and power consumption of MAE-CSLA.

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Dadgar, Zahra, and Abdalhossein Rezai. "An Efficient Design for Coplanar Ripple Carry Adder in Quantum-dot Cellular Automata Technology." Journal of Nano- and Electronic Physics 11, no. 3 (2019): 03034–1. http://dx.doi.org/10.21272/jnep.11(3).03034.

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K.L.V, Ramana Kumari, Asha Rani M, and Balaji N. "Design Verification and Test Vector Minimization Using Heuristic Method of a Ripple Carry Adder." International Journal on Cybernetics & Informatics 5, no. 4 (August 30, 2016): 307–13. http://dx.doi.org/10.5121/ijci.2016.5433.

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Masood, Md, K. Manjunathachari, and K. Lalkishore. "Static Power Reduction in 32-bit Ripple Carry Adder using Dual Threshold Voltage Assignment." International Journal of Computer Applications 124, no. 2 (August 18, 2015): 16–20. http://dx.doi.org/10.5120/ijca2015905366.

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Journal articles on the topic 'Ripple carry'

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