Relevant bibliographies by topics / RISC-V

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'RISC-V'

Author: Grafiati
Published: 4 June 2021
Last updated: 25 January 2025

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Journal articles on the topic "RISC-V"

1

Frolov, Vladimir Alexandrovitch, Vladimir Alexandrovitch Galaktionov, and Vadim Vladimirovitch Sangarov. "Investigation of the RISC-V." Proceedings of the Institute for System Programming of the RAS 32, no. 2 (2020): 81–98. http://dx.doi.org/10.15514/ispras-2020-32(2)-7.

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Frolov, V. A., V. A. Galaktionov, and V. V. Sanzharov. "Investigation of RISC-V." Programming and Computer Software 47, no. 7 (December 2021): 493–504. http://dx.doi.org/10.1134/s0361768821070045.

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Felzmann, Isaias, Joao Fabricio Filho, and Lucas Wanner. "Risk-5: Controlled Approximations for RISC-V." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, no. 11 (November 2020): 4052–63. http://dx.doi.org/10.1109/tcad.2020.3012312.

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Greengard, Samuel. "Will RISC-V revolutionize computing?" Communications of the ACM 63, no. 5 (April 20, 2020): 30–32. http://dx.doi.org/10.1145/3386377.

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Шабан, Максим. "ІМПЛЕМЕНТАЦІЯ НАБОРУ ІНСТРУКЦІЇ RISC-V." Ukrainian Scientific Journal of Information Security 28, no. 2 (December 4, 2022): 80–86. http://dx.doi.org/10.18372/2225-5036.28.16948.

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В 70-х роках минулого сторіччя, під час активного розвитку електронно-обчислювальної техніки, розвиток обчислювальних систем пішов двома шляхами: високопродуктивні обчислювальні системи (ОС); вузькопрофільні обчислювальні системи. Фактично, високопродуктивні системи – це універсальні ОС завданням яких є максимальна висока швидкість обчислень за одиницю часу. Вузькопрофільні ОС ставили за мету виконання певних типів завдань, де якраз швидкість обчислень не мала такого значення, а на перші ролі виходили інші технічні характеристики: енергоефективність, ергономіка виробу, необхідність виконання тільки певного роду завдань та інше. Саме вид завдань став вирішальним з точки зору архітектурної реалізації ОС. Розглянемо архітектуру RISC-V з метою оцінки перспективності впровадження її до масового сегменту.
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Núñez-Prieto, Ricardo, David Castells-Rufas, and Lluís Terés-Terés. "RisCO2: Implementation and Performance Evaluation of RISC-V Processors for Low-Power CO2 Concentration Sensing." Micromachines 14, no. 7 (July 4, 2023): 1371. http://dx.doi.org/10.3390/mi14071371.

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In the field of embedded systems, energy efficiency is a critical requirement, particularly for battery-powered devices. RISC-V processors have gained popularity due to their flexibility and open-source nature, making them an attractive choice for embedded applications. However, not all RISC-V processors are equally energy-efficient, and evaluating their performance in specific use cases is essential. This paper presents RisCO2, an RISC-V implementation optimized for energy efficiency. It evaluates its performance compared to other RISC-V processors in terms of resource utilization and energy consumption in a signal processing application for nondispersive infrared (NDIR) CO2 sensors.The processors were implemented in the PULPino SoC and synthesized using Vivado IDE. RisCO2 is based on the RV32E_Zfinx instruction set and was designed from scratch by the authors specifically for low-power signal demodulation in CO2 NDIR sensors. The other processors are Ri5cy, Micro-riscy, and Zero-riscy, developed by the PULP team, and CV32E40P (derived from Ri5cy) from the OpenHW Group, all of them widely used in the RISC-V community. Our experiments showed that RisCO2 had the lowest energy consumption among the five processors, with a 53.5% reduction in energy consumption compared to CV32E40P and a 94.8% reduction compared to Micro-riscy. Additionally, RisCO2 had the lowest FPGA resource utilization compared to the best-performing processors, CV32E40P and Ri5cy, with a 46.1% and a 59% reduction in LUTs, respectively. Our findings suggest that RisCO2 is a highly energy-efficient RISC-V processor for NDIR CO2 sensors that require signal demodulation to enhance the accuracy of the measurements. The results also highlight the importance of evaluating processors in specific use cases to identify the most energy-efficient option. This paper provides valuable insights for designers of energy-efficient embedded systems using RISC-V processors.
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V, Prof Jaswanth. "Implementation and Evaluation of SIMD Instructions using RISC-V." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 05 (May 15, 2024): 1–5. http://dx.doi.org/10.55041/ijsrem34010.

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This thesis introduces and explores the design and verification of a packed Single Instruction, Multiple Data (SIMD) instruction set for a RISC-V processor, known as the RISC-V P extension. This extension enhances the RISC-V instruction set architecture by providing packed SIMD support for 8-bit, 16-bit, and 32-bit integer data types. The significance of this architecture lies in its potential to empower developers in constructing more efficient and powerful data-parallel programs for RISC-V processors. This contribution enhances the overall capabilities of the RISC-V ecosystem, providing a valuable extension to the instruction set architecture for data-parallel applications. Keywords: Data-parallel Programs, instruction set architecture, RISC-V, P extension, Packed SIMD
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Rajveer Singh, Et al. "RISC-V Processor for IOT Applications." International Journal on Recent and Innovation Trends in Computing and Communication 11, no. 11 (December 31, 2023): 701–5. http://dx.doi.org/10.17762/ijritcc.v11i11.10074.

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RISC-V is a recently introduced instruction-set architecture (ISA) that offers innovative advantages, including low power consumption, affordability, and scalability. Utilizing an open, non-proprietary Instruction Set Architecture (ISA) enables the creation of on-the-fly design of soft error countermeasures at the microarchitecture level. This may significantly enhance the resilience of Application Specific Standard Products (ASSP) and FPGA implementations. This paper offers a quick overview of the RISC-V architecture. This paper presents a plan to create and execute a 32-bit single-cycle RISC-V processor using Verilog HDL in the Vivado software.
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Строгонов, А. В., А. Винокуров, and А. И. Строгонов. "ПРИМЕР РЕАЛИЗАЦИИ ОДНОТАКТНОГО ПРОЦЕССОРНОГО ЯДРА RISC-V В САПР ALTERA QUARTUS II." ELECTRONICS: SCIENCE, TECHNOLOGY, BUSINESS 240, no. 9 (October 18, 2024): 70–79. https://doi.org/10.22184/1992-4178.2024.240.9.70.79.

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В России продолжается популяризация и развитие открытой архитектуры RISC-V. Сегодня разработкой проектов на базе открытой архитектуры RISC-V занимается ряд российских компаний и ведущих университетов. Например, микроконтроллер Hackee на базе ядра SCR1 (от российского разработчика Syntacore) был спроектирован совместно магистрантами НИУ «МИЭТ» и специалистами компании Yadro. «Микрон» представил микроконтроллер «MIK32 Амур» (К1948ВК018) на базе RISC-V и отладочную плату на его основе. Есть проекты и других российских компаний, действующих в рамках «Альянса RISC-V» [1]. Одним из направлений исследований в этой области является отработка прототипов процессоров на платформе ПЛИС. В статье рассмотрен пример реализации однотактного процессорного ядра RISC-V в базисе ПЛИС Cyclone V с применением САПР Altera Quartus II.
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P, Pavan, Kamal P S, Govardhan G, and Suresh Kumar V. "Basic RISC-V Instruction Set Architecture: Design and Validation." International Journal for Research in Applied Science and Engineering Technology 11, no. 5 (May 31, 2023): 2845–50. http://dx.doi.org/10.22214/ijraset.2023.52205.

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Abstract: This project's primary goal is to design and implement a simple RISC V instruction set architecture. This paper offers insights into the architecture of the risc v instruction set. This system employs the RISC V R-type (register) type instruction format. Using this format, we designed the fundamental isa and tested its functionality using verilog code. There is no licence fee for using RISC V, an open source isa that is available to everyone. Reduced instruction set (RISC) computers are created to make the individual instructions given to computers to perform various tasks more manageable. Most instruction set architectures, or isas, are proprietary and cannot be used or modified without permission from the companies; as a result, an isa that is free and open source, which is provided by risc v, will help in increasing the speed and lowering system costs by using these instruction set formats, and we are designing 32 bit isa architecture. instruction formats for the risc v instruction set architecture
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Dissertations / Theses on the topic "RISC-V"

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Barták, Jiří. "Model procesoru RISC-V." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2016. http://www.nusl.cz/ntk/nusl-255393.

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The number of application specific instruction set processors is rapidly increasing, because of increased demand for low power and small area designs. A lot of new instruction sets are born, but they are usually confidential. University of California in Berkeley took an opposite approach. The RISC-V instruction set is completely free. This master's thesis focuses on analysis of RISC-V instruction set and two programming languages used to model instruction sets and microarchitectures, CodAL and Chisel. Implementation of RISC-V base instruction set along with multiplication, division and 64-bit address space extensions and implementation of cycle accurate model of Rocket Core-like microarchitecture in CodAL are main goals of this master's thesis. The instruction set model is used to generate the C compiler and the cycle accurate model is used to generate RTL representation, all thanks to Codasip Studio. Generated compiler is compared against the one implemented manually and results are used for instruction set optimizations. RTL is synthesized to Artix 7 FPGA and compared to the Rocket Core synthesis.
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Vavro, Tomáš. "Periferie procesoru RISC-V." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2021. http://www.nusl.cz/ntk/nusl-445553.

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The RISC-V platform is one of the leaders in the computer and embedded systems industry. With the increasing use of these systems, the demand for available peripherals for the implementations of this platform is growing. This thesis deals with the FU540-C000 processor from SiFive company, which is one of the implementations of the RISC-V architecture, and its basic peripherals. Based on the analysis, an UART circuit for asynchronous serial communication was selected from the peripherals of this processor. The aim of this master thesis is to design and implement the peripheral in one of the languages for the description of digital circuits, and then create a verification environment, through which the functionality of the implementation will be verified.
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Benna, Filip. "Generování objektových souborů pro RISC-V." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-363865.

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This master’s thesis deals with the topic of program source code compilation for RISC-V processor architecture. The generated object files need to be compatible with GNU binutils open source tools which are already available for the architecture. The focus is on relocations which must be correctly detected in Codasip Studio tools and transformed into RISC-V platform specific relocation types.
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Skála, Milan. "Prostředí pro spouštění testů kompatibility RISC-V." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2018. http://www.nusl.cz/ntk/nusl-386021.

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This thesis focuses on design and implementation of a testing framework for different implementation types of RISC-V architecture. It describes history, instruction set and processor modes which are supported by this architecture. Further, the current methodologies and testing frameworks implemented in Python are discussed. Emphasis is placed on the analysis of compliance tests. In the practical part, the design and implementation of a framework for execution of compliance tests for models, which can be implemented in various ways, either as an ISA simulator or a hardware model, is done. The secondary aim of the thesis is to create a graphical user interface for quick and easy test configuration. Finally, the results are evaluated and the possibilities of further development are discussed.
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Midéus, Gustav, and Chavez Antonio Morales. "RISC-V Thread Isolation : Using Zephyr RTOS." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-279100.

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Many embedded systems lack a memory management unit (MMU) and thus often also lack protection of memory. This causes these systems to be less robust since the operating system (OS), processes, and threads are no longer isolated from each other. This is also a potential security issue and with the number of embedded systems rapidly increasing as a result of the rise of Internet of things (IoT), vulnerabilities like this could become a major problem. However, with a recent update to the RISC-V processor architecture, a possibility to isolate regions of memory without an MMU was introduced. This study aims to identify problems and possibilities of implementing such memory protection with RISC-V. Based on a study of literature and documentation on memory protection and the RISC-V architecture, a prototype was designed and implemented to determine potential problems and evaluate performance in terms of execution time and memory cost. The developed prototype showed aworking implementation of memory protection for the memory regions with RISC-V. The evaluation of the prototype demonstrated an increase in context switch execution time and memory usage. The results indicate that the implemented memory protection comes with an increased cost in performance with a constant factor and a small memory overhead. Therefore, it is recommended that implementations that wish to implement memory protection with RISC-V on smaller embedded systems where time and memory may be crucial takes the overhead in consideration. Further research and testing is needed to identify optimizations that could improve the performance as well as discover security flaws.
Många inbyggda system saknar en enhet för minneshantering (s.k. MMU) och saknar därför oftast minnesskydd. Detta leder till att dessa system blir mindre robusta eftersom operativsystemet, processer och trådar inte längre är isolerade från varandra. Detta är också en säkerhetsbrist och med antalet inbyggda system som snabbt ökar på grund av tillväxten av Internet of things (IoT), så kan sårbarheter som denna bli ett stort problem. Med en nyligen introducerad uppdatering av RISC-Vprocessor arkitekturen, så introducerades en möjlighet till att isolera minne utan hjälp av en MMU. Denna studie syftar till att identifiera problem och möjligheter av att implementera sådant minneskydd med RISC-V. Baserat på en studie av litteratur och dokumentation om minnesskydd och RISC-V arkitekturen designades och implementerades en prototyp för att hjälpa till att fastställa problem och möjligheter samt göra en utvärdering med avseende på prestanda- och minneskostnader. Den utvecklade prototypen visade en fungerande implementering av minneskydd för minnesregioner med RISC-V. Utvärderingen av prototypen visade en ökad exekveringstid för kontextbyten och ökad minnesanvändning. Resultaten indikerar att det implementerade minneskyddet kommer med en ökad kostnad i prestanda med en konstant faktor och en liten omkostnad i minne. Därför rekommenderas att implementeringar som vill implementera minneskydd med RISC-V på mindre inbyggda system där tid och minne kan vara avgörande tar hänsyn till omkostnaderna. Ytterligare studier och tester behövs för att identifiera optimeringar som kan förbättra prestandan och upptäcka säkerhetsbrister.
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Dalbom, Axel, and Tim Svensson. "Implementing the Load Slice Core on a RISC-V based microarchitecture." Thesis, Uppsala universitet, Datorarkitektur och datorkommunikation, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-424385.

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As cores have become better at exposing Instruction-Level Parallelism (ILP), they have become bigger, more complex, and consumes more power. These cores are approaching the Power- and Memory-wall quickly. A new microarchitecture proposed by Carlson et. al claims to solve these problems. They claim that the new microarchitecture, the Load Slice Core, is able to outperform both In-Order and Out-of-Order designs in an area and power restricted environment. Based on Carlson et. al.’s work, we have implemented and evaluated a prototype version of their Load Slice Core using the In-Order Core Ariane. We evaluated the Load Slice Core by comparing the LSC to an IOC when running a microbenchmark designed by us, and when running a set of Application Benchmarks. The results from the Microbenchmark are promising, the LSC outperformed the comparable IOC in each test but problems related to the configuration of the design were found. The results from the Application Benchmarks are inconclusive. Due to time constraints, only a partially functioning LSC were compared to a comparable IOC. From these results we found that the LSC performed comparably or slightly worse than its IOC counterpart. More research on the subject is required for any conclusive statement on the microarchitecture can be made, but it is the opinion of this paper’s authors that it does show promise.
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Bardonek, Petr. "Specifikace scénářů portovatelných stimulů pro moduly procesoru RISC-V." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2018. http://www.nusl.cz/ntk/nusl-385914.

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The thesis is focused on the design and implementation of the portable stimulus verification scenarios for selected Berkelium processor modules based on RISC-V architecture from Codasip. The aim of this work is to use new standard for Portable Stimulus developed by Accellera organization to design and implement portable stimulus scenarios using the Questa InFact tool from Mentor. The proposed portable stimulus scenarios are then linked to the already existing verification environments of the UVM methodology and then they are used for verification of the Berkelium processor modules based on RISC-V architecture. The last part of the thesis is the evaluation of portability of the implemented scenarios to the individual levels of the Berkelium processor based on RISC-V architecture (IP blocks, subsystems, system level), in which it tries to use the proposed scenarios across all verificated levels.
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Javor, Adrián. "Formalní verifikace RISC-V procesoru s využitím Questa PropCheck." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2020. http://www.nusl.cz/ntk/nusl-413219.

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The topic of this master thesis is Formal verification of RISC-V processor with Questa PropCheck using SystemVerilog assertions. The theoretical part writes about the RISC-V architecture, furthermore, selected components of Codix Berkelium 5 processor used for formal verification are described, communication protocol AHB-lite, formal verification and its methods and tools are also studied. Experimental part consists of verification planning of selected components, subsequent formal verification, analysing of results and evaluating a benefits of formal technics.
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Chovančíková, Lucie. "Implementace mikroprocesoru RISC-V s rozšířením pro bitové manipulace." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2020. http://www.nusl.cz/ntk/nusl-413229.

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This master thesis deals with the design of a RISC-V processor with bit manipulations instruction set extension. In this work, attention is paid to the description of the RISC-V instruction set and the CodAL language, which is used to describe the instruction sets and the processor architectures. The main goal of this work is to implement a model with a 32-bit address space, RISC-V basic instruction set and bit manipulations instruction set. The processor's design have two models, which one is instruction model and second is RTL model. The resulting parameters of the designed processor are measured using a Genus Synthesis Solution tool. The usability of bit manipulations based on decoder coverage is also included in the measurement.
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Bjäreholt, Johan. "RISC-V Compiler Performance:A Comparison between GCC and LLVM/clang." Thesis, Blekinge Tekniska Högskola, Institutionen för programvaruteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-14659.

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RISC-V is a new open-source instruction set architecture (ISA) that in De-cember 2016 manufactured its rst mass-produced processors. It focuses onboth eciency and performance and diers from other open-source architec-tures by not having a copyleft license permitting vendors to freely design,manufacture and sell RISC-V chips without any fees nor having to sharetheir modications on the reference implementations of the architecture.The goal of this thesis is to evaluate the performance of the GCC andLLVM/clang compilers support for the RISC-V target and their ability tooptimize for the architecture. The performance will be evaluated from ex-ecuting the CoreMark and Dhrystone benchmarks are both popular indus-try standard programs for evaluating performance on embedded processors.They will be run on both the GCC and LLVM/clang compilers on dierentoptimization levels and compared in performance per clock to the ARM archi-tecture which is mature yet rather similar to RISC-V. The compiler supportfor the RISC-V target is still in development and the focus of this thesis willbe the current performance dierences between the GCC and LLVM com-pilers on this architecture. The platform we will execute the benchmarks onwil be the Freedom E310 processor on the SiFive HiFive1 board for RISC-Vand a ARM Cortex-M4 processor by Freescale on the Teensy 3.6 board. TheFreedom E310 is almost identical to the reference Berkeley Rocket RISC-Vdesign and the ARM Coretex-M4 processor has a similar clock speed and isaimed at a similar target audience.The results presented that the -O2 and -O3 optimization levels on GCCfor RISC-V performed very well in comparison to our ARM reference. Onthe lower -O1 optimization level and -O0 which is no optimizations and -Oswhich is -O0 with optimizations for generating a smaller executable code sizeGCC performs much worse than ARM at 46% of the performance at -O1,8.2% at -Os and 9.3% at -O0 on the CoreMark benchmark with similar resultsin Dhrystone except on -O1 where it performed as well as ARM. When turn-ing o optimizations (-O0) GCC for RISC-V was 9.2% of the performanceon ARM in CoreMark and 11% in Dhrystone which was unexpected andneeds further investigation. LLVM/clang on the other hand crashed whentrying to compile our CoreMark benchmark and on Dhrystone the optimiza-tion options made a very minor impact on performance making it 6.0% theperformance of GCC on -O3 and 5.6% of the performance of ARM on -O3, soeven with optimizations it was still slower than GCC without optimizations.In conclusion the performance of RISC-V with the GCC compiler onthe higher optimization levels performs very well considering how young theRISC-V architecture is. It does seems like there could be room for improvement on the lower optimization levels however which in turn could also pos-sibly increase the performance of the higher optimization levels. With theLLVM/clang compiler on the other hand a lot of work needs to be done tomake it competetive in both performance and stability with the GCC com-piler and other architectures. Why the -O0 optimization is so considerablyslower on RISC-V than on ARM was also very unexpected and needs furtherinvestigation.
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Books on the topic "RISC-V"

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Smith, Stephen. RISC-V Assembly Language Programming. Berkeley, CA: Apress, 2024. http://dx.doi.org/10.1007/979-8-8688-0137-2.

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International Conference on the Impact of Environmental Factors on Health (5th 2009 New Forest, District, England). Environmental health risk V. Edited by Brebbia C. A. Southampton: WIT Press, 2009.

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Zhivetin, Vladimir. Nauchnyĭ risk: Vvedenie v analiz. Moskva: In-t problem riska, 2008.

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Kuzmanova-Kartalova, Rozalii︠a︡. Sot︠s︡ialnopedagogicheska rabota s det︠s︡a v risk. V. [Veliko] Tŭrnovo: Universitetsko izdatelstvo "Sv. sv. Kiril i Metodiĭ", 2013.

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Al'gin, A. P. Risk i ego rol' v obshchestvennoi zhizni. Moskva: Mysl', 1989.

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Knobloch, Iva. Odvaha a risk: Století designu v UPM. Praha: Uměleckoprůmyslové muzeum, 2019.

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Alʹgin, A. P. Risk i ego rolʹ v obshchestvennoĭ zhizni. Moskva: "Myslʹ", 1989.

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I, Okseni͡uk G., and Biologo-pochvennyĭ institut (Akademii͡a nauk SSSR), eds. Vozbuditeli gribnykh bolezneĭ risa v Primorskom krae. Vladivostok: DVO AN SSSR, 1987.

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Kerim, Yildiz, Kurdish Human Rights Project, European Court of Human Rights., and İnsan Hakları Derneği (Turkey), eds. Kaya v. Turkey & Kiliç v. Turkey: Failure to protect victims at risk. London: Kurdish Human Rights Project, 2001.

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Zhukovskiĭ, Vladislav Iosifovich. Risk v mnogokriterialʹnykh i konfliktnykh sistemakh pri neopredelennosti. Moskva: Ėditorial URSS, 2004.

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Book chapters on the topic "RISC-V"

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Morgan, Fearghal, Arthur Beretta, Ian Gallivan, Joseph Clancy, Frédéric Rousseau, Roshan George, László Bakó, and Frank Callaly. "RISC-V Online Tutor." In Lecture Notes in Networks and Systems, 131–43. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-82529-4_14.

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Goossens, Bernard. "The RISC-V Architecture." In Undergraduate Topics in Computer Science, 105–22. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-18023-1_4.

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Lupori, Leandro, Vanderson Martins do Rosario, and Edson Borin. "High-Performance RISC-V Emulation." In Communications in Computer and Information Science, 135–51. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-41050-6_9.

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Goossens, Bernard. "Testing Your RISC-V Processor." In Undergraduate Topics in Computer Science, 201–31. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-18023-1_7.

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Goossens, Bernard. "A Multicore RISC-V Processor." In Undergraduate Topics in Computer Science, 377–99. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-18023-1_12.

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Goossens, Bernard. "Building a RISC-V Processor." In Undergraduate Topics in Computer Science, 183–200. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-18023-1_6.

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Lee, Joseph K. L., Maurice Jamieson, and Nick Brown. "Backporting RISC-V Vector Assembly." In Lecture Notes in Computer Science, 433–43. Cham: Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-40843-4_32.

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Smith, Stephen. "Interacting with C and Python." In RISC-V Assembly Language Programming, 189–212. Berkeley, CA: Apress, 2024. http://dx.doi.org/10.1007/979-8-8688-0137-2_9.

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Smith, Stephen. "Floating-Point Operations." In RISC-V Assembly Language Programming, 233–58. Berkeley, CA: Apress, 2024. http://dx.doi.org/10.1007/979-8-8688-0137-2_11.

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Smith, Stephen. "Thanks for the Memories." In RISC-V Assembly Language Programming, 89–115. Berkeley, CA: Apress, 2024. http://dx.doi.org/10.1007/979-8-8688-0137-2_5.

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Conference papers on the topic "RISC-V"

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Liu, Qiankun, Sam Amiri, and Luciano Ost. "Exploring RISC-V Based DNN Accelerators." In 2024 IEEE International Conference on Omni-layer Intelligent Systems (COINS), 1–6. IEEE, 2024. http://dx.doi.org/10.1109/coins61597.2024.10622495.

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K, Paldurai, Srivarsa T, Ashwin Kumar S, Bharath Ram K, and Chandra Prakash S. "UVM Verification of RISC-V Instruction set." In 2024 International Conference on Smart Systems for Electrical, Electronics, Communication and Computer Engineering (ICSSEECC), 301–5. IEEE, 2024. http://dx.doi.org/10.1109/icsseecc61126.2024.10649455.

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Schupp, Jonas, Patrick Karl, Jens Nöpel, Alexander Hepp, Tim Music, and Georg Sigl. "RISC-V Triplet: Tapeouts for Security Applications." In 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 1–6. IEEE, 2024. http://dx.doi.org/10.1109/norcas64408.2024.10752453.

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Meeradevi, T., K. Mohanraj, B. M. Mourissh, V. Santhosh Sivaa, Ravi Samikannu, and S. Sasikala. "Design of 32 Bit RISC V Processor." In 2024 15th International Conference on Computing Communication and Networking Technologies (ICCCNT), 1–7. IEEE, 2024. http://dx.doi.org/10.1109/icccnt61001.2024.10726132.

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Yamazawa, Akira, Tsutomu Itou, Kazutoshi Suito, and Nobuyuki Yamasaki. "Context Cache for Multicore RISC-V Processor." In 2024 Twelfth International Symposium on Computing and Networking (CANDAR), 272–78. IEEE, 2024. https://doi.org/10.1109/candar64496.2024.00043.

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Naylor, Matthew, Alexandre Joannou, A. Theodore Markettos, Paul Metzger, Simon W. Moore, and Timothy M. Jones. "Advanced Dynamic Scalarisation for RISC-V GPGPUs." In 2024 IEEE 42nd International Conference on Computer Design (ICCD), 260–67. IEEE, 2024. https://doi.org/10.1109/iccd63220.2024.00047.

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Ben-Asher, Yosi, and Ibrahim Qashqoush. "An Extended pipeline RISC-V CPU architecture." In 2024 IEEE 17th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 517–23. IEEE, 2024. https://doi.org/10.1109/mcsoc64144.2024.00090.

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Zekany, Stephen A., Jielun Tan, James A. Connelly, and Ronald G. Dreslinski. "RISC-V Reward." In SIGCSE '21: The 52nd ACM Technical Symposium on Computer Science Education. New York, NY, USA: ACM, 2021. http://dx.doi.org/10.1145/3408877.3432472.

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Nitta, Christopher, Aaron Kaloti, and Shuotong Wang. "RISC-V Console." In ITiCSE 2022: Innovation and Technology in Computer Science Education. New York, NY, USA: ACM, 2022. http://dx.doi.org/10.1145/3502718.3524791.

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Rogan, Sam, and Yoshihito Kondo. "RISC-V Is Inevitable." In 2023 International Conference on IC Design and Technology (ICICDT). IEEE, 2023. http://dx.doi.org/10.1109/icicdt59917.2023.10332314.

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Reports on the topic "RISC-V"

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Waterman, Andrew, Yunsup Lee, David A. Patterson, and Krste Asanovi. The RISC-V Instruction Set Manual. Volume 1: User-Level ISA, Version 2.0. Fort Belvoir, VA: Defense Technical Information Center, May 2014. http://dx.doi.org/10.21236/ada605735.

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Lavell, Allan M., and Omar D. Cardona. Institutional Budgetary Resources, Sources of Public and Private Funds for Financial Protection and Risk Reduction Incentives: Situational Analysis. Inter-American Development Bank, June 2005. http://dx.doi.org/10.18235/0006684.

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This presentation was commissioned by the Natural Disaster Network of the Regional Policy Dialogue for the V Hemispheric Meeting celebrated on June 13th and 14th, 2005. Institutional, Legal And Public Policy And Planning Aspects Of Disaster Risk Management.
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Backus, George A., Thomas Stephen Lowry, Shannon M. Jones, La Tonya Nicole Walker, Barry L. Roberts, and Leonard A. Malczynski. County-Level Climate Uncertainty for Risk Assessments: Volume 23 Appendix V - Forecast Sea Ice Thickness. Office of Scientific and Technical Information (OSTI), April 2017. http://dx.doi.org/10.2172/1365483.

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Wahl, L. E. A comparison of radiological risk assessment models: Risk assessment models used by the BEIR V Committee, UNSCEAR, ICRP, and EPA (for NESHAP). Office of Scientific and Technical Information (OSTI), March 1994. http://dx.doi.org/10.2172/10141938.

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Levi, Brittany E. Choledochal Cysts: In Brief with Dr. Alexander Bondoc. Stay Current, May 2022. http://dx.doi.org/10.47465/sc1.

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Choledochal cysts are a core pathology in pediatric surgery, affecting 1/100,000 live births in the western world, and 1/13,000 in eastern asia. These cysts are classified by the Todani classification, types I-V, in respect to their location and underlying pathophysiology. Infants and children presenting with stigmata of biliary disease should undergo evaluation for choledocal cyst. Workup includes axial imaging, ultrasonography, and laboratory investigation. A liver biopsy is necessary in neonates and newborns to rule out cystic biliary atresia, which would require further evaluation and management. Large choledochal cysts may be visualized on prenatal ultrasound, and warrant referral to a fetal care center for postnatal work up and monitoring. Management of choledochal cysts is dependent on the anatomic variant and spans from ERCP with sphincterotomy, to cyst excision with ductal and alimentary tract reconstruction. Type V choledochal cysts may require liver transplantation. Long term follow up is required due to an enhanced risk of future malignancy, even after resection.
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Levi, Brittany E., Rodrigo G. Gerardo, Alexander J. Bondoc, Rachel E. Hanke, Chandler Gibson, Ellen M. Encisco, and Todd A. Ponsky. Choledochal Cysts: In Brief with Dr. Alexander Bondoc. Stay Current, May 2022. http://dx.doi.org/10.47465/sc00001.

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Choledochal cysts are a core pathology in pediatric surgery, affecting 1/100,000 live births in the western world, and 1/13,000 in eastern asia. These cysts are classified by the Todani classification, types I-V, in respect to their location and underlying pathophysiology. Infants and children presenting with stigmata of biliary disease should undergo evaluation for choledocal cyst. Workup includes axial imaging, ultrasonography, and laboratory investigation. A liver biopsy is necessary in neonates and newborns to rule out cystic biliary atresia, which would require further evaluation and management. Large choledochal cysts may be visualized on prenatal ultrasound, and warrant referral to a fetal care center for postnatal work up and monitoring. Management of choledochal cysts is dependent on the anatomic variant and spans from ERCP with sphincterotomy, to cyst excision with ductal and alimentary tract reconstruction. Type V choledochal cysts may require liver transplantation. Long term follow up is required due to an enhanced risk of future malignancy, even after resection.
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Travis, Amanda, Margaret Harvey, and Michelle Rickard. Adverse Childhood Experiences and Urinary Incontinence in Elementary School Aged Children. University of Tennessee Health Science Center, October 2021. http://dx.doi.org/10.21007/con.dnp.2021.0012.

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Purpose/Background: Adverse Childhood Experiences (ACEs) have an impact on health throughout the lifespan (Filletti et al., 1999; Hughes et al., 2017). These experiences range from physical and mental abuse, substance abuse in the home, parental separation or loss, financial instability, acute illness or injury, witnessing violence in the home or community, and incarceration of family members (Hughes et al., 2017). Understanding and screening for ACEs in children with urinary incontinence can help practitioners identify psychological stress as a potentially modifiable risk factor. Methods: A 5-month chart review was performed identifying English speaking patients ages 6-11 years presenting to the outpatient urology office for an initial visit with a primary diagnosis of urinary incontinence. Charts were reviewed for documentation of individual or family risk factors for ACEs exposure, community risk factors for ACEs exposures, and records where no related documentation was included. Results: For the thirty-nine patients identified, no community risk factors were noted in the charts. Seventy-nine percent of patients had one or more individual or family risk factors documented. Implications for Nursing Practice This chart review indicates that a significant percentage of pediatric, school-aged patients presenting with urinary incontinence have exposure to ACEs. A formal assessment for ACEs at the time of initial presentation would be helpful to identify those at highest risk. References: Felitti VJ, Anda RF, Nordenberg D, Williamson DF, Spitz AM, Edwards V, Koss MP, Marks JS. Relationship of childhood abuse and household dysfunction to many of the leading causes of death in adults: the adverse childhood experiences (ACE) study. Am J Prev Med. 1998;14:245–258 Hughes, K., Bellis, M.A., Hardcastle, K.A., Sethi, D., Butchart, D., Mikton, C., Jones, L., Dunne, M.P. (2017) The effect of multiple adverse childhood experiences on health: a systematic review and meta-analysis. Lancet Public Health, 2(8): e356–e366. Published online 2017 Jul 31.doi: 10.1016/S2468-2667(17)30118-4 Lai, H., Gardner, V., Vetter, J., & Andriole, G. L. (2015). Correlation between psychological stress levels and the severity of overactive bladder symptoms. BMC urology, 15, 14. doi:10.1186/s12894-015-0009-6
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Terusaki, Stanley. Soil Sample Workplan in Support of the Site 300 Explosives Waste Treatment Facility Ecological Risk Assessment Pursuant to the Hazardous Waste Facility Permit (Part V, Special Condition #14 a-f). Office of Scientific and Technical Information (OSTI), June 2021. http://dx.doi.org/10.2172/1806413.

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Ramírez Rodríguez, Santiago. Violence and Crime in Nicaragua: A Country Profile. Inter-American Development Bank, June 2013. http://dx.doi.org/10.18235/0006969.

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The Office of Evaluation and Oversight (OVE) conducted an evaluation of a cluster of citizen security projects. The main objective was to identify what factors explained the implementation performance of the projects, and what lessons could be learned from these experiences. This Background Paper presents the results of one of these diagnostics for Nicaragua. Following the introduction, the country profile begins with an overview of the Nicaraguan context in terms of geography, demographics, economy, as well as recent political history (section II). It then builds a diagnostic that covers different forms of violence and crime (section III) as well as main risk and protective factors (section IV), based on available statistics and specialized international and local literature. In section V, the paper reviews the strategy adopted by the Government throughout the last decade to respond to main forms of violence and crime, it describes the budget allocation to citizen security over recent years. Finally, section VI presents the IDB citizen security project part of the comparative evaluation, and summarizes various exercises that OVE undertook to provide additional background information and analysis.
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Terusaki, Stanley. Soil Sample Plan in Support of the Site 300 Explosives Waste Treatment Facility Ecological Risk Assessment Pursuant to the Hazardous Waste Facility Permit, Part V, Special Condition #14 a-f. August 2020. Office of Scientific and Technical Information (OSTI), July 2020. http://dx.doi.org/10.2172/1646560.

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