Log in

Relevant bibliographies by topics / RISC V processor / Journal articles

To see the other types of publications on this topic, follow the link: RISC V processor.

Journal articles on the topic 'RISC V processor'

Author: Grafiati

Published: 6 September 2023

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the top 50 journal articles for your research on the topic 'RISC V processor.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Browse journal articles on a wide variety of disciplines and organise your bibliography correctly.

1

Pitcher, Graham. "RISC-V Powers IoT Apps Processor." New Electronics 51, no. 4 (2018): 7. http://dx.doi.org/10.12968/s0047-9624(23)60141-5.

Full text

APA, Harvard, Vancouver, ISO, and other styles

2

Gamino del Río, Iván, Agustín Martínez Hellín, Óscar R. Polo, et al. "A RISC-V Processor Design for Transparent Tracing." Electronics 9, no. 11 (2020): 1873. http://dx.doi.org/10.3390/electronics9111873.

Full text

Abstract:

Code instrumentation enables the observability of an embedded software system during its execution. A usage example of code instrumentation is the estimation of “worst-case execution time” using hybrid analysis. This analysis combines static code analysis with measurements of the execution time on the deployment platform. Static analysis of source code determines where to insert the tracing instructions, so that later, the execution time can be captured using a logic analyser. The main drawback of this technique is the overhead introduced by the execution of trace instructions. This paper prop

APA, Harvard, Vancouver, ISO, and other styles

3

Hongsheng, Zhang, Zekun Jiang, and Yong Li. "Design of a dual-issue RISC-V processor." Journal of Physics: Conference Series 1693 (December 2020): 012192. http://dx.doi.org/10.1088/1742-6596/1693/1/012192.

Full text

APA, Harvard, Vancouver, ISO, and other styles

4

An, Hyogeun, Sudong Kang, Guard Kanda, and Kwangki Ryoo. "RISC-V Hardware Synthesizable Processor Design Test and Verification Using User-Friendly Desktop Application." Webology 19, no. 1 (2022): 4597–620. http://dx.doi.org/10.14704/web/v19i1/web19305.

Full text

Abstract:

Although the RISC-V ISA has not been around for long, it is a processor architecture that has been highlighted by many businesses and individuals for its low-cost and rapid pace of development. They are open-source-synthesizable hardware processors with minimal functionality that is ideal for current IoT applications involving simple sensors and actuator controls. Due to some qualities of hardware, they can operate in areas where software programs and applications cannot be used whereas, these software programs that run on such hardware equally help in understanding how hardware operates. This

APA, Harvard, Vancouver, ISO, and other styles

5

Núñez-Prieto, Ricardo, David Castells-Rufas, and Lluís Terés-Terés. "RisCO2: Implementation and Performance Evaluation of RISC-V Processors for Low-Power CO2 Concentration Sensing." Micromachines 14, no. 7 (2023): 1371. http://dx.doi.org/10.3390/mi14071371.

Full text

Abstract:

In the field of embedded systems, energy efficiency is a critical requirement, particularly for battery-powered devices. RISC-V processors have gained popularity due to their flexibility and open-source nature, making them an attractive choice for embedded applications. However, not all RISC-V processors are equally energy-efficient, and evaluating their performance in specific use cases is essential. This paper presents RisCO2, an RISC-V implementation optimized for energy efficiency. It evaluates its performance compared to other RISC-V processors in terms of resource utilization and energy

APA, Harvard, Vancouver, ISO, and other styles

6

Michel Deves de Souza, Eduardo, Nathalia Nathalia Adriana de Oliveira, Douglas Almeida dos Santos Almeida dos Santos, and Douglas Rossi de Melo. "RVSH - Um processador RISC-V para fins didáticos." Anais do Computer on the Beach 14 (May 3, 2023): 450–52. http://dx.doi.org/10.14210/cotb.v14.p450-452.

Full text

Abstract:

ABSTRACTEmbedded systems constitute the class of computers that presentthe most significant volume and are increasingly present ineveryday life. The main element of these systems is the processor,which can be found in discrete form, represented by a physicalcomponent, or cores, as used in programmable logic devices.Processors of the same architecture share the same instructionset but may differ in the organization’s implementation. RISC(Reduced Instruction Set Computer) is the class of architecturesthat favors a simple, reduced instruction set. RISC-V is an exampleof such architecture, which c

APA, Harvard, Vancouver, ISO, and other styles

7

Zhou, Weixin, Dehua Wu, Wan’ang Xiao, Shan Gao, and Wanlin Gao. "A Novel Sleep Scheduling Strategy on RISC-V Processor." Journal of Physics: Conference Series 1631 (September 2020): 012028. http://dx.doi.org/10.1088/1742-6596/1631/1/012028.

Full text

APA, Harvard, Vancouver, ISO, and other styles

8

Xue, Wang, Liu, Lv, Wang, and Zeng. "An RISC-V Processor with Area-Efficient Memristor-Based In-Memory Computing for Hash Algorithm in Blockchain Applications." Micromachines 10, no. 8 (2019): 541. http://dx.doi.org/10.3390/mi10080541.

Full text

Abstract:

Blockchain technology is increasingly being used in Internet of things (IoT) devices for information security and data integrity. However, it is challenging to implement complex hash algorithms with limited resources in IoT devices owing to large energy consumption and a long processing time. This paper proposes an RISC-V processor with memristor-based in-memory computing (IMC) for blockchain technology in IoT applications. The IMC-adapted instructions were designed for the Keccak hash algorithm by virtue of the extendibility of the RISC-V instruction set architecture (ISA). Then, an RISC-V pr

APA, Harvard, Vancouver, ISO, and other styles

9

Santos, Douglas A., André M. P. Mattos, Douglas R. Melo, and Luigi Dilillo. "Enhancing Fault Awareness and Reliability of a Fault-Tolerant RISC-V System-on-Chip." Electronics 12, no. 12 (2023): 2557. http://dx.doi.org/10.3390/electronics12122557.

Full text

Abstract:

Recent research has shown interest in adopting the RISC-V processors for high-reliability electronics, such as aerospace applications. The openness of this architecture enables the implementation and customization of the processor features to increase their reliability. Studies on hardened RISC-V processors facing harsh radiation environments apply fault tolerance techniques in the processor core and peripherals, exploiting system redundancies. In prior work, we present a hardened RISC-V System-on-Chip (SoC), which could detect and correct radiation-induced faults with limited fault awareness.

APA, Harvard, Vancouver, ISO, and other styles

10

Gomes, Tiago, Pedro Sousa, Miguel Silva, Mongkol Ekpanyapong, and Sandro Pinto. "FAC-V: An FPGA-Based AES Coprocessor for RISC-V." Journal of Low Power Electronics and Applications 12, no. 4 (2022): 50. http://dx.doi.org/10.3390/jlpea12040050.

Full text

Abstract:

In the new Internet of Things (IoT) era, embedded Field-Programmable Gate Array (FPGA) technology is enabling the deployment of custom-tailored embedded IoT solutions for handling different application requirements and workloads. Combined with the open RISC-V Instruction Set Architecture (ISA), the FPGA technology provides endless opportunities to create reconfigurable IoT devices with different accelerators and coprocessors tightly and loosely coupled with the processor. When connecting IoT devices to the Internet, secure communications and data exchange are major concerns. However, adding se

APA, Harvard, Vancouver, ISO, and other styles

11

Pietzsch, Marcus. "RISC-V Processor for Network Platforms According to ISO 26262." ATZelectronics worldwide 16, no. 11 (2021): 8–13. http://dx.doi.org/10.1007/s38314-021-0691-y.

Full text

APA, Harvard, Vancouver, ISO, and other styles

12

Gao, Shan, Wan’ang Xiao, Zhenghong Yang, Dehua Wu, and Wanlin Gao. "A fast on-chip debugging design for RISC-V processor." Journal of Physics: Conference Series 1976, no. 1 (2021): 012056. http://dx.doi.org/10.1088/1742-6596/1976/1/012056.

Full text

APA, Harvard, Vancouver, ISO, and other styles

13

Cheng, Yuan-Hu, Li-Bo Huang, Yi-Jun Cui, Sheng Ma, Yong-Wen Wang, and Bing-Cai Sui. "RV16: An Ultra-Low-Cost Embedded RISC-V Processor Core." Journal of Computer Science and Technology 37, no. 6 (2022): 1307–19. http://dx.doi.org/10.1007/s11390-022-0910-x.

Full text

APA, Harvard, Vancouver, ISO, and other styles

14

Jamieson, Peter, Huan Le, Nathan Martin, et al. "Computer Engineering Education Experiences with RISC-V Architectures—From Computer Architecture to Microcontrollers." Journal of Low Power Electronics and Applications 12, no. 3 (2022): 45. http://dx.doi.org/10.3390/jlpea12030045.

Full text

Abstract:

With the growing popularity of RISC-V and various open-source released RISC-V processors, it is now possible for computer engineers students to explore this simple and relevant architecture, and also, these students can explore and design a microcontroller at a low-level using real tool-flows and implement and test their hardware. In this work, we describe our experiences with undergraduate engineers building RISC-V architectures on an FPGA and then extending their experiences to implement an Arduino-like RISC-V tool-flow and the respective hardware and software to handle input-output ports, i

APA, Harvard, Vancouver, ISO, and other styles

15

B, Rajeshwari, Rithvik Kumar, Shweta P. Hegde, Manav Eswar Prasad, Vandhya D M, and Bajrangabali B. "Dual Quaternion Hardware Accelerator for RISC-V based System." International Journal of Research and Scientific Innovation 09, no. 05 (2022): 77–81. http://dx.doi.org/10.51244/ijrsi.2022.9506.

Full text

Abstract:

In this work, a hardware accelerator has been developed for a RISC-V processor. The ‘Parashu’ Shakti processor is the SoC of choice for application testing and development. The IP is designed to speed up applications involving dual quaternion operations. Our module primarily aids dual quaternion multiplication which further helps with other complex operations like translation, rotation and transformation. Two solutions have been proposed for the same, i.e. either a quaternion IP if power and resource utilization is a concern, or a dual quaternion IP if performance gain is the primary objective

APA, Harvard, Vancouver, ISO, and other styles

16

Lim, Seung-Ho, WoonSik William Suh, Jin-Young Kim, and Sang-Young Cho. "RISC-V Virtual Platform-Based Convolutional Neural Network Accelerator Implemented in SystemC." Electronics 10, no. 13 (2021): 1514. http://dx.doi.org/10.3390/electronics10131514.

Full text

Abstract:

The optimization for hardware processor and system for performing deep learning operations such as Convolutional Neural Networks (CNN) in resource limited embedded devices are recent active research area. In order to perform an optimized deep neural network model using the limited computational unit and memory of an embedded device, it is necessary to quickly apply various configurations of hardware modules to various deep neural network models and find the optimal combination. The Electronic System Level (ESL) Simulator based on SystemC is very useful for rapid hardware modeling and verificat

APA, Harvard, Vancouver, ISO, and other styles

17

Gao, Shan, Dehua Wu, Wan’ang Xiao, Zetao Wang, Zhenghong Yang, and Wanlin Gao. "A novel method for on-chip debugging based on RISC-V processor." MATEC Web of Conferences 355 (2022): 03055. http://dx.doi.org/10.1051/matecconf/202235503055.

Full text

Abstract:

An on-chip debugging method based on the RISC-V processor is introduced, which simplifies the complicated debugging operation into instructions and improves the debugging efficiency effectively. The method adopts a JTAG interface to realize the debugging functions of the processor, such as running control, software breakpoint, hardware breakpoint and single-step execution. The method was verified by simulation at the RTL level, and the logic synthesis was carried out in SMIC 180nm process library.

APA, Harvard, Vancouver, ISO, and other styles

18

MIYAZAKI, Hiromu, Takuto KANAMORI, Md Ashraful ISLAM, and Kenji KISE. "RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining." IEICE Transactions on Information and Systems E103.D, no. 12 (2020): 2494–503. http://dx.doi.org/10.1587/transinf.2020pap0015.

Full text

APA, Harvard, Vancouver, ISO, and other styles

19

Li, Jiemin, Shancong Zhang, and Chong Bao. "DuckCore: A Fault-Tolerant Processor Core Architecture Based on the RISC-V ISA." Electronics 11, no. 1 (2021): 122. http://dx.doi.org/10.3390/electronics11010122.

Full text

Abstract:

With the development of large-scale CMOS-integrated circuit manufacturing technology, microprocessor chips are more vulnerable to soft errors and radiation interference, resulting in reduced reliability. Core reliability is an important element of the microprocessor’s ability to resist soft errors. This paper proposes DuckCore, a fault-tolerant processor core architecture based on the free and open instruction set architecture (ISA) RISC-V. This architecture uses improved SECDED (single error correction, double error detection) code between pipelines, detects processor operating errors in real

APA, Harvard, Vancouver, ISO, and other styles

20

Patrick, Mark. "What's all the Hype About?" New Electronics 53, no. 14 (2020): 22–23. http://dx.doi.org/10.12968/s0047-9624(22)61362-2.

Full text

APA, Harvard, Vancouver, ISO, and other styles

21

Kwon, Donghyun, Dongil Hwang, and Yunheung Paek. "A Hardware Platform for Ensuring OS Kernel Integrity on RISC-V." Electronics 10, no. 17 (2021): 2068. http://dx.doi.org/10.3390/electronics10172068.

Full text

Abstract:

The OS kernel is typically preassumed as a trusted computing base in most computing systems. However, it also implies that once an attacker takes control of the OS kernel, the attacker can seize the entire system. Because of such security importance of the OS kernel, many works have proposed security solutions for the OS kernel using an external hardware module located outside the processor. By doing this, these works can realize the physical isolation of security solutions from the OS kernel running in the processor, but they cannot access the inner state of the processor, which attackers can

APA, Harvard, Vancouver, ISO, and other styles

22

Cococcioni, Marco, Federico Rossi, Emanuele Ruffaldi, and Sergio Saponara. "Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE." Neural Computing and Applications 33, no. 16 (2021): 10575–85. http://dx.doi.org/10.1007/s00521-021-05814-0.

Full text

Abstract:

AbstractWith the arrival of the open-source RISC-V processor architecture, there is the chance to rethink Deep Neural Networks (DNNs) and information representation and processing. In this work, we will exploit the following ideas: i) reduce the number of bits needed to represent the weights of the DNNs using our recent findings and implementation of the posit number system, ii) exploit RISC-V vectorization as much as possible to speed up the format encoding/decoding, the evaluation of activations functions (using only arithmetic and logic operations, exploiting approximated formulas) and the

APA, Harvard, Vancouver, ISO, and other styles

23

Li, Zhiyu, Yuhao Huang, Longfeng Tian, Ruimin Zhu, Shanlin Xiao, and Zhiyi Yu. "A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method." IEEE Transactions on Circuits and Systems II: Express Briefs 68, no. 9 (2021): 3153–57. http://dx.doi.org/10.1109/tcsii.2021.3100524.

Full text

APA, Harvard, Vancouver, ISO, and other styles

24

Murabayashi, F., T. Yamauchi, H. Yamada, et al. "2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor." IEEE Journal of Solid-State Circuits 31, no. 7 (1996): 972–80. http://dx.doi.org/10.1109/4.508211.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

Zhang, Haifeng, Xiaoti Wu, Yuyu Du, et al. "A Heterogeneous RISC-V Processor for Efficient DNN Application in Smart Sensing System." Sensors 21, no. 19 (2021): 6491. http://dx.doi.org/10.3390/s21196491.

Full text

Abstract:

Extracting features from sensing data on edge devices is a challenging application for which deep neural networks (DNN) have shown promising results. Unfortunately, the general micro-controller-class processors which are widely used in sensing system fail to achieve real-time inference. Accelerating the compute-intensive DNN inference is, therefore, of utmost importance. As the physical limitation of sensing devices, the design of processor needs to meet the balanced performance metrics, including low power consumption, low latency, and flexible configuration. In this paper, we proposed a ligh

APA, Harvard, Vancouver, ISO, and other styles

26

Schmidt, Colin, John Wright, Zhongkai Wang, et al. "An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET." IEEE Journal of Solid-State Circuits 57, no. 1 (2022): 140–52. http://dx.doi.org/10.1109/jssc.2021.3118046.

Full text

APA, Harvard, Vancouver, ISO, and other styles

27

Tada, Jubee, and Keiichi Sato. "An Implementation of a Grid Square Codes Generator on a RISC-V Processor." International Journal of Networking and Computing 12, no. 1 (2022): 204–17. http://dx.doi.org/10.15803/ijnc.12.1_204.

Full text

APA, Harvard, Vancouver, ISO, and other styles

28

de Oliveira, Adria B., Lucas A. Tambara, Fabio Benevenuti, et al. "Evaluating Soft Core RISC-V Processor in SRAM-Based FPGA Under Radiation Effects." IEEE Transactions on Nuclear Science 67, no. 7 (2020): 1503–10. http://dx.doi.org/10.1109/tns.2020.2995729.

Full text

APA, Harvard, Vancouver, ISO, and other styles

29

Cho, Hyungmin. "Impact of Microarchitectural Differences of RISC-V Processor Cores on Soft Error Effects." IEEE Access 6 (2018): 41302–13. http://dx.doi.org/10.1109/access.2018.2858773.

Full text

APA, Harvard, Vancouver, ISO, and other styles

30

Kaneko, Hiroaki, and Akinori Kanasugi. "An integrated machine code monitor for a RISC-V processor on an FPGA." Artificial Life and Robotics 25, no. 3 (2020): 427–33. http://dx.doi.org/10.1007/s10015-020-00593-8.

Full text

APA, Harvard, Vancouver, ISO, and other styles

31

Garofalo, Angelo, Manuele Rusci, Francesco Conti, Davide Rossi, and Luca Benini. "PULP-NN: accelerating quantized neural networks on parallel ultra-low-power RISC-V processors." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 378, no. 2164 (2019): 20190155. http://dx.doi.org/10.1098/rsta.2019.0155.

Full text

Abstract:

We present PULP-NN, an optimized computing library for a parallel ultra-low-power tightly coupled cluster of RISC-V processors. The key innovation in PULP-NN is a set of kernels for quantized neural network inference, targeting byte and sub-byte data types, down to INT-1, tuned for the recent trend toward aggressive quantization in deep neural network inference. The proposed library exploits both the digital signal processing extensions available in the PULP RISC-V processors and the cluster’s parallelism, achieving up to 15.5 MACs/cycle on INT-8 and improving performance by up to 63 × with re

APA, Harvard, Vancouver, ISO, and other styles

32

C, Rohan. "Design of a 32-Bit, Dual Pipeline Superscalar RISC-V Processor on FPGA: A Review." International Journal for Research in Applied Science and Engineering Technology 10, no. 6 (2022): 4044–46. http://dx.doi.org/10.22214/ijraset.2022.44654.

Full text

Abstract:

Abstract: A 40 MHz with 32-bit and 5-stage dual-pipeline superscalar processor based on RISC-V Instruction Set Architecture is presented. It supports integer, multiply-divide and atomic read-modify-write operations. The proposed system implements inorder issuing of instructions. The design includes a dynamic branch prediction unit, memory subsystem with virtual memory, separate instruction cache and data cache, integer and floating-point execution units, interrupt controller, error control module, and a UART peripheral. Individual interrupts can have up to four levels of primary priority set i

APA, Harvard, Vancouver, ISO, and other styles

33

Yu, Hongjiang, Guoshun Yuan, Dewei Kong, and Chuhuai Chen. "An Optimized Implementation of Activation Instruction Based on RISC-V." Electronics 12, no. 9 (2023): 1986. http://dx.doi.org/10.3390/electronics12091986.

Full text

Abstract:

Activation is an important component of the neural network, and the standard instructions of RISC-V are difficult to use to effectively handle the activation of the array. In this paper, we propose an optimized implementation of activation instruction based on RISC-V. Based on the opensource RISC-V processor Hummingbird E203, we designed a special instruction for the implementation of activation functions. A single instruction is chosen to implement the entire activation operation, including data loading, data arithmetic and data write-back. At the hardware level, we designed a method of alter

APA, Harvard, Vancouver, ISO, and other styles

34

Kalapothas, Stavros, Manolis Galetakis, Georgios Flamis, Fotis Plessas, and Paris Kitsos. "A Survey on RISC-V-Based Machine Learning Ecosystem." Information 14, no. 2 (2023): 64. http://dx.doi.org/10.3390/info14020064.

Full text

Abstract:

In recent years, the advancements in specialized hardware architectures have supported the industry and the research community to address the computation power needed for more enhanced and compute intensive artificial intelligence (AI) algorithms and applications that have already reached a substantial growth, such as in natural language processing (NLP) and computer vision (CV). The developments of open-source hardware (OSH) and the contribution towards the creation of hardware-based accelerators with implication mainly in machine learning (ML), has also been significant. In particular, the r

APA, Harvard, Vancouver, ISO, and other styles

35

Jaiswal, Nidhi. "Design of High Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications." International Journal for Research in Applied Science and Engineering Technology 11, no. 7 (2023): 734–42. http://dx.doi.org/10.22214/ijraset.2023.54647.

Full text

Abstract:

Abstract: Numerous current and future applications aim to create highly efficient central processing units (CPUs). The RISC V processor micro-architecture is one illustration of a design that satisfies the necessities. The RISC-V Instruction Set Architecture [ISA] provides support for the micro-architecture. The instruction set architecture and the micro-architecture of a processor are two of the most crucial aspects of its design. The multiplier and divider circuits have a relatively high level of hardware complexity compared to other stages of the instruction execution process, which must be

APA, Harvard, Vancouver, ISO, and other styles

36

GuangTang, Jiancheng, and Li. "Research and design of low-power, high-performance processor based on RISC-V instruction set architecture." Journal of Physics: Conference Series 2221, no. 1 (2022): 012008. http://dx.doi.org/10.1088/1742-6596/2221/1/012008.

Full text

Abstract:

Abstract In embedded IoT applications, in order to meet the needs of small area, low power consumption, and high performance, this paper designs a 32-bit low-power, high-performance microprocessor based on the RISC-V instruction set architecture. It uses a 3-stage pipeline structure with static branch prediction function, supports RV32IM instruction set, and adopts AHB bus as the control bus. The logic function of the processor was verified under the iverilog environment, and the simulation results showed that the processor can run normally. The CoreMark score of 2.38 CoreMark/MHz was measured

APA, Harvard, Vancouver, ISO, and other styles

37

Ragini, Dr K., and Nidhi Jaiswal. "Design of High-Performance Core Micro-Architecture Based on 32- Bit RISC-V Instruction Set Architecture [ISA]." International Journal for Research in Applied Science and Engineering Technology 11, no. 7 (2023): 1025–33. http://dx.doi.org/10.22214/ijraset.2023.54791.

Full text

Abstract:

Abstract: A wide range of present and future applications strive to develop highly efficient central processing units (CPUs). One particular design that meets these requirements is the RISC V processor micro-architecture. The RISC-V Instruction Set Architecture (ISA) provides the necessary support for this micro-architecture. The instruction set architecture and microarchitecture are crucial components in processor design. Among these components, the multiplier and divider circuits exhibit a relatively high level of hardware complexity compared to other stages of instruction execution. Therefo

APA, Harvard, Vancouver, ISO, and other styles

38

Nişancı, Görkem, Paul G. Flikkema, and Tolga Yalçın. "Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms." Cryptography 6, no. 3 (2022): 41. http://dx.doi.org/10.3390/cryptography6030041.

Full text

Abstract:

The ever-increasing need for securing computing systems using cryptographic algorithms is spurring interest in the efficient implementation of common algorithms. While the algorithms can be implemented in software using base instruction sets, there is considerable potential to reduce memory cost and improve speed using specialized instructions and associated hardware. However, there is a need to assess the benefits and costs of software implementations and new instructions that implement key cryptographic algorithms in fewer cycles. The primary aim of this paper is to improve the understanding

APA, Harvard, Vancouver, ISO, and other styles

39

Andorno, M., M. Andersen, G. Borghello, et al. "Rad-hard RISC-V SoC and ASIP ecosystems studies for high-energy physics applications." Journal of Instrumentation 18, no. 01 (2023): C01018. http://dx.doi.org/10.1088/1748-0221/18/01/c01018.

Full text

Abstract:

Abstract The increase in complexity and size of modern ASIC designs in the HEP community and the use of advanced semiconductor fabrication processes raises the need for a shift toward a more abstract design methodology, that takes advantage of modularity and programmability to achieve a faster turnaround time both for design and verification. This contribution will present two complementary approaches, one using a RISC-V based System-on-Chip (SoC) and the other based on Application-Specific Instruction set Processors (ASIP). The SoC uses the PicoRV32 open-source RISC-V core and a rad-hard vers

APA, Harvard, Vancouver, ISO, and other styles

40

Rathi, C. Arul, G. Rajakumar, T. Ananth Kumar, and T. S. Arun Samuel. "Design and Development of an Efficient Branch Predictor for an In-order RISC-V Processor." Journal of Nano- and Electronic Physics 12, no. 5 (2020): 05021–1. http://dx.doi.org/10.21272/jnep.12(5).05021.

Full text

APA, Harvard, Vancouver, ISO, and other styles

41

RAO, Jinli, Tianyong AO, Shu XU, Kui DAI, and Xuecheng ZOU. "Design Exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V Processor." IEICE Transactions on Information and Systems E101.D, no. 11 (2018): 2698–705. http://dx.doi.org/10.1587/transinf.2017icp0019.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

Xin, Guozhu, Jun Han, Tianyu Yin, et al. "VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture." IEEE Transactions on Circuits and Systems I: Regular Papers 67, no. 8 (2020): 2672–84. http://dx.doi.org/10.1109/tcsi.2020.2983185.

Full text

APA, Harvard, Vancouver, ISO, and other styles

43

Cho, Hyungmin. "Correction to “Impact of Microarchitectural Differences of RISC-V Processor Cores on Soft Error Effects”." IEEE Access 7 (2019): 35034. http://dx.doi.org/10.1109/access.2019.2904033.

Full text

APA, Harvard, Vancouver, ISO, and other styles

44

Zhou, Yuzhi, Xi Jin, Tian Xiang, and Daolu Zha. "Enhancing energy efficiency of RISC-V processor-based embedded graphics systems through frame buffer compression." Microprocessors and Microsystems 77 (September 2020): 103140. http://dx.doi.org/10.1016/j.micpro.2020.103140.

Full text

APA, Harvard, Vancouver, ISO, and other styles

45

Le, Anh-Tien, Trong-Thuc Hoang, Ba-Anh Dao, Akira Tsukamoto, Kuniyasu Suzaki, and Cong-Kha Pham. "A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment." Computers and Electrical Engineering 105 (January 2023): 108546. http://dx.doi.org/10.1016/j.compeleceng.2022.108546.

Full text

APA, Harvard, Vancouver, ISO, and other styles

46

Zhou, Ziqiao, and Michael K. Reiter. "Interpretable noninterference measurement and its application to processor designs." Proceedings of the ACM on Programming Languages 5, OOPSLA (2021): 1–30. http://dx.doi.org/10.1145/3485518.

Full text

Abstract:

Noninterference measurement quantifies the secret information that might leak to an adversary from what the adversary can observe and influence about the computation. Static and high-fidelity noninterference measurement has been difficult to scale to complex computations, however. This paper scales a recent framework for noninterference measurement to the open-source RISC-V BOOM core as specified in Verilog, through three key innovations: logically characterizing the core’s execution incrementally, applying specific optimizations between each cycle; permitting information to be declassified, t

APA, Harvard, Vancouver, ISO, and other styles

47

Chen, Yuehai, Huarun Chen, Shaozhen Chen, et al. "DITES: A Lightweight and Flexible Dual-Core Isolated Trusted Execution SoC Based on RISC-V." Sensors 22, no. 16 (2022): 5981. http://dx.doi.org/10.3390/s22165981.

Full text

Abstract:

A Trusted Execution Environment (TEE) is an efficient way to secure information. To obtain higher efficiency, the building of a dual-core system-on-chip (SoC) with TEE security capabilities is the hottest topic. However, TEE SoCs currently commonly use complex processor cores such as Rocket, resulting in high resource usage. More importantly, the cryptographic unit lacks flexibility and ignores secure communication in dual cores. To address the above problems, we propose DITES, a dual-core TEE SoC based on a Reduced Instruction Set Computer-V (RISC-V). At first, we designed a fully isolated mu

APA, Harvard, Vancouver, ISO, and other styles

48

Taştan, İbrahim, Mahmut Karaca, and Arda Yurdakul. "Approximate CPU Design for IoT End-Devices with Learning Capabilities." Electronics 9, no. 1 (2020): 125. http://dx.doi.org/10.3390/electronics9010125.

Full text

Abstract:

With the rise of Internet of Things (IoT), low-cost resource-constrained devices have to be more capable than traditional embedded systems, which operate on stringent power budgets. In order to add new capabilities such as learning, the power consumption planning has to be revised. Approximate computing is a promising paradigm for reducing power consumption at the expense of inaccuracy introduced to the computations. In this paper, we set forth approximate computing features of a processor that will exist in the next generation low-cost resource-constrained learning IoT devices. Based on these

APA, Harvard, Vancouver, ISO, and other styles

49

Han, Xiaojing, Liang Liu, Zhe Zhang, Yufeng Sun, Jiahui Zhou, and Hao Cai. "Design of a High Performance Vector Processor Based on RISIC-V Architecture." Journal of Physics: Conference Series 2560, no. 1 (2023): 012027. http://dx.doi.org/10.1088/1742-6596/2560/1/012027.

Full text

Abstract:

Abstract This paper proposes a high performance Vector processor based on the high performance Embedded Core which is named TS800. The TS800 is a 4-core processor based on RISC-V architecture, implements IMAFDV instruction set, supports L2 Cache, branch prediction, sequential pipeline, and dual-issue structure. The traditional CPU mainly supports Scalar calculations, or only supports Vector calculations. For applications such as image and signal processing, there are a large number of data parallel computing operations. To solve the problem of low performance of parallel data calculations in i

APA, Harvard, Vancouver, ISO, and other styles

50

Mach, Ján, Lukáš Kohútka, and Pavel Čičák. "In-Pipeline Processor Protection against Soft Errors." Journal of Low Power Electronics and Applications 13, no. 2 (2023): 33. http://dx.doi.org/10.3390/jlpea13020033.

Full text

Abstract:

The shrinking of technology nodes allows higher performance, but susceptibility to soft errors increases. The protection has been implemented mainly by lockstep or hardened process techniques, which results in a lower frequency, a larger area, and higher power consumption. We propose a protection technique that only slightly affects the maximal frequency. The area and power consumption increase are comparable with dual lockstep architectures. A reaction to faults and the ability to recover from them is similar to triple modular redundancy architectures. The novelty lies in applying redundancy

APA, Harvard, Vancouver, ISO, and other styles

We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!