To see the other types of publications on this topic, follow the link: RISC-V.
Dissertations / Theses on the topic 'RISC-V'
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the top 50 dissertations / theses for your research on the topic 'RISC-V.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.
1
Barták, Jiří. "Model procesoru RISC-V." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2016. http://www.nusl.cz/ntk/nusl-255393.
Full textAbstract:
The number of application specific instruction set processors is rapidly increasing, because of increased demand for low power and small area designs. A lot of new instruction sets are born, but they are usually confidential. University of California in Berkeley took an opposite approach. The RISC-V instruction set is completely free. This master's thesis focuses on analysis of RISC-V instruction set and two programming languages used to model instruction sets and microarchitectures, CodAL and Chisel. Implementation of RISC-V base instruction set along with multiplication, division and 64-bit address space extensions and implementation of cycle accurate model of Rocket Core-like microarchitecture in CodAL are main goals of this master's thesis. The instruction set model is used to generate the C compiler and the cycle accurate model is used to generate RTL representation, all thanks to Codasip Studio. Generated compiler is compared against the one implemented manually and results are used for instruction set optimizations. RTL is synthesized to Artix 7 FPGA and compared to the Rocket Core synthesis.
2
Vavro, Tomáš. "Periferie procesoru RISC-V." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2021. http://www.nusl.cz/ntk/nusl-445553.
Full textAbstract:
The RISC-V platform is one of the leaders in the computer and embedded systems industry. With the increasing use of these systems, the demand for available peripherals for the implementations of this platform is growing. This thesis deals with the FU540-C000 processor from SiFive company, which is one of the implementations of the RISC-V architecture, and its basic peripherals. Based on the analysis, an UART circuit for asynchronous serial communication was selected from the peripherals of this processor. The aim of this master thesis is to design and implement the peripheral in one of the languages for the description of digital circuits, and then create a verification environment, through which the functionality of the implementation will be verified.
3
Benna, Filip. "Generování objektových souborů pro RISC-V." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-363865.
Full textAbstract:
This master’s thesis deals with the topic of program source code compilation for RISC-V processor architecture. The generated object files need to be compatible with GNU binutils open source tools which are already available for the architecture. The focus is on relocations which must be correctly detected in Codasip Studio tools and transformed into RISC-V platform specific relocation types.
4
Skála, Milan. "Prostředí pro spouštění testů kompatibility RISC-V." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2018. http://www.nusl.cz/ntk/nusl-386021.
Full textAbstract:
This thesis focuses on design and implementation of a testing framework for different implementation types of RISC-V architecture. It describes history, instruction set and processor modes which are supported by this architecture. Further, the current methodologies and testing frameworks implemented in Python are discussed. Emphasis is placed on the analysis of compliance tests. In the practical part, the design and implementation of a framework for execution of compliance tests for models, which can be implemented in various ways, either as an ISA simulator or a hardware model, is done. The secondary aim of the thesis is to create a graphical user interface for quick and easy test configuration. Finally, the results are evaluated and the possibilities of further development are discussed.
5
Midéus, Gustav, and Chavez Antonio Morales. "RISC-V Thread Isolation : Using Zephyr RTOS." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-279100.
Full textAbstract:
Many embedded systems lack a memory management unit (MMU) and thus often also lack protection of memory. This causes these systems to be less robust since the operating system (OS), processes, and threads are no longer isolated from each other. This is also a potential security issue and with the number of embedded systems rapidly increasing as a result of the rise of Internet of things (IoT), vulnerabilities like this could become a major problem. However, with a recent update to the RISC-V processor architecture, a possibility to isolate regions of memory without an MMU was introduced. This study aims to identify problems and possibilities of implementing such memory protection with RISC-V. Based on a study of literature and documentation on memory protection and the RISC-V architecture, a prototype was designed and implemented to determine potential problems and evaluate performance in terms of execution time and memory cost. The developed prototype showed aworking implementation of memory protection for the memory regions with RISC-V. The evaluation of the prototype demonstrated an increase in context switch execution time and memory usage. The results indicate that the implemented memory protection comes with an increased cost in performance with a constant factor and a small memory overhead. Therefore, it is recommended that implementations that wish to implement memory protection with RISC-V on smaller embedded systems where time and memory may be crucial takes the overhead in consideration. Further research and testing is needed to identify optimizations that could improve the performance as well as discover security flaws.Många inbyggda system saknar en enhet för minneshantering (s.k. MMU) och saknar därför oftast minnesskydd. Detta leder till att dessa system blir mindre robusta eftersom operativsystemet, processer och trådar inte längre är isolerade från varandra. Detta är också en säkerhetsbrist och med antalet inbyggda system som snabbt ökar på grund av tillväxten av Internet of things (IoT), så kan sårbarheter som denna bli ett stort problem. Med en nyligen introducerad uppdatering av RISC-Vprocessor arkitekturen, så introducerades en möjlighet till att isolera minne utan hjälp av en MMU. Denna studie syftar till att identifiera problem och möjligheter av att implementera sådant minneskydd med RISC-V. Baserat på en studie av litteratur och dokumentation om minnesskydd och RISC-V arkitekturen designades och implementerades en prototyp för att hjälpa till att fastställa problem och möjligheter samt göra en utvärdering med avseende på prestanda- och minneskostnader. Den utvecklade prototypen visade en fungerande implementering av minneskydd för minnesregioner med RISC-V. Utvärderingen av prototypen visade en ökad exekveringstid för kontextbyten och ökad minnesanvändning. Resultaten indikerar att det implementerade minneskyddet kommer med en ökad kostnad i prestanda med en konstant faktor och en liten omkostnad i minne. Därför rekommenderas att implementeringar som vill implementera minneskydd med RISC-V på mindre inbyggda system där tid och minne kan vara avgörande tar hänsyn till omkostnaderna. Ytterligare studier och tester behövs för att identifiera optimeringar som kan förbättra prestandan och upptäcka säkerhetsbrister.
6
Dalbom, Axel, and Tim Svensson. "Implementing the Load Slice Core on a RISC-V based microarchitecture." Thesis, Uppsala universitet, Datorarkitektur och datorkommunikation, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-424385.
Full textAbstract:
As cores have become better at exposing Instruction-Level Parallelism (ILP), they have become bigger, more complex, and consumes more power. These cores are approaching the Power- and Memory-wall quickly. A new microarchitecture proposed by Carlson et. al claims to solve these problems. They claim that the new microarchitecture, the Load Slice Core, is able to outperform both In-Order and Out-of-Order designs in an area and power restricted environment. Based on Carlson et. al.’s work, we have implemented and evaluated a prototype version of their Load Slice Core using the In-Order Core Ariane. We evaluated the Load Slice Core by comparing the LSC to an IOC when running a microbenchmark designed by us, and when running a set of Application Benchmarks. The results from the Microbenchmark are promising, the LSC outperformed the comparable IOC in each test but problems related to the configuration of the design were found. The results from the Application Benchmarks are inconclusive. Due to time constraints, only a partially functioning LSC were compared to a comparable IOC. From these results we found that the LSC performed comparably or slightly worse than its IOC counterpart. More research on the subject is required for any conclusive statement on the microarchitecture can be made, but it is the opinion of this paper’s authors that it does show promise.
7
Bardonek, Petr. "Specifikace scénářů portovatelných stimulů pro moduly procesoru RISC-V." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2018. http://www.nusl.cz/ntk/nusl-385914.
Full textAbstract:
The thesis is focused on the design and implementation of the portable stimulus verification scenarios for selected Berkelium processor modules based on RISC-V architecture from Codasip. The aim of this work is to use new standard for Portable Stimulus developed by Accellera organization to design and implement portable stimulus scenarios using the Questa InFact tool from Mentor. The proposed portable stimulus scenarios are then linked to the already existing verification environments of the UVM methodology and then they are used for verification of the Berkelium processor modules based on RISC-V architecture. The last part of the thesis is the evaluation of portability of the implemented scenarios to the individual levels of the Berkelium processor based on RISC-V architecture (IP blocks, subsystems, system level), in which it tries to use the proposed scenarios across all verificated levels.
8
Javor, Adrián. "Formalní verifikace RISC-V procesoru s využitím Questa PropCheck." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2020. http://www.nusl.cz/ntk/nusl-413219.
Full textAbstract:
The topic of this master thesis is Formal verification of RISC-V processor with Questa PropCheck using SystemVerilog assertions. The theoretical part writes about the RISC-V architecture, furthermore, selected components of Codix Berkelium 5 processor used for formal verification are described, communication protocol AHB-lite, formal verification and its methods and tools are also studied. Experimental part consists of verification planning of selected components, subsequent formal verification, analysing of results and evaluating a benefits of formal technics.
9
Chovančíková, Lucie. "Implementace mikroprocesoru RISC-V s rozšířením pro bitové manipulace." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2020. http://www.nusl.cz/ntk/nusl-413229.
Full textAbstract:
This master thesis deals with the design of a RISC-V processor with bit manipulations instruction set extension. In this work, attention is paid to the description of the RISC-V instruction set and the CodAL language, which is used to describe the instruction sets and the processor architectures. The main goal of this work is to implement a model with a 32-bit address space, RISC-V basic instruction set and bit manipulations instruction set. The processor's design have two models, which one is instruction model and second is RTL model. The resulting parameters of the designed processor are measured using a Genus Synthesis Solution tool. The usability of bit manipulations based on decoder coverage is also included in the measurement.
10
Bjäreholt, Johan. "RISC-V Compiler Performance:A Comparison between GCC and LLVM/clang." Thesis, Blekinge Tekniska Högskola, Institutionen för programvaruteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-14659.
Full textAbstract:
RISC-V is a new open-source instruction set architecture (ISA) that in De-cember 2016 manufactured its rst mass-produced processors. It focuses onboth eciency and performance and diers from other open-source architec-tures by not having a copyleft license permitting vendors to freely design,manufacture and sell RISC-V chips without any fees nor having to sharetheir modications on the reference implementations of the architecture.The goal of this thesis is to evaluate the performance of the GCC andLLVM/clang compilers support for the RISC-V target and their ability tooptimize for the architecture. The performance will be evaluated from ex-ecuting the CoreMark and Dhrystone benchmarks are both popular indus-try standard programs for evaluating performance on embedded processors.They will be run on both the GCC and LLVM/clang compilers on dierentoptimization levels and compared in performance per clock to the ARM archi-tecture which is mature yet rather similar to RISC-V. The compiler supportfor the RISC-V target is still in development and the focus of this thesis willbe the current performance dierences between the GCC and LLVM com-pilers on this architecture. The platform we will execute the benchmarks onwil be the Freedom E310 processor on the SiFive HiFive1 board for RISC-Vand a ARM Cortex-M4 processor by Freescale on the Teensy 3.6 board. TheFreedom E310 is almost identical to the reference Berkeley Rocket RISC-Vdesign and the ARM Coretex-M4 processor has a similar clock speed and isaimed at a similar target audience.The results presented that the -O2 and -O3 optimization levels on GCCfor RISC-V performed very well in comparison to our ARM reference. Onthe lower -O1 optimization level and -O0 which is no optimizations and -Oswhich is -O0 with optimizations for generating a smaller executable code sizeGCC performs much worse than ARM at 46% of the performance at -O1,8.2% at -Os and 9.3% at -O0 on the CoreMark benchmark with similar resultsin Dhrystone except on -O1 where it performed as well as ARM. When turn-ing o optimizations (-O0) GCC for RISC-V was 9.2% of the performanceon ARM in CoreMark and 11% in Dhrystone which was unexpected andneeds further investigation. LLVM/clang on the other hand crashed whentrying to compile our CoreMark benchmark and on Dhrystone the optimiza-tion options made a very minor impact on performance making it 6.0% theperformance of GCC on -O3 and 5.6% of the performance of ARM on -O3, soeven with optimizations it was still slower than GCC without optimizations.In conclusion the performance of RISC-V with the GCC compiler onthe higher optimization levels performs very well considering how young theRISC-V architecture is. It does seems like there could be room for improvement on the lower optimization levels however which in turn could also pos-sibly increase the performance of the higher optimization levels. With theLLVM/clang compiler on the other hand a lot of work needs to be done tomake it competetive in both performance and stability with the GCC com-piler and other architectures. Why the -O0 optimization is so considerablyslower on RISC-V than on ARM was also very unexpected and needs furtherinvestigation.
11
Chatterjee, Aakriti. "Development of an RSA Algorithm using Reduced RISC V instruction Set." University of Cincinnati / OhioLINK, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1617104502129937.
Full text
12
Almeida, Dos Santos Douglas. "Développement d'un processeur durci sur architecture RISC-V pour applications en environnement sévère." Electronic Thesis or Diss., Université de Montpellier (2022-....), 2023. http://www.theses.fr/2023UMONS089.
Full textAbstract:
Cette thèse explore le développement et la caractérisation du processeur HARV et de sa version HARV-SoC, spécifiquement conçus pour fonctionner dans des environnements hostiles. Elle commence par mettre en évidence les défis posés par les environnements hostiles, en particulier l'impact des radiations sur les dispositifs et systèmes électroniques. La thèse classe les environnements hostiles en environnements spatiaux, atmosphériques et artificiels, chacun ayant ses caractéristiques uniques.Dans les environnements de radiations artificielles, différentes installations expérimentales sont décrites, fournissant différents spectres de particules, notamment des neutrons, des protons et des champs mixtes. La thèse se penche sur les effets des radiations sur les dispositifs électroniques, couvrant les effets cumulatifs tels que la dose ionisante totale (TID) et les dommages par déplacement (DD), ainsi que les événements uniques entraînant des erreurs et des défaillances système.La recherche introduit l'architecture d'ensemble d'instructions (ISA) RISC-V en tant qu'architecture de processeur largement adoptée, connue pour son format d'instruction régulier, son décodage d'instructions économique et sa flexibilité modulaire. La thèse souligne l'importance de la fiabilité dans l'utilisation des processeurs dans des environnements hostiles et discute des techniques de détection et de correction d'erreurs, notamment la redondance spatiale, temporelle et informationnelle.Reconnaissant l'utilisation croissante des processeurs RISC-V dans des applications critiques, la thèse propose un résumé des travaux connexes, positionnant HARV-SoC dans le contexte des derniers développements. Elle se penche ensuite sur la mise en œuvre de HARV, la version initiale du processeur, mettant en avant la tolérance aux fautes au niveau de la microarchitecture. La protection des registres à l'aide de codes correcteurs d'erreurs et de la redondance modulaire triple est mise en évidence.Les travaux se poursuivent avec le développement d'un SoC à architecture multi-cycles, permettant des applications plus complexes tout en conservant des périphériques essentiels. Des simulations d'injection de fautes sont réalisées pour analyser de manière exhaustive les modèles de fautes. Pour préparer HARV-SoC aux expériences dans les accélérateurs de particules, des mécanismes d'observabilité sont introduits, permettant une analyse détaillée des erreurs au sein du processeur, en particulier avec les radiations neutroniques.Reconnaissant les limites des compteurs d'erreurs, un gestionnaire d'erreurs est mis en œuvre pour stocker temporairement des informations sur les erreurs détectées. Ces informations sont signalées aux applications via des exceptions, facilitant l'analyse détaillée des erreurs et les réponses. La conception est soigneusement caractérisée et évaluée dans le cadre d'expériences impliquant différents environnements de radiations.L'analyse s'étend aux tests des systèmes d'exploitation et à l'utilisation de techniques de récupération logicielle. En conclusion, la thèse offre une exploration complète des processeurs tolérants aux radiations pour les environnements hostiles, fournissant des informations précieuses et des techniques pour améliorer la fiabilité et les performances du système dans des situations exigeantesThis thesis explores the development and characterization of the HARV processor and its HARV-SoC version, specifically designed for operation in harsh environments. It begins by highlighting the challenges posed by harsh environments, particularly the impact of radiation on electronic devices and systems. The thesis categorizes harsh environments into space, atmospheric, and artificial radiation environments, each with its unique characteristics.In the artificial radiation environments, various experimental facilities are described, which provide different particle spectra, including neutrons, protons, and mixed fields. The thesis delves into the radiation effects on electronic devices, covering cumulative effects like total ionizing dose (TID) and displacement damage (DD), as well as single events leading to errors and system failures.The research introduces the RISC-V Instruction Set Architecture (ISA) as a widely adopted processor architecture known for its regular instruction formatting, cost-effective instruction decoding, and modular flexibility. The thesis emphasizes the importance of reliability in using processors in harsh environments and discusses techniques for error detection and correction, including spatial, temporal, and information redundancy.Acknowledging the increasing use of RISC-V processors in critical applications, the thesis summarizes related work, positioning HARV-SoC in the context of the latest developments. It then delves into the implementation of HARV, the initial version of the processor, emphasizing microarchitecture-level fault tolerance. Register protection using error-correcting codes and triple modular redundancy is highlighted.The work extends to developing an SoC with a multi-cycle architecture, allowing for more complex applications while maintaining essential peripherals. Fault injection simulations are conducted to analyze fault models comprehensively. Observability mechanisms are introduced to prepare HARV-SoC for experiments in particle accelerators, enabling a detailed analysis of errors within the processor, particularly with neutron radiation.Recognizing the limitations of error counters, an error handler is implemented to temporarily store information about detected errors. This information is reported to applications through exceptions, facilitating detailed error analysis and responses. The design is thoroughly characterized and evaluated in experiments involving various radiation environments.The analysis expands to testing operating systems and using software recovery techniques. In conclusion, the thesis comprehensively explores radiation-tolerant processors for harsh environments, providing valuable insights and techniques to enhance system reliability and performance in challenging scenarios
13
Ottavi, Gianmarco. "Sviluppo e Ottimizzazione di un Processore Configurabile con Unità di Calcolo a Precisione Variabile." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2019.
Find full textAbstract:
Negli ultimi anni in applicazioni come il Machine Learning la complessità degli algoritmi è in continua crescita, per migliorarne l’efficienza e velocizzarne l’esecuzione si è iniziato ad usare nuovi formati di precisione, come ad esempio il brain float il quale, presenta lo stesso numero di bit per l’esponente di un floating point a 32 bit ma tronca la mantissa in modo da rientrare in 16 bit. In questa maniera si mantiene lo stesso range dinamico del fp32 riducendo però la precisione in modo accettabile per applicazioni come near-sensor-computing e machine learning. Il vantaggio di utilizzare un formato con ridotto numero di bit si vede in termini di memory-footprint e banda, e nelle performance grazie alla vettorizzazione delle operazioni. Altri formati che possiamo trovare in algoritmi di machine learning sono fixed-point a 4, 2 ed 1 bit che vengono usati in reti neurali quantizzate in modo da permetterne l’implementazione anche in dispositivi come i microcontollori con risorse limitate. Supportare tutti questi formati su processori general-purpose può essere difficoltoso per il rischio di saturare l’encoding space e soluzioni come l’implementazione di istruzioni a lunghezza variabili rischiano di complicare troppo lo stadio di decodifica con conseguente aumento di consumi. In questa tesi si propone la progettazione e ottimizzazione di un core basato su ISA RISC-V in modo da operare a stati: per ogni tipo di istruzione floating point e SIMD fixed point si ha un unica codifica indipendentemente dal formato, dove quest’ultimo (stato) è contenuto in un registro di controllo risolvendo quindi il problema dell’encoding space. Questo ci ha permesso di supportare 15 formati per istruzioni SIMD tra cui 6 a precisioni miste. Queste modifiche hanno reso possibile l’esecuzione di kernel convoluzionali a 4 e 2 bit con performance da 3,78 a 7,78 volte superiori al core originale.
14
Tehrani, Etienne. "Cryptographic primitives adapted to connected car requirements." Electronic Thesis or Diss., Institut polytechnique de Paris, 2022. https://theses.hal.science/tel-03788940.
Full textAbstract:
La communication est une des fonctions clés des véhicules à venir, ce qui impose de la protéger. La cryptographie est une façon évidente d’en assurer la sécurité, spécifiquement, la cryptographie légère qui est mieux adaptée aux contraintes de ressources. Il est également essentiel de prendre en compte la résilience aux attaques par canaux auxiliaires sur des systèmes embarqués. Les objectifs principaux de cette thèse sont d’étudier la possibilité d’implémenter une large variété d’algorithmes de chiffrement légers ainsi que leur protection. Une solution idéale est d’utiliser une implémentation agile, capable d’exécuter différents algorithmes, tout en utilisant un minimum de ressources et en garantissant la sécurité contre les attaques par canaux auxiliaires. Notre principale solution est une extension du jeu d’instruction du RISC-V permettant l’exécution de multiples algorithmes tout en satisfaisant les contraintes d’agilité. Nous avons étudié de nombreux algorithmes de chiffrement et avons proposé plusieurs approches. La première est totalement matériel et la seconde et basée sur un processeur dédié afin d’implémenter ces algorithmes de chiffrement légers ainsi que leur protection dans un environnement avec de fortes contraintes de ressourcesCommunications are one of the key functions in future vehicles and require protection. Cryptography is an obvious answer to secure communications, specifically we studied lightweight cryptography to fit the constrained resources of the environment. A second emerging problem, specific to embedded systems, is resilience to side-channel attacks.The main objectives of the thesis are to study the feasibility of implementing a wide variety of symmetric lightweight encryption algorithms and their protection. An optimal solution is to have an agile implementation, able to quickly execute different lightweight encryption algorithms, using few resources and guaranteeing protection against physical attacks. Our main architecture starts from a modification of the instruction set of a RISC-V processor to satisfy the agility property of lightweight cryptography algorithms. We have studied many encryption algorithms and have proposed a first approach with a fully hardware architecture and a second approach with a dedicated processor in order to efficiently implement Lightweight Cryptography and their protection in a constrained embedded system
15
Louetsi, Kenelm. "Un environnement de développement d'applications sur un processeur à beaucoup de cœurs parallélisant." Electronic Thesis or Diss., Perpignan, 2024. http://www.theses.fr/2024PERP0024.
Full textAbstract:
Les objets numériques du futur (robots domestiques, véhicules autonomes, engins spatiaux automatiques,...) auront besoin à la fois de puissance de calcul et de sûreté. Le Little Big Processor (LBP) est adapté à ce défi : il a une approche novatriced u parallélisme qui offre l'avantage de la puissance en garantissant un certain déterminisme de l'exécution. Ce déterminisme d'exécution donne une sûreté de fonctionnement indispensable dans la plupart des dispositifs interagissant avec le monde et l'humain. Dans cette thèse, nous avons réalisé un environnement de développement pour LBP, avec un compilateur, un « bootloader » et un débogueur. Ces outils sont classiques, mais en l'occurrence, ils devront être adaptés à la mise en oeuvre d'applications parallélisées avec OpenMP pour LBP. Suite à la réalisation de l'environnement de développement, nous avons défini un modèle de parallélisme déterministe pour de l'embarqué « bareme-tal ». Ce modèle a été évalué sur une plateforme embarquée « baremetal » et nous a permis de confirmer qu'il était possible d'avoir une exécution parallèle déterministe qui conserve les gains en performance du parallélismeDigital objects of the future (domestic robots, autonomous vehicles, automatic spacecraft, ...) will need both computing power and safety. The Little Big Processor (LBP) is suitable for this challenge: it has an innovative approach to parallelism which offers the advantages of computing power while guaranteeing a certain determinism of execution. This execution determinism brings a level of operational safety essential in most devices interacting with the world and humans. In the present thesis we created a development environment for LBP, with a compiler, a loader and a debugger. These tools are classic but in this case, they will have to be adapted to the implementation of parallelized OpenMP applications for LBP. Following the creation of the development environment, we defined a deterministic parallel model for embedded bare-metal. This model has been evaluated on a embedded bare-metal platform, and this allowed us to confirm that it is possible to have a deterministic parallel execution which keeps the performance speedups from parallelism
16
Chai, Ke. "XBT: FPGA Accelerated Binary Translation." Case Western Reserve University School of Graduate Studies / OhioLINK, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=case1626692665154349.
Full text
17
Fuchs, Franz Anton. "Analysis of Transient-Execution Attacks on the out-of-order CHERI-RISC-V Microprocessor Toooba." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-291743.
Full textAbstract:
Transient-execution attacks have been deemed a large threat for microarchitectures through research in recent years. In this work, I reproduce and develop transient-execution attacks against RISC-V and CHERI-RISC-V microarchitectures. CHERI is an instruction set architecture (ISA) security extension that provides fine-grained memory protection and compartmentalisation. I conduct transient-execution experiments for this work on Toooba – a superscalar out-of-order processor implementing CHERI-RISC-V. I present a new subclass of transient-execution attacks dubbed Meltdown-CF(Capability Forgery). Furthermore, I reproduced all four major Spectre-style attacks and important Meltdown-style attacks. This work analyses all attacks and explains the outcome of the respective experiments based on architectural and microarchitectural decisions made by their developers. While all four Spectre-style attacks could be successfully reproduced, the cores do not appear to be vulnerable to prior Meltdown-style attacks. I find that Spectre-BTB and Spectre-RSB pose a large threat to CHERI systems as well as the newly developed transientexecution attack subclass Meltdown-CF. However, all four major Spectre-style attacks and all attacks of the Meltdown-CF subclass violate CHERI’s security model and therefore require security mechanisms to be put in place.Transient-execution-attacker har utgjort ett stort hot för mikroarkitekturer i senaste årens forskning. I den här avhandlingen återskapar jag och utvecklar transient-execution-attacker mot RISC-V och CHERI-RISC-V mikroarkitekturer. CHERI är en instruction set architecture (ISA) security extension som ger finkornig memory protection och compartmentalisation. I avhandlingen genomför jag transient-execution-experiment på Toooba – en superscalar outof-order processor som implementerar CHERI-RISC-V. Jag presenterar en ny sorts transient-execution-attack som kallas Meltdown-CF(Capability Forgery). Därutöver har jag återskapat de fyra stora Spectre-style-attackerna och viktiga Meltdown-style-attacker. I avhandlingen analyserar jag dessa attacker och förklarar resultaten från experimenten utifrån de arkitektoniska och mikroarkitektoniska besluten tagna av respektive utvecklare. Medan de fyra Spectre-style-attackerna kunde återskapas med framgång verkar inte processorkärnorna vara sårbara för tidigare Meltdown-style-attacker. Jag kom fram till att Spectre-BTB och Spectre-RSB såväl som den nya sortens transientexecution-attack Meltdown-CF utgör ett stort hot för CHERI-system. Däremot bryter de fyra stora Spectre-style-attackerna och alla attacker av MeltdownCF-typen mot CHERI:s threat-model och kräver därmed säkerhetsmekanismer för att verkställas.
18
Saussereau, Jonathan. "AsteRISC : architectures de processeur RISC-V flexibles et outils pour l’exploration de l’espace de conception." Electronic Thesis or Diss., Bordeaux, 2024. http://www.theses.fr/2024BORD0002.
Full textAbstract:
Dans l'industrie électronique, les concepteurs sont souvent confrontés au défi de l'évolution des exigences tout au long du cycle de développement et après le déploiement des produits. Ce défi est amplifié par la longue période de temps entre la conception de l'ASIC et la fabrication, ainsi que par l'inflexibilité intrinsèque des architectures numériques une fois gravées sur le silicium. Par conséquent, les approches permettant la modification après fabrication sont des solutions attrayantes.Cependant, une telle flexibilité entraîne généralement des coûts supplémentaires en termes d'utilisation des ressources, de performance et de consommation d'énergie. Pour y faire face, les concepteurs doivent trouver un équilibre optimal entre ces facteurs, en créant une architecture qui minimise ces surcoûts tout en répondant aux exigences du cahier des charges.Ce travail explore une solution basée sur un processeur comme alternative à la solution fixe. Le design proposé est un processeur RISC-V flexible : AsteRISC. L'originalité de ce cœur réside dans le fait qu'il possède des registres optionnels à des points clés de son chemin de données, permettant au concepteur de contrôler directement le chemin critique, afin de trouver celui optimal pour l'application visée. La configuration de registre choisie est sélectionnée par des paramètres avant la synthèse logique. Deux approches architecturales sont explorées : une approche non pipeline, visant à assurer une utilisation limitée des ressources et offrant une grande variété de microarchitectures différentes, et une approche pipeline flexible pour étendre l'espace de conception aux architectures à plus hautes performances.Un environnement flexible de conception de System-On-Chip (SoC) est proposé, présentant une approche indépendante de la cible technologique. Un environnement d'exploration architecturale est également présenté, permettant la recherche en parallèle de la fréquence maximale de fonctionnement pour de nombreuses micro-architectures différentes et facilitant l'interprétation des résultats.Les résultats expérimentaux et leur analyse fournissent des benchmarks, des résultats de performance, autant avec des circuits FPGA que pour les technologies ASIC. Les résultats mettent en évidence les avantages de la flexibilité architecturale pour répondre à des exigences strictes. En effet, ils démontrent que chaque configuration présente des caractéristiques distinctes en fonction de la technologie ciblée et du contexte de l'application, ce qui permet de trouver la plus adaptée au cadre applicatif.L'étude est ancrée dans le développement d'un SoC pour une fonction de pointage radar, intégrant le processeur proposé pour relever le défi du traitement des données dans des contraintes de temps serrées, tout en conservant une faible utilisation des ressources. Les résultats de mise en œuvre, jusqu'au layout, démontrent qu'il est possible d'offrir les mêmes fonctionnalités que l'architecture fixe originale tout en permettant une modification dynamique de son comportement après fabrication, en changeant le logiciel. Les impacts, notamment en termes de surface utilisée, sont présentés, permettant une compréhension des compromis sous-jacentsIn the electronic industry, designers are often faced with the challenge of evolving requirements throughout the development lifecycle and post-deployment of products. This challenge is compounded by the lengthy timespan from ASIC design to manufacturing and the inherent inflexibility of digital architectures once etched onto silicon. Thus, approaches allowing modification after manufacturing are attractive solutions.However, such flexibility typically incurs additional costs in resource utilization, performance overhead, and power consumption. To address this, designers must strike an optimal balance among these competing factors, crafting an architecture that minimizes extra costs while meeting the specific demands of the specifications.The research explores a processor-based solution as a viable alternative to the fixed one. The proposed design is a flexible RISC-V processor: AsteRISC. The originality of this core is to have optional registers at key points of its datapath, allowing the designer to have direct control over the critical path, in order to find the optimal one for the application. The chosen register configuration is selected through parameters before logic synthesis. Two architectural approaches are being explored: a non-pipelined approach, aimed at ensuring limited resource usage and offering a wide variety of different microarchitectures, and a flexible pipelined approach to extend the design space to architectures with higher performance capabilities.A flexible System-On-Chip (SoC) framework is proposed, featuring, a multi-target approach. An architecture exploration environment is also presented, enabling the parallel search for maximum operating frequency for many micro-architectures and facilitating result interpretation.Experimental results and analyses provide benchmarks, performance results on both FPGA devices and ASIC technologies. Results showcase the advantages of architectural flexibility to meet stringent performance demands. Indeed, they clearly demonstrate that each configuration exhibits distinct characteristics based on the targeted technology and the application context.The study is anchored in the development of a SoC for a radar aiming function, utilizing the proposed processor to address the challenge of processing data within tight timing constraints, while keeping a low hardware footprint. Implementation results, down the layout, demonstrate that it is possible to offer the same functionalities as the original fixed architecture while allowing dynamic modification of its behavior by changing the software. The impacts, especially in terms of used surface area, are presented, allowing for a nuanced understanding of the underlying trade-offs
19
Musasa, Mutombo Mike. "Evaluation of embedded processors for next generation asic : Evaluation of open source Risc-V processors and tools ability to perform packet processing operations compared to Arm Cortex M7 processors." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-299656.
Full textAbstract:
Nowadays, network processors are an integral part of information technology. With the deployment of 5G network ramping up around the world, numerous new devices are going to take advantage of their processing power and programming flexibility. Contemporary information technology providers of today such as Ericsson, spend a great amount of financial resources on licensing deals to use processors with proprietary instruction set architecture designs from companies like Arm holdings. There is a new non-proprietary instruction set architecture technology being developed known as Risc-V. There are many open source processors based on Risc-V architecture, but it is still unclear how well an open-source Risc-V processor performs network packet processing tasks compared to an Arm-based processor. The main purpose of this thesis is to design a test model simulating and evaluating how well an open-source Risc-V processor performs packet processing compared to an Arm Cortex M7 processor. This was done by designing a C code simulating some key packet processing functions processing 50 randomly generated 72 bytes data packets. The following functions were tested: framing, parsing, pattern matching, and classification. The code was ported and executed in both an Arm Cortex M7 processor and an emulated open source Risc-V processor. A working packet processing test code was built, evaluated on an Arm Cortex M7 processor. Three different open-source Risc-V processors were tested, Arianne, SweRV core, and Rocket-chip. The execution time of both cases was analyzed and compared. The execution time of the test code on Arm was 67, 5 ns. Based on the results, it can be argued that open source Risc-V processor tools are not fully reliable yet and ready to be used for packet processing applications. Further evaluation should be performed on this topic, with a more in-depth look at the SweRV core processor, at physical open-source Risc-V hardware instead of emulators.Nätverksprocessorer är en viktig byggsten av informationsteknik idag. I takt med att 5G nätverk byggs ut runt om i världen, många fler enheter kommer att kunna ta del av deras kraftfulla prestanda och programerings flexibilitet. Informationsteknik företag som Ericsson, spenderarmycket ekonomiska resurser på licenser för att kunna använda proprietära instruktionsuppsättnings arkitektur teknik baserade processorer från ARM holdings. Det är väldigt kostam att fortsätta köpa licenser då dessa arkitekturer är en byggsten till designen av många processorer och andra komponenter. Idag finns det en lovande ny processor instruktionsuppsättnings arkitektur teknik som inte är licensierad så kallad Risc-V. Tack vare Risc-V har många propietära och öppen källkod processor utvecklats idag. Det finns dock väldigt lite information kring hur bra de presterar i nätverksapplikationer är känt idag. Kan en öppen-källkod Risc-V processor utföra nätverks databehandling funktioner lika bra som en proprietär Arm Cortex M7 processor? Huvudsyftet med detta arbete är att bygga en test model som undersöker hur väl en öppen-källkod Risc-V baserad processor utför databehandlings operationer av nätverk datapacket jämfört med en Arm Cortex M7 processor. Detta har utförts genom att ta fram en C programmeringskod som simulerar en mottagning och behandling av 72 bytes datapaket. De följande funktionerna testades, inramning, parsning, mönster matchning och klassificering. Koden kompilerades och testades i både en Arm Cortex M7 processor och 3 olika emulerade öppen källkod Risc-V processorer, Arianne, SweRV core och Rocket-chip. Efter att ha testat några öppen källkod Risc-V processorer och använt test koden i en ArmCortex M7 processor, kan det hävdas att öppen-källkod Risc-V processor verktygen inte är tillräckligt pålitliga än. Denna rapport tyder på att öppen-källkod Risc-V emulatorer och verktygen behöver utvecklas mer för att användas i nätverks applikationer. Det finns ett behov av ytterligare undersökning inom detta ämne i framtiden. Exempelvis, en djupare undersökning av SweRV core processor, eller en öppen-källkod Risc-V byggd hårdvara krävs.
20
Leplus, Gaëtan. "Processeur résistant et résilient aux attaques de fautes et aux attaques par canaux auxiliaires." Electronic Thesis or Diss., Saint-Etienne, 2023. http://www.theses.fr/2023STET0059.
Full textAbstract:
Dans le paysage technologique actuel, l'internet des objets (IoT) a émergé comme un élément omniprésent, engendrant néanmoins des défis majeurs en matière de sécurité. Les attaques par injection de fautes et par canaux auxiliaires sont particulièrement préoccupantes. Les processeurs, étant les pierres angulaires des systèmes informatiques, sont cruciaux pour la sécurisation de l'IoT.Cette thèse se focalise sur la sécurisation du pipeline des processeurs pour contrer ces menaces. L'importance de cette recherche est mise en évidence par la nécessité d'élaborer des mécanismes de sécurité robustes au niveau du processeur, le noyau de tout calcul et contrôle. Plusieurs contre-mesures sont proposées.Pour sécuriser le chemin de données, une méthode de tag d'intégrité est proposée. Compatible avec les techniques de masquage traditionnelles, cette méthode vise à garantir l'intégrité des données tout au long du pipeline du processus, et ce, avec un surcoût réduit.Pour le chemin d'instructions, un mécanisme de masquage de l'instruction en cours est proposé, où un masque est généré en fonction de l'instruction précédente. Cette technique innovante permet une sécurisation efficace des instructions avec un surcoût très faible.Quant au procédé de désynchronisation, il introduit une méthode robuste permettant d'insérer des instructions factices de manière plus efficace que les techniques actuelles.Ces contre-mesures, en ciblant les composantes clés du processeur, contribuent à une amélioration notable de la sécurité des systèmes IoT. Elles s'attaquent aux racines des vulnérabilités, offrant ainsi un niveau de protection renforcé contre une gamme variée d'attaquesIn today's technological landscape, the Internet of Things (IoT) has emerged as a ubiquitous element, yet it brings major security challenges. Fault injection and side-channel attacks are of particular concern, targeting systemic weaknesses and compromising data integrity and confidentiality. Processors, as the cornerstones of computing systems, are crucial in securing the IoT.This thesis focuses on securing the processor pipeline to counter these threats. The significance of this research is highlighted by the need to develop robust security mechanisms at the processor level, the core of all computation and control. Several countermeasures are proposed to enhance the resilience of different parts of the processor against attacks.To secure the data path, an integrity tagging method is proposed. Compatible with traditional masking techniques, this method aims to ensure data integrity throughout the processing pipeline, with minimal overhead.For the instruction path, a mechanism for masking the current instruction is proposed, where a mask is generated based on the previous instruction. This innovative technique enables effective instruction security with very low overhead.Regarding the desynchronization process, it introduces a robust method for inserting dummy instructions more efficiently than current techniques.These countermeasures, by targeting key components of the processor, contribute to a notable improvement in the security of IoT systems. They address the roots of vulnerabilities, thus providing enhanced protection against a wide range of attacks
21
Ducousso, Rieul. "Sécurisation des accès aux périphériques et depuis les périphériques dans une architecture multicœur RISC-V utilisée pour la virtualisation." Electronic Thesis or Diss., Sorbonne université, 2023. http://www.theses.fr/2023SORUS040.
Full textAbstract:
La sécurité informatique est un enjeu majeur dans des domaines variés tels que la santé, les transports, l'industrie ou encore la défense. Ces systèmes intègrent de plus en plus de composants développés par des sous traitants ne pouvant être considérés comme de confiance pour la garantie de la sécurité du système. Les attaques par canaux cachés contournent les mécanismes classiques d'isolation mis en place dans les systèmes et permettent l'échange de données entre deux processus ou machines virtuelles isolés. Différentes attaques et contremesures existent principalement dans les processeurs. Nous proposons une attaque par canal caché exploitant les variations temporelles dues au parcours de la hiérarchie mémoire. Elle brise l'isolation entre les périphériques d'un système virtualisé ouvrant un canal de communication entre deux périphériques malicieux. Nous montrons par l'adaptation, aux spécificités des périphériques, des principes exploités par les canaux cachés sur les processeurs qu'il est possible d'échanger des données entre deux périphériques isolés par une IOMMU. Dans un second temps nous modifions la microarchitecture de l'IOMMU pour réduire l'impact de ce type d'attaques. La stratégie mise en place est de décorréler les opérations effectuées par les périphériques et l'état interne de ses composants. Nous montrons, en simulation et sur un système intégrant un processeur exécutant Linux implémenté sur une carte FPGA, les effets de cette contremesure sur l’isolation et sur les performances. Le débit du canal caché est réduit sans toutefois l'interdire totalement. L'impact sur les performances des accès mémoires des périphériques est limitéToday, computer security is a major topic in various fields such as healthcare, transport, industry or defense. Systems integrated an ever increasing number of components developed by untrusted sources. Covert channel attacks subvert system mechanism to create a communication channel between entities that otherwise shouldn't be able to communicate thus breaching data confidentiality. These attacks circumvent classical isolation mechanisms by allowing processes or virtual machines to exchange and exfiltrate data. Most attacks target the processor and its neighbouring components. We propose a new side-channel attack exploiting the temporal variations due to the memory hierarchy to implement a communication channel. This attack breaks the isolation between peripherals of a virtualized system opening a communication channel between two malicious devices. This attack relies on the adaptation of principles exploited by covert channels on processors with specificities of peripherals. We show that it is possible to exchange data between two devices isolated by an IOMMU. Secondly, we modify the microarchitecture of the IOMMU to reduce the impact of such attacks. The defense strategy is to decorrelate the operations performed by the peripherals and the internal state of its components. We show in simulation and on a system incorporating a processor running Linux implemented on a board FPGA the effects of this countermeasure on the isolation as well as on the device performance. This countermeasure reduces the throughput covert channel without however negating it fully. The impact on performance of peripheral memory accesses is limited
22
MELO, Cecil Accetti Resende de Ataíde. "Projeto de uma arquitetura baseada num processador RISC-V para desenvolvimento de aplicações em software-defined radio." Universidade Federal de Pernambuco, 2016. https://repositorio.ufpe.br/handle/123456789/26036.
Full textAbstract:
Submitted by Pedro Barros (pedro.silvabarros@ufpe.br) on 2018-08-22T19:41:45Z
No. of bitstreams: 2
license_rdf: 811 bytes, checksum: e39d27027a6cc9cb039ad269a5db8e34 (MD5)
DISSERTAÇÃO Cecil Accetti Resende de Ataíde Melo.pdf: 2769633 bytes, checksum: f491d3b88b08cb65e70c14b653034fdf (MD5)Approved for entry into archive by Alice Araujo (alice.caraujo@ufpe.br) on 2018-08-29T21:40:28Z (GMT) No. of bitstreams: 2 license_rdf: 811 bytes, checksum: e39d27027a6cc9cb039ad269a5db8e34 (MD5) DISSERTAÇÃO Cecil Accetti Resende de Ataíde Melo.pdf: 2769633 bytes, checksum: f491d3b88b08cb65e70c14b653034fdf (MD5)
Made available in DSpace on 2018-08-29T21:40:28Z (GMT). No. of bitstreams: 2 license_rdf: 811 bytes, checksum: e39d27027a6cc9cb039ad269a5db8e34 (MD5) DISSERTAÇÃO Cecil Accetti Resende de Ataíde Melo.pdf: 2769633 bytes, checksum: f491d3b88b08cb65e70c14b653034fdf (MD5) Previous issue date: 2016-08-26
CNPq
Os sistemas de software-defined radio práticos normalmente se dividem em duas classes: arquiteturas reconfiguráveis em FPGA que implementam os algoritmos de processamento de digital de sinais, com granularidade alta e, as arquiteturas baseadas em processador. Um dos problemas no projeto de arquiteturas de processamento digital de sinais baseadas em processador é o do suporte a compiladores e linguagens de alto nível. Arquiteturas muito especializadas, com conjuntos de instruções extensos e muitos modos de endereçamento, dificultam a implementação de compiladores para linguagens de alto nível. Neste trabalho buscou-se explorar a viabilidade de um conjunto de instruções emergente, RISC-V, e uma extensão do seu conjunto de instruções para a aplicação em processamento digital de sinais de banda base, sobretudo nas funcionalidades de modem, em aplicações de software-defined radio. A análise das operações de um modem, para as modulações digitais mais utilizadas, revela que as operações feitas para modulação/ demodulação envolvem números complexos. No entanto, aritmética de complexos não é normalmente suportada pelo hardware em arquiteturas tradicionais. Além da arquitetura proposta para o processador, com suporte a novas instruções especializadas, os periféricos necessários para o front-end de rádio frequência e o software de suporte foram implementados, resultando num SoC para software defined radio.
Practical software-defined radio systems are usually classified in two main architecture classes: Reconfigurable architectures on FPGAs, that implement coarse grained digital signal processing algorithms, or processor-based architectures. One of the issues in the design of processor-based digital signal processing architectures is compiler and high-level languages support. Highly specialized architectures, with extensive instruction sets (ISA) and addressing modes turn high-level languages compiler design a complex task. In this work we explore the viability to extend the emerging RISC-V instruction set for baseband processing applications for software-defined radio, especially for modem applications. The analysis of modem functions, for the most used digital modulation schemes, reveals that the modulation/demodulation tasks involve complex number operations. Complex number arithmetic, however, is not supported on traditional architectures. The proposed platform includes a 3-stage pipelined processor with new specialized instructions, as well as the peripherals needed to the radio-frequency front-end and supporting software, resulting on a system-on-a-chip for software-defined radio applications. software-defined radio.
23
Dechelotte, Jonathan. "Etude et mise en oeuvre d'un environnement d'exécution pour architecture hétérogène reconfigurable." Thesis, Bordeaux, 2020. http://www.theses.fr/2020BORD0025.
Full textAbstract:
Aujourd'hui, les systèmes embarqués ont pris une part hégémonique dans notre monde. Leurs utilisation est prépondérante, que ce soit pour communiquer, se déplacer, travailler ou se divertir. Des efforts dans le domaine de la recherche et de l'industrie n'ont de cesse de faire évoluer les parties qui composent ces systèmes dont le processeur, le FPGA, la mémoire et le système d'exploitation.D'un point de vue architectural, l'apport d'une architecture généraliste couplée à une architecture reconfigurable positionne le SoC FPGA comme une cible préférentielle pour une utilisation dans les systèmes embarqués. Leurs adoption est cependant difficile du fait de leur complexité d'implémentation. L'abstraction des couches de bas niveau semble un axe d'investigation qui tend à inverser cette tendance. Au premier abord, l'utilisation d'un système d'exploitation paraît idoine. En effet, il possède l'écosystème de drivers et services disponibles pour l'accès aux ressources matérielles, la capacité d'ordonnancement natif ainsi que des bibliothèques pour la sécurité. Toutefois, cette solution engendre des contraintes qui poussent à évaluer d'autres approches. Ce manuscrit évalue la capacité d'un langage de haut niveau tel que Lua à fournir un environnement d'exécution dans le cas d'une implémentation sans système d'exploitation.À travers un écosystème nommé Lynq, cet environnement d'exécution procure les briques nécessaires à la gestion et l'allocation des ressources présentes sur le SoC FPGA, ainsi qu'une méthode proposant une isolation entre applicatifs.La capacité des architectures généralistes que sont les CPUs à devenir spécialisés lorsqu'ils sont implémentés sur un FPGA a été exploré par la suite. Ceci au travers d'une contribution permettant la génération d'un CPU RISC-V ainsi que son microcode associéToday, embedded systems have taken a leading role in our world. Whether for communication, travel, work or entertainment, their use is preponderant. Together, research and industry efforts are constantly developing various parts that make up these systems: processor, FPGA, memory, operating system.From an architectural point of view, the contribution of a generalist architecture coupled with a reconfigurable architecture positions SoC FPGA as popular targets for use in embedded systems. However, their implementation's complexity makes their adoption difficult. The abstraction of low-level layers seems to be an investigation's axis that would tend to reverse this trend. The use of an operating system seems suitable at first glance because they deliver an ecosystem of drivers and services for access to hardware resources, native scheduling capacities and libraries for security. However, this solution brings constraints and lead to evaluate other approaches.This manuscript evaluates the ability of a high-level language, Lua, to provide an execution environment in such a case that the implementation does not provide operating system. It gives, through an ecosystem named Lynq, the necessary building blocks for the management and allocation of resources present on the SoC FPGA as well as a method for isolation between applications. Besides the adoption of this execution environment, our work explores the capacity of generalist architectures such as CPUs to become specialized when implemented on a FPGA. This is done through a contribution allowing the generation of a RISC-V CPU and its associated microcode
24
Ducasse, Quentin. "Sécurisation matérielle de la compilation à la volée des machines virtuelles langage." Electronic Thesis or Diss., Brest, École nationale supérieure de techniques avancées Bretagne, 2024. http://www.theses.fr/2024ENTA0003.
Full textAbstract:
Les machines virtuelles langage (VM) sont l’environnement d’exécution des langages de haut niveau les plus répandus. Elles permettent une portabilité du code applicatif et la gestion automatique de la mémoire. Leur large diffusion couplée à l’exécution de tâches de bas niveau les rendent intéressantes pour les attaquants. Les solutions purement logicielles entraînent souvent une perte de performance incompatible avec la compilation just-in-time (JIT). Des solutions accélérées matériellement sont ajoutées dans des processeurs commerciaux pour concilier des garanties de sécurité fortes avec la performance. Pour comparer ces solutions, cette thèse s’intéresse au jeu d’instructions RISC-V et à ses capacités d’extension. Nous présentons Gigue, un générateur de binaires similaires au code JIT directement exécutables sur les softcores RISC-V. Il fournit une interface pour des instructions personnalisées et garantit leur exécution. Nous présentons une solution d’isolation de domaine au niveau des instructions ajoutée aux binaires de Gigue et déployée dans un processeur avec des modifications minimales. La solution ajoute un surcoût de performance négligeable tout en garantissant des propriétés fortes sur les domaines. Afin de motiver le déploiement dans des cas d’utilisation réels, nous étendons le compilateur JIT Pharo au jeu d’instructions RISC-V, ainsi que son infrastructure de testLanguage Virtual Machines (VMs) are the run-time environment of popular high level managed languages. They offer portability and memory handling for the developer and are deployed on most computing devices. Their widespread distribution, handling of untrusted user inputs, and low-level task execution make them interesting to attackers. Software-only solutions that isolate their different components often incur a high performance overhead incompatible with just-in-time (JIT) compilation. Hardware-accelerated run time protections are pushed in vendor processors as a solution to conciliate strong security guarantees with performance. To allow experimentation in the design and comparison of such solutions, this thesis is interested in the RISC-V instruction set and its extension capabilities. We present Gigue, a workload generator that outputs binaries similar to JIT code directly executable on RISC-V softcores. It provides an interface for custom instructions and guarantees their execution. We present an instruction-level domain isolation solution added to Gigue binaries and implemented in an application-class processor with processor modifications. The solution adds negligible performance overhead while enforcing strong properties on domains. As an effort to motivate deployment in real use cases, we extend the Pharo JIT compiler to the RISC-V instruction set along with its testing infrastructure
25
Fang, Gloria(Gloria Yu Liang). "Instruction-level power consumption simulator for modeling simple timing and power side channels in a 32-bit RISC-V micro-processor." Thesis, Massachusetts Institute of Technology, 2021. https://hdl.handle.net/1721.1/130686.
Full textAbstract:
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, February, 2021Cataloged from the official PDF of thesis.
Includes bibliographical references (pages 139-140).
We create a Python based RISC-V simulator that is capable of simulating any assembly code written in RISC-V, and even perform simple power analysis of RISC-V designs. The power consumption of non-privileged RISC-V RV32IM instructions are measured experimentally, forming the basis for our simulator. These instructions include memory loads and stores, PC jumps and branches, as well as arithmetic instructions with register values. The object-oriented simulator also supports stepping and debugging. In the context of designing software for hardware use, the simulator helps assess vulnerability to side channel attacks by accepting input power consumption values. The power consumption graph of any disassembled RISC-V code can be obtained if the power consumption of each instruction is given as an input; then, from the output power consumption waveforms, we can assess how vulnerable a system is to side channel attacks. Because the power values can be customized based on what's experimentally measured, this means that our simulator can be applied to any disassembled code and to any system as long as the input power consumption of each instruction is supplied. Finally, we demonstrate an example application of the simulator on a pseudorandom function for simple side channel power analysis.
by Gloria (Yu Liang) Fang.
M. Eng.
M.Eng. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science
26
Cong, Minh Thanh. "Hardware accelerated simulation and automatic design of heterogeneous architecture." Electronic Thesis or Diss., Université de Rennes (2023-....), 2023. https://ged.univ-rennes1.fr/nuxeo/site/esupversions/1ae038b9-380e-4e42-bcd4-fa3a28cb34b0.
Full textAbstract:
La conception de plates-formes de système sur puce hétérogènes est complexe avec de nombreuses combinaisons possibles. La simulation détaillée de différentes solutions est nécessaire pour déterminer le meilleur design. Les environnements de simulation existants (tels que gem5) sont limités car purement logiciels et ne prennent pas en compte les architectures hétérogènes. Pour pallier ces limitations, l'utilisation de composants reprogrammables FPGA pour accélérer la simulation est motivée. Notre travail est divisé en deux parties. La première partie est d'ordre expérimental et a étudié une approche de conception d'architectures hétérogènes en se concentrant sur la simulation de modèles de performance de composants de l'architecture (accélérateurs matériels et cœurs de processeurs) sur FPGA. La seconde partie est méthodologique et concerne un flot pour déterminer la meilleure microarchitecture en termes de rapport performance/consommation d'énergie. Ce flot combine un simulateur logiciel d'architecture et une méthode d'optimisation d'hyperparamètres pour trouver la meilleure combinaison de parallélisme, stratégies de déroulage de boucles et interfaces de mémoire. Les expérimentations ont été menées sur différents problèmes pour déterminer les solutions les plus optimales en termes d'efficacité énergétiqueThe design of heterogeneous system-on-chip platforms is complex with many possible combinations. Detailed simulation of different solutions is necessary to determine the best design. Existing simulation environments (such as gem5) are limited as they are purely software based and do not take into account heterogeneous architectures. To address these limitations, the use of reprogrammable FPGA components to accelerate simulation is motivated. Our work is divided into two parts. The first part is experimental and studied an approach to design heterogeneous architectures focusing on simulating performance models of architecture components (hardware accelerators and processor cores) on FPGA. The second part is methodological and concerns a flow to determine the best microarchitecture in terms of performance to energy consumption ratio. This flow combines a software architecture simulator and a hyperparameter optimization method to find the best combination of parallelism, loop unrolling strategies, and memory interfaces. Experiments were conducted on different problems to determine the most optimal solutions in terms of energy efficiency
27
Chechi, Dario. "Framework per il benchmarking comparativo dei componenti software su piattaforme embedded multi-core." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2021. http://amslaurea.unibo.it/23752/.
Full textAbstract:
In questo elaborato vengono mostrati i concetti alla base della piattaforma PULP e il processo di sviluppo di un framework open-source che permette di eseguire benchmark comparativi fra diversi programmi sviluppati per la piattaforma stessa.
L'obiettivo del tool sviluppato è quello di fornire agli sviluppatori un metodo rapido ed efficace per confrontare le varie configurazioni possibili dei programmi e permettere loro di vedere facilmente quali siano le impostazioni migliori da utilizzare per raggiungere l'obiettivo desiderato.
28
James, Benjamin. "Compiler-Assisted Software Fault Tolerance for Bare Metal and RTOS Applications on Embedded Platforms." BYU ScholarsArchive, 2021. https://scholarsarchive.byu.edu/etd/8958.
Full textAbstract:
In the presence of ionizing particles and other high-energy atomic sources, many electronic and computer systems fail. Single event upsets (SEUs) can be mitigated through hardware and/or software methods. Previous research at BYU has introduced COAST, a compiler-based tool that can automatically add software protection schemes to improve fault coverage of programs. This thesis will expand on the work already done with the COAST project by proving its effectiveness across multiple platforms and benchmarks. The ability to automatically add fault protection to arbitrary user programs will be very valuable for many application designers. The results presented herein show that mean work to failure (MWTF) of an application can increase from 1.2x – 36x when protected by COAST. In addition to the results based on bare metal applications, in this thesis we will show that it is both possible and profitable to protect a real-time operating system with COAST. We present experimental results which show that our protection scheme gives a 2x – 100x improvement in MWTF. We also present a fault injection framework that allows for rapid and reliable testing of multiple protection schemes across different benchmarks. The code setup used in this paper is publicly available. We make it public in the hope that it will be useful for others doing similar research to have a concrete starting point.
29
Vávra, Jan. "Grafický simulátor superskalárních procesorů." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2021. http://www.nusl.cz/ntk/nusl-445476.
Full textAbstract:
Práce se zabývá implementací simulátoru superskalárního procesoru. Implementace se odvíjí od existujících simulátorů a jejich chybějících částí. Simulátor umí vykonávat instrukční sadu RISC-V, ovšem je umožněno přidání jakékoli RISC instrukční sady. Simulátor má deterministickou predikci skoku. Části procesoru lze upravovat. Součástí je i editor kódu pro danou instrukční sadu.
30
Cydlíková, Jana. "Implementace risk managementu v podniku." Master's thesis, Vysoká škola ekonomická v Praze, 2007. http://www.nusl.cz/ntk/nusl-7691.
Full textAbstract:
Definition of enterprise risk management (ERM), key point of implementation, application techniques in key areas. Use some concrete application techniques in real organization - Huhtamaki Česká republika, a.s.
31
Sláma, Pavel. "Paralelismus na úrovni instrukcí v moderních procesorech." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2020. http://www.nusl.cz/ntk/nusl-413231.
Full textAbstract:
Basic methodology that exploits instruction level parallelism is called pipelining and it is part of every processor for decades. The ideal pipeline increases performance and efficiency for a relatively small cost. But the real pipeline has number of limitations caused by dependencies and hazards between instructions. The aim of this thesis is to discuss techniques used to improve efficency and performance of pipelined processors, to implement selected techniques to a RISC processor model and discuss its benefits.
32
Moussa, Imed. "Applications des circuits numériques en arseniure de gallium dans les systèmes à haut débit de communication et dans les calculateurs performants." Grenoble INPG, 1996. http://www.theses.fr/1996INPG0077.
Full textAbstract:
Ce document presente diverses applications des circuits numeriques en arseniure de gallium (asga) dans les systemes a haut debit de communication et dans les calculateurs performants. Ces applications ont guidees l'ensemble des recherches effectuees au cours de la these dont ce document est l'aboutissement. La necessite de performances elevees, inherentes aux applications traitees, a necessite l'etude et la mise en uvre de topologies differentes qui ont donne lieu a un ensemble de solutions efficaces. Dans le but d'obtenir une marge de bruit assez elevee et de bonnes performances en vitesse, en complexite et en puissance consommee, la conception de circuit en asga souleve des themes majeurs qui se resument aux points suivants: dimentionnement de transistors, topologies de masques, strategies d'amplification et de distribution d'horloges. Ils apparaissent nettement dans les applications traites qui sont decrites ci-dessous. La premiere application de la technologie asga dans les circuits a grande vitesse concerne la conception d'un diviseur redondant a 16 chiffres binaires. Une methode purement full custom a ete utilisee pour exploiter le potentiel de la technologie. Cette methode a permis des optimisations au niveau de la vitesse, de la densite et de la consommation. Le principal probleme mis en evidence lie a cette methode, est sa lourdeur d'emploi, qui la rend pratiquement inutilisable dans le cas des circuits a grande complexite. Pour mettre rapidement sur le marche un produit en asga, nous avons choisi de mettre en application les methodes de synthese de haut niveau afin de generer un chemin de donnees destine a un microprocesseur de type risc. L'avantage en temps de conception lie aux outils de synthese comportementale s'est avere compense par une augmentation de la surface d'implantation comparee a la methode full-custom. Ceci etant un facteur determinant en asga par rapport au cmos, technologie bien meilleur marche et initialement visee par cet outil, il est donc ressorti tres clairement de cette application l'interet d'appliquer un compromis consistant a synthetiser automatiquement des parties du circuit ou la vitesse n'est pas critique, et a utiliser la methode full custom pour les parties ou la vitesse est un parametre important. Cette derniere approche a ete adoptee pour la conception d'un circuit destine a des applications atm (asynchronous transfer mode). Ce circuit a ete concu pour fonctionner a une frequence de 312 mhz. La consommation de puissance a ete estimee autour de 4w, ce qui s'avere etre une performance tout a fait competitive compte tenu du debit a assumer, par rapport aux conceptions cmos existantes
33
Fabík, Peter. "Credit risk management v leasingové společnosti." Master's thesis, Vysoká škola ekonomická v Praze, 2007. http://www.nusl.cz/ntk/nusl-1580.
Full textAbstract:
Práce pojednává o řízení rizik v leasingové společnosti. Popisuje proces hodnocení bonity klienta a faktory ovlivňující schvalování obchodních případů. Charakterizuje ratingový a scoringový model v konkrétní leasingové společnosti, hodnotí jejich nedostatky a navrhuje změny na jejich vylepšení. Obsahuje i praktický příklad komplexního hodnocení obchodního případu včetně posouzení bonity klienta prostřednictvím ratingového modelu a nástrojů finanční analýzy.
34
Bach, Štěpán. "Standardy v oblasti Enterprise Risk Managementu." Master's thesis, Vysoká škola ekonomická v Praze, 2008. http://www.nusl.cz/ntk/nusl-3662.
Full textAbstract:
Faktory, jako například rostoucí globalizace, technologický vývoj, Internet a zvyšující se nároky vlastníků na vedení organizací v oblasti řízení rizik, vedly organizace ke změně jejich přístupu k řízení rizik. Nový přístup se označuje jako ?Enterprise Risk Management? (ERM). Podstatou ERM je efektivně řídit všechna rizika, kterým organizace čelí, a to na všech úrovních organizace jednotným a integrovaným způsobem. Práce charakterizuje ERM včetně důvodů vzniku, vývoje, definice obecného ERM procesu, současné situace a trendů. Podrobně jsou popsány vybrané čtyři nejvýznamnější standardy a rámcové publikace v oblasti ERM včetně jejich srovnání.
35
Pawlik, Jan. "Zavedení ISMS v podniku." Master's thesis, Vysoké učení technické v Brně. Fakulta podnikatelská, 2015. http://www.nusl.cz/ntk/nusl-224837.
Full textAbstract:
This master thesis deals with the implementation of the information security management system according to the standard ISO/IEC 27 001 in the environment of a small company. In the first part, it focuses on the theoretical background of the information security. The second part deals with the analysis of the company and concept of a company's measures to increase the security of information within the selected company.
36
Laukkanen, Antti. "Volkswagen V-Trek : The Rise of Mental Transportation." Thesis, Umeå universitet, Designhögskolan vid Umeå universitet, 2018. http://urn.kb.se/resolve?urn=urn:nbn:se:umu:diva-149717.
Full textAbstract:
I started this project with a mindset that I want to design something for younger generations living in the future megacities. After a while, trying to figure out their urban mobility needs, I came to this conclusion: Already today we have so many different options for urban com- muting as well as several different car sharing services. I couldn’t find a way to create some- thing new. I changed my approach and I started thinking; what is it that they don’t have? I pret- ty soon understood it. They have no nature. By the year 2040, 70% of world’s population is expected to live in urban areas. This, in turn, is diminishing the natural environments around the globe. Needless to say, that people are becoming more and more disconnected from nature. In my research I quoted George Monbiot from The Guardian: “If Children lose contact with nature, they won’t fight for it.” This de- scribes the problem to the core. Coming gen- erations need to know where all that we have comes from. This is why I decided to create a way, people in megacities can connect to nature instantly. Volkswagen V-Trek offers an instant escape to nature from megacities to conservation areas around the world. With an immersive full-body experience, V-Trek engages people with nature, as well as with Volkswagen as a brand. The concept is demonstrated in a visual story. The scenario of the events was created based on predictions and possible events in the future. Most of the time in my process I used for research about VR and other technologies related to the topic. As the physical movement is an important part of the concept, and because I wanted to enhance it on the platform, I spent time trying to figure it out. When things started to get together, I began to shape quick mockups in 3D for development of the form and archi- tecture. Later on in the process, it was easy to transform those mockups into sketch models and for testing in VR. The most important part of the project was the story and scenario, which justifies and ex- plains the whole concept. I started planning the scenario and the details early on which made it easier for me to visualize it in finalization phase. This project also raises a question: What comes next in the field of transportation and mobil- ity? For years’ cars and transportation have remained the same. We move from place A to B, this is what I call: Physical transportation. Right now we are living times of change as autono- mous technology is finally breaking through. However, cars have always been about the driv- ing experience and in autonomous future; trav- eling experience. Because of the changing atti- tudes towards cars amongst youth, cars are not seen as a pleasant experience anymore. Rather as a necessity. Experiences engage users with brands, whether it is a smartphone or a car, and this is what young users appreciate. When Physical transportation is no longer delivering that experience, car brands need to figure out a way to engage the users. This is where Mental Transportation changes the game. Mental Transportation is a term I came up with along the process and as the name suggests, it enables users to travel in their mind. With the idea of mental transportation, I want to chal- lenge everyone to think differently and with an open mind about the future of mobility and transportation.
37
Omishore, Abayomi. "Obytný soubor Brno Holásky, lokalita V Aleji." Master's thesis, Vysoké učení technické v Brně. Fakulta stavební, 2013. http://www.nusl.cz/ntk/nusl-225822.
Full textAbstract:
Master´s thesis proposes the design of low-rise residential complex in the city Brno - Tuřany, the cadastral territory Holásky. The location is defined from the west by the stream Černovický potok with natural monument - lakes Holásecká jezera, from the east by railway line Brno - Uherské Hradiště and from south by street U Potoka. The proposed area is west of the street V Aleji. The main objective was to use the framework conditions of the specified territory, propose urbanistic quality residential complex without losing the connection with the original structure of the township and to ensure full-fledged facilities for living, walking ,resting and recreation of the population.
38
Kravar, Jan. "Risk management pojišťovny v souvislosti s metodikou Solvency II." Master's thesis, Vysoká škola ekonomická v Praze, 2011. http://www.nusl.cz/ntk/nusl-124922.
Full textAbstract:
This final thesis deals with the risk management of the insurance company within the establishment of the new concept Solvency II valid for the each European Union member states in insurance industry. In first part, there are defined risks of the insurance company. Lamfalussy's legislative process used for concept Solvency II establishment is described in second part. New concept Solvency II, their objectives, three props, implementation time schedule as well as analysis of five quantitative impact studies is determined in third part. Final part of this thesis is focused on Risk management of the insurance company.
39
Ou, Po-Hsiang. "Climate change v Eurozone crisis : social and economic views of risk in inter-expert risk communication." Thesis, University of Oxford, 2015. https://ora.ox.ac.uk/objects/uuid:f3619fc5-fd2a-483b-92b5-94aa90ce13d1.
Full textAbstract:
This DPhil thesis discusses how two divergent risk conceptions, a 'social view' and an 'economic view' of risk, are constructed through inter-expert risk communication. Different and sometimes contradictory concepts of risk are mobilised in regulatory practice, but the origins of these divergent risk conceptions are not extensively studied. This thesis seeks to unpack this divergence. Empirically, I analyse risk communication among experts in the European Union (EU) during the creation of two risk regulation standards. The two case studies, one related to the development of the two-degree target of EU climate policies (the climate case) and the other about the negotiation of the excessive deficit criteria of the Maastricht Treaty (the euro case), can shed light on the relations between risk conceptions and inter-expert risk communication. I argue that through risk communication, an initial 'view' of risk can be entrenched and developed into a paradigmatic 'risk conception'. My analysis uses historical and sociological institutionalism, by focusing on path dependence of risk communication and social construction risk conceptions among EU experts. Through the two case studies, I identify four analytical dimensions of inter-expert risk communication: networks (the institutional setting and relationships between different experts), cultures (the mentalities of experts in relation to discussing risks), dynamics (the actual processes of transmitting and receiving risk messages) and strategies (the rationales supporting the decisions of risk regulation standards). My thematic analysis reveals four key distinct 'features' of social/economic views of risk: expertise (the types of knowledge mobilised), normality (characterising risk as either 'special' or 'routine'), probability (considering risk as either uncertain or calculable) and impact (seeing risk as either negative or positive). I argue that these four features can help explain the construction of risk conceptions, and more broadly, provide an analytical framework for studying how views of risk evolve and interact over time.
40
Almeida, N?dia Rossi de. "Ocorr?ncia da infec??o pelo V?rus da Leucemia Felina (FeLV) em gatos dom?sticos do munic?pio do Rio de Janeiro e Baixada Fluminense e an?lise dos fatores de risco para a infec??o." Universidade Federal Rural do Rio de Janeiro, 2009. https://tede.ufrrj.br/jspui/handle/tede/877.
Full textAbstract:
Made available in DSpace on 2016-04-28T20:17:29Z (GMT). No. of bitstreams: 1
2009 - Nadia Rossi de Almeida.pdf: 1219567 bytes, checksum: 83793b5f3d79ab19c2fe40b41ba26f70 (MD5)
Previous issue date: 2009-02-05The present study had the aim to make a survey of the Feline Leukemia Virus infection in domestic cats of Rio de Janeiro city and Baixada Fluminense region and to analyze risk factors involved in this infection. For this purpose, peripheral blood smears of 1094 cats had been submitted to indirect immunofluorescence for viral antigen detection and data relative to the animals surveyed, such as sex, age, race, access to the street, sexual life, housing, number of contactants and symptoms and/or clinical signals had been registered in individual files. Among the analyzed samples, 11,52% were positive for the test, corresponding to 11,49% of the animals collected at the Rio de Janeiro city and 11,62% of the collected samples at Baixada Fluminense region. The qui-square test was used for the descriptive analysis of all the selected variables, where only the significant variable had been included in multivariate analysis, by logistic regression. In accordance to these analysis, the access to the street, the age range between 1 and 5 years old and the cohabitation with too much cats in groups among 6 to15 cats and above of 15 cats had been considered risk factors for FeLV infection.
O presente estudo teve como objetivo pesquisar a ocorr?ncia da infec??o pelo V?rus da Leucemia Felina (FeLV) em gatos dom?sticos do munic?pio do Rio de Janeiro e Baixada Fluminense e tamb?m analisar fatores de risco envolvidos na infec??o por este retrov?rus. Para esta finalidade, esfrega?os de sangue perif?rico de 1.094 gatos foram submetidos ao teste de imunofluoresc?ncia indireta para pesquisa de ant?geno viral e os dados relativos aos animais, tais como o sexo, idade, ra?a, acesso ? rua, vida sexual, moradia, n?mero de contactantes e sintomas e/ou sinais cl?nicos foram registrados em fichas individuais. Do total de amostras analisadas, 11,52% apresentaram positividade para o teste, correspondendo a 11,49% de ocorr?ncia da infec??o em animais do munic?pio do Rio de Janeiro e 11,62% da Baixada Fluminense. O teste de qui-quadrado foi utilizado para a an?lise descritiva de todas as vari?veis levantadas, onde apenas as vari?veis que apresentaram signific?ncia foram inclu?das na an?lise multivariada, atrav?s da regress?o log?stica. De acordo com estas an?lises, o acesso ? rua, a faixa et?ria entre 1 e 5 anos de idade e a conviv?ncia com demais gatos na faixa entre 6 e 15 gatos e acima de 15 gatos foram fatores de risco para a infec??o pelo FeLV.
41
Whitworth, Lloyd R. "Software risk management : a case study of the V-22 program /." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1996. http://handle.dtic.mil/100.2/ADA307865.
Full text
42
Vrátil, Tomáš. "Analýza a řízení rizik podnikatelského subjektu provozujícího svoji hospodářskou činnost v zemědělském odvětví." Master's thesis, Vysoká škola ekonomická v Praze, 2010. http://www.nusl.cz/ntk/nusl-96395.
Full textAbstract:
The aim of this thesis is to describe the methods, tools and procedures for analysis and risk management businesses. Another objective is to identify specific features of the agricultural sector and to identify the risks that are unique to this sector. The identification and risk assessment of the significance of the selected business entity is part of the thesis. The main contribution of this thesis is processing of risk management. This section consists of the recommendations and proposals in the field of preventing and reducing the impact of risks on the business entity and suggestions for possible improvements of the current situation in order to increase the stability, resilience and flexibility of the entity.
43
De, Sancho Maria. "Risk factors for clinical manifestations in carriers of Factor V Leiden and prothrombin gene mutations /." Access full-text from WCMC, 2008. http://proquest.umi.com/pqdweb?did=1695109691&sid=1&Fmt=2&clientId=8424&RQT=309&VName=PQD.
Full text
44
Kneblová, Jana. "Metody analýzy korporátních ukazatelů a jejich využití v rámci preventivního Risk managementu pro Škoda Auto a.s." Master's thesis, Vysoké učení technické v Brně. Fakulta podnikatelská, 2015. http://www.nusl.cz/ntk/nusl-224954.
Full textAbstract:
The Diploma thesis deals with the methods of analysis of corporate indicators and their use in the context of preventive Risk management for company Skoda Auto a.s.. Based on the performed analysis is optimized current process and are proposed new corporate indicators in the context of preventive Risk management.
45
Fotso, Milly. "Risk Gene v. Safety Net: An Analysis of the Factors the Drive Individuals to Become Entrepreneurs." Scholarship @ Claremont, 2016. http://scholarship.claremont.edu/cmc_theses/1216.
Full textAbstract:
The goal of this paper is to outline patterns in biographical background of founders of successful startup ventures, more particularly in the technology sector, that contributed to their success. Additionally, this article aims to disprove the assumption that entrepreneurs have a special tolerance for risk, and rather explores the idea that entrepreneurs have access to resources--financial, social, and intellectual--that come from their family and friends that then give them an edge and a safety net that de-mystifies them from the risk of starting a business. Once we realize that because the majority of the entrepreneurs studied in this thesis had unusually privileged backgrounds, we may then end with a suggestion as to how to level the playing field for those who may not have the same.
46
Smoleňák, Ivo. "Rizikové investice v rodinném portfoliu." Master's thesis, Vysoká škola ekonomická v Praze, 2009. http://www.nusl.cz/ntk/nusl-76896.
Full textAbstract:
Diploma thesis is trying to find the main factors influencing investment decisions of Czech households and effectiveness of their saving. Habits of Czech households are compared with the economically advanced countries, where efficiency in savings is much higher. Work reveals the possibility of value funds, but also the risks that accompany investment. In the final part is swowm, how different could be the effectivenes of risk seeking household in compare to the conservative one.
47
Hu, Lijiao. "ECONOMIC ANALYSIS OF CARBON SEQUESTRATION UNDER CATASTROPHIC RISK AND PRICE UNCERTAINTY IN KENTUCKY." UKnowledge, 2014. http://uknowledge.uky.edu/agecon_etds/25.
Full textAbstract:
Internalizing carbon value for forest landowners has the potential to increase carbon supply in forest and mitigate CO2 in the atmosphere. In this study, we developed a modified Hartman model to investigate how payments of carbon offsets impact the optimal management of hardwood forests in Kentucky under condition of catastrophic events. Different carbon markets were modeled and several sensitivity analyses were performed to examine varied management strategies to achieve maximized financial return or highest environmental benefits. Furthermore, another model was developed to incorporate the impact of risk aversion to price uncertainty using E-V model. We were able to identify the most favorable scenarios for landowners and society in the face of price variability and catastrophic risk.
48
Pinto, Flávia Morais Gomes. "Desinfecção das canetas de alta rotação com álcool 70% p/v sem limpeza prévia: avaliação do risco de infecção cruzada." Universidade de São Paulo, 2013. http://www.teses.usp.br/teses/disponiveis/7/7139/tde-20092013-091255/.
Full textAbstract:
Introdução: Na prática clínica odontológica, justificada pela praticidade, tempo curto disponível entre os atendimentos, associados à insuficiente previsão e provisão das Canetas de Alta Rotação (CAR), a descontaminação destas por meio de aplicação direta do álcool 70% p/v, sem limpeza prévia, é uma realidade. Este procedimento contraria, a priori, os protocolos de processamento que recomendam, no mínimo, limpeza seguida de desinfecção de alto nível para prevenção de infecção cruzada. Objetivo: avaliar a desinfecção das CAR com álcool 70% p/v, sem limpeza prévia com vistas ao risco de causar infecção cruzada. Método: caracterizou-se como uma pesquisa pragmática em um Estabelecimento Odontológico, onde rotineiramente as práticas de interesse para o estudo estavam presentes. O grupo experimental foi composto por 100 amostras de CAR utilizadas em tratamentos diversos, após a fricção do desinfetante por 90 segundos em sua superfície externa. Para avaliação dos resultados, uma gaze umedecida com soro fisiológico foi utilizada como carreador para o arraste dos possíveis micro-organismos nas superfícies desinfetadas. Metade do número das amostras (50) foi analisada pelo método de filtração por membrana (Método I - quantitativo), sendo cada gaze imersa em 300 mL de solução fisiológica. Sequencialmente, as amostras foram expostas a sonicação e agitação. Em seguida, o lavado foi filtrado em três partes iguais para diferentes análises (micro-organismos aeróbios, anaeróbios e específicos da microbiota oral humana), por meio da membrana com porosidade de 0,45 m. As outras 50 amostras foram analisadas pelo método de imersão direta da gaze em meio de cultura Fluid Thioglycollate Medium (Método II qualitativo). O tubo contendo a gaze foi agitado e incubado a 37ºC por 21 dias. Resultados: as amostras analisadas pelo Método I apresentaram crescimento positivo em 27/50 (54%) das amostras na faixa de 100 a 102 UFC/amostra. Deste total, foram identificados sete micro-organismos distintos, representados por 37,1% do Staphylococcus coagulase negativa, 28,5% dos Bacillus spp, 17,1% dos Bacilo Gram positivos não esporulados, 5,7% dos Micrococcus spp, 5,7% dos Penicillium spp, 2,8% Acinetobacter baumannii e 2,8% da Candida spp. No grupo analisado pelo Método II, o total de tubos com crescimento positivo foi de 12/50 (24%) amostras. Deste total, foram identificados três micro-organismos distintos, sendo 38,4% de Bacilos Gram positivos inespecíficos, seguidos dos Staphylococcus spp e Peptococcus spp com a mesma porcentagem de positividade de 30,7% cada. O grupo controle negativo, composto por amostras submetidas à limpeza e esterilização consecutiva, apresentaram resultados satisfatórios de ausência microbiana na totalidade das amostras. O crescimento médio encontrado no grupo controle positivo foi de 17,5 UFC/placa, com exceção de uma amostra que apresentou crescimento incontável. Conclusão: os resultados da presente investigação reprovam a prática da descontaminação das CAR com álcool 70% p/v, sem limpeza prévia, substanciada pela sobrevivência de micro-organismos que não corresponderam à ação fungicida e bactericida esperada do álcool 70% p/v na condição de desinfetante de nível intermediário. Outro aspecto que reforça a reprovação da prática analisada é a consideração de que os micro-organismos recuperados, mesmo sendo de baixo potencial patogênico, podem comportar-se como anfibiontes, isto é, são capazes de agredir o hospedeiro quando as condições ambientais e imunológicas são favoráveis aos micro-organismos, causando infecção.Introduction: In dental clinical practice, decontamination of high-speed dental equipment (HSDE) by direct use of 70% ethanol without previous cleaning, justified by practicality, the short-time available between appointments, together with inadequate predicting and provision of HSDE, is a reality. This procedure, a priori, contradicts the processing protocols recommended to prevent cross-infection. Objective: to evaluate the disinfection of HSDE with 70% ethanol without previous cleaning, with views of cross-infection risk. Method: the present study was characterized as a pragmatic research in a Dental Office, which practices of interest to the study were routinely performed. The experimental group consisted of 100 samples of HSDE used in different treatments after rubbing the disinfectant for 90 seconds on its outer surface. To evaluate the results, gauze moistened with saline solution was used as a carrier for obtaining microorganisms from the disinfected surfaces. Half of the samples (50) were analyzed by membrane filtration (Method I - quantitative), with the gauze being immersed in 300 mL of saline solution. Sequentially, the sample was exposed to sonication and agitation. After that, the lavage was filtered in three equal parts for different analyses, through a membrane with 0.45 m porosity and seeded on blood agar culture medium, for recovery of aerobic and anaerobic microorganisms, as well as those specifically found in the human oral microbiota. The other 50 samples were analyzed by direct immersion of the gauze in culture medium (Method II - Qualitative): after rubbing the wet gauze on the outer surface of the HSDE, it was placed directly in Fluid Thioglycollate culture medium. The tube containing the gauze was shaken in a vortex mixer and then incubated at 37 ° C for 21 days. Results: samples analyzed by Method I, showed positive growth in 27/50 (54%) of the samples within the range of 100 to 102 CFU/sample. Of this total, 7 different microorganisms were identified, represented by 37.1% of coagulase-negative Staphylococcus, 28.5% of Bacillus spp, 17.1% of non-sporulating Gram-positive bacillus, 5.7% of Micrococcus spp, 5.7 % of Penicillium spp, 2.8% of Acinetobacter baumannii and 2.8% of Candida spp. In the group analyzed by Method II, the total number of tubes with positive growth was 12/50 (24%) samples. Of this total, we identified 2 different microorganisms, being 38.4% of Gram-positive bacillus nonspecific, followed by Staphylococcus spp and Peptococcus spp with the same percentage of positivity of 30.7% each. The negative control group, composed of samples subjected to cleaning and sterilization consecutive showed satisfactory results. The average growth found in the positive control group was 17.5 CFU/sample, except for one sample that showed growth uncountable. Conclusion: the results of the present study do not support the practice of decontamination of HSDE with 70% ethanol without previous cleaning, based on the evidence of microorganism survival that did not meet the expected bactericidal and fungicidal action of alcohol as an intermediate level disinfectant. Another aspect that reinforces the disapproval this practice, it is the consideration that the micro-organisms recovered, even being low pathogenic potential, may behave as anfibionte, which are capable of harming the host when the environmental and immune conditions are favorable to micro-organisms, causing infection.
49
Lipovský, Tomáš. "Modelování rizik v dopravě." Master's thesis, Vysoké učení technické v Brně. Ústav soudního inženýrství, 2016. http://www.nusl.cz/ntk/nusl-241283.
Full textAbstract:
This thesis deals with theoretical basics of risk modelling in transportation and optimization using aggregated traffic data. In this thesis is suggested the procedure and implemented the application solving network problem of shortest path between geographical points. The thesis includes method for special paths evaluation depending on the frequency of traffic incidents based on real historical data. The thesis also includes a~graphical interface for presentation of the achieved results.
50
Krindges, Cris Aline. "Regula??o emocional, satisfa??o sexual e comportamento sexual de risco em mulheres v?timas de abuso sexual na inf?ncia." Pontif?cia Universidade Cat?lica do Rio Grande do Sul, 2016. http://tede2.pucrs.br/tede2/handle/tede/6745.
Full textAbstract:
Submitted by Setor de Tratamento da Informa??o - BC/PUCRS (tede2@pucrs.br) on 2016-06-03T18:21:56Z
No. of bitstreams: 1
DIS_CRIS_ALINE_KRINDGES_PARCIAL.pdf: 254839 bytes, checksum: 77badb2f05a6fc3ec73c1c32e78f2f50 (MD5)Made available in DSpace on 2016-06-03T18:21:56Z (GMT). No. of bitstreams: 1 DIS_CRIS_ALINE_KRINDGES_PARCIAL.pdf: 254839 bytes, checksum: 77badb2f05a6fc3ec73c1c32e78f2f50 (MD5) Previous issue date: 2016-03-04
Child sexual abuse (CSA) is considered a public health problem. It includes social, cultural, psychological, medical and legal aspects, and it can be an inciting factor of different consequences for the human development. This thesis aimed to observe women who were CSA victims and the consequences for adulthood, concerning emotion regulation, sexual satisfaction and risky sexual behavior. The research consists of two articles: the literature narrative review and the empirical study. The literature narrative review focuses on the CSA through empirical studies review on this theme. Some significant CSA consequences were verified in the sexual satisfaction scope, such as the lack of pleasure, besides the sexual aversion and avoidance. However, there are some opposite results in which CSA victims also presented major excitation, sexual desire and satisfaction in sexual relations. The review study showed there is no unanimity in literature and the CSA may affect the sexual satisfaction in different ways. In the empirical study, I aimed to investigate the CSA consequences for emotion regulation, sexual satisfaction and risky sexual behavior based on a descriptive and exploratory analysis. Eight women over the age of 18 and presenting some CSA episode were subjects for this study. The evaluation occurred through self-report scale and semi-structured interview and results showed that all the evaluated CSA victims presented different levels of emotion dysregulation. In regard to sexual satisfaction, in some cases, women reported difficulties, whereas others reported the preservation of their sexual desire and satisfaction. Risky sexual behaviors were identified in only two cases and remitted the sexual experiences of the past. These results are relevant for understanding potential long-term CSA repercussions and helping with effective psychological intervention for specific cases of women with history of sexual victimization in childhood.
O abuso sexual na inf?ncia (ASI) ? considerado um problema de sa?de p?blica, englobando aspectos sociais, culturais, psicol?gicos, m?dicos e jur?dicos e pode ser fator desencadeante de diferentes consequ?ncias para o desenvolvimento humano. Esta disserta??o objetivou avaliar mulheres v?timas de ASI e as consequ?ncias para a vida adulta, em rela??o ? regula??o emocional, satisfa??o sexual e comportamento sexual de risco. A disserta??o ? composta por dois artigos, sendo um estudo de revis?o narrativa da literatura e um estudo emp?rico. O estudo de revis?o narrativa da literatura aborda as consequ?ncias do ASI por meio da revis?o de estudos emp?ricos nesta tem?tica. Foram verificadas consequ?ncias significativas do ASI no ?mbito da satisfa??o sexual, como aus?ncia de prazer, avers?o e evita??o sexual. Por?m, resultados opostos foram identificados, nos quais v?timas de ASI tamb?m possu?am maior excita??o e desejo sexual, assim como satisfa??o nas rela??es sexuais. O estudo de revis?o indicou n?o haver um consenso na literatura e que o ASI pode afetar a satisfa??o sexual de diferentes formas. No estudo emp?rico buscou-se investigar as consequ?ncias do ASI para a regula??o emocional, satisfa??o sexual e comportamento sexual de risco a partir de uma an?lise descritiva e explorat?ria. Participaram deste estudo oito mulheres com idade acima de 18 anos e com algum epis?dio de ASI. A avalia??o ocorreu por meio de escalas de autorrelato e entrevista semiestruturada. Os resultados demonstraram que todas as v?timas de ASI avaliadas possu?am dificuldades de regula??o emocional, em diferentes n?veis. Em rela??o ? satisfa??o sexual, em alguns casos as mulheres relataram dificuldades, no entanto outras relataram desejo e satisfa??o sexual preservados. Comportamentos sexuais de risco foram identificados em apenas dois casos e remetidos a experi?ncias sexuais do passado. Estes resultados s?o relevantes para compreender poss?veis repercuss?es da ASI em longo prazo e para subsidiar interven??es psicol?gicas efetivas para demandas espec?ficas de mulheres com hist?rico de vitimiza??o sexual na inf?ncia.