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Journal articles on the topic 'RISC-V'

Author: Grafiati
Published: 4 June 2021
Last updated: 25 January 2025

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1

Frolov, Vladimir Alexandrovitch, Vladimir Alexandrovitch Galaktionov, and Vadim Vladimirovitch Sangarov. "Investigation of the RISC-V." Proceedings of the Institute for System Programming of the RAS 32, no. 2 (2020): 81–98. http://dx.doi.org/10.15514/ispras-2020-32(2)-7.

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2

Frolov, V. A., V. A. Galaktionov, and V. V. Sanzharov. "Investigation of RISC-V." Programming and Computer Software 47, no. 7 (December 2021): 493–504. http://dx.doi.org/10.1134/s0361768821070045.

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3

Felzmann, Isaias, Joao Fabricio Filho, and Lucas Wanner. "Risk-5: Controlled Approximations for RISC-V." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, no. 11 (November 2020): 4052–63. http://dx.doi.org/10.1109/tcad.2020.3012312.

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4

Greengard, Samuel. "Will RISC-V revolutionize computing?" Communications of the ACM 63, no. 5 (April 20, 2020): 30–32. http://dx.doi.org/10.1145/3386377.

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5

Шабан, Максим. "ІМПЛЕМЕНТАЦІЯ НАБОРУ ІНСТРУКЦІЇ RISC-V." Ukrainian Scientific Journal of Information Security 28, no. 2 (December 4, 2022): 80–86. http://dx.doi.org/10.18372/2225-5036.28.16948.

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В 70-х роках минулого сторіччя, під час активного розвитку електронно-обчислювальної техніки, розвиток обчислювальних систем пішов двома шляхами: високопродуктивні обчислювальні системи (ОС); вузькопрофільні обчислювальні системи. Фактично, високопродуктивні системи – це універсальні ОС завданням яких є максимальна висока швидкість обчислень за одиницю часу. Вузькопрофільні ОС ставили за мету виконання певних типів завдань, де якраз швидкість обчислень не мала такого значення, а на перші ролі виходили інші технічні характеристики: енергоефективність, ергономіка виробу, необхідність виконання тільки певного роду завдань та інше. Саме вид завдань став вирішальним з точки зору архітектурної реалізації ОС. Розглянемо архітектуру RISC-V з метою оцінки перспективності впровадження її до масового сегменту.
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Núñez-Prieto, Ricardo, David Castells-Rufas, and Lluís Terés-Terés. "RisCO2: Implementation and Performance Evaluation of RISC-V Processors for Low-Power CO2 Concentration Sensing." Micromachines 14, no. 7 (July 4, 2023): 1371. http://dx.doi.org/10.3390/mi14071371.

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In the field of embedded systems, energy efficiency is a critical requirement, particularly for battery-powered devices. RISC-V processors have gained popularity due to their flexibility and open-source nature, making them an attractive choice for embedded applications. However, not all RISC-V processors are equally energy-efficient, and evaluating their performance in specific use cases is essential. This paper presents RisCO2, an RISC-V implementation optimized for energy efficiency. It evaluates its performance compared to other RISC-V processors in terms of resource utilization and energy consumption in a signal processing application for nondispersive infrared (NDIR) CO2 sensors.The processors were implemented in the PULPino SoC and synthesized using Vivado IDE. RisCO2 is based on the RV32E_Zfinx instruction set and was designed from scratch by the authors specifically for low-power signal demodulation in CO2 NDIR sensors. The other processors are Ri5cy, Micro-riscy, and Zero-riscy, developed by the PULP team, and CV32E40P (derived from Ri5cy) from the OpenHW Group, all of them widely used in the RISC-V community. Our experiments showed that RisCO2 had the lowest energy consumption among the five processors, with a 53.5% reduction in energy consumption compared to CV32E40P and a 94.8% reduction compared to Micro-riscy. Additionally, RisCO2 had the lowest FPGA resource utilization compared to the best-performing processors, CV32E40P and Ri5cy, with a 46.1% and a 59% reduction in LUTs, respectively. Our findings suggest that RisCO2 is a highly energy-efficient RISC-V processor for NDIR CO2 sensors that require signal demodulation to enhance the accuracy of the measurements. The results also highlight the importance of evaluating processors in specific use cases to identify the most energy-efficient option. This paper provides valuable insights for designers of energy-efficient embedded systems using RISC-V processors.
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V, Prof Jaswanth. "Implementation and Evaluation of SIMD Instructions using RISC-V." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 08, no. 05 (May 15, 2024): 1–5. http://dx.doi.org/10.55041/ijsrem34010.

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This thesis introduces and explores the design and verification of a packed Single Instruction, Multiple Data (SIMD) instruction set for a RISC-V processor, known as the RISC-V P extension. This extension enhances the RISC-V instruction set architecture by providing packed SIMD support for 8-bit, 16-bit, and 32-bit integer data types. The significance of this architecture lies in its potential to empower developers in constructing more efficient and powerful data-parallel programs for RISC-V processors. This contribution enhances the overall capabilities of the RISC-V ecosystem, providing a valuable extension to the instruction set architecture for data-parallel applications. Keywords: Data-parallel Programs, instruction set architecture, RISC-V, P extension, Packed SIMD
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8

Rajveer Singh, Et al. "RISC-V Processor for IOT Applications." International Journal on Recent and Innovation Trends in Computing and Communication 11, no. 11 (December 31, 2023): 701–5. http://dx.doi.org/10.17762/ijritcc.v11i11.10074.

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RISC-V is a recently introduced instruction-set architecture (ISA) that offers innovative advantages, including low power consumption, affordability, and scalability. Utilizing an open, non-proprietary Instruction Set Architecture (ISA) enables the creation of on-the-fly design of soft error countermeasures at the microarchitecture level. This may significantly enhance the resilience of Application Specific Standard Products (ASSP) and FPGA implementations. This paper offers a quick overview of the RISC-V architecture. This paper presents a plan to create and execute a 32-bit single-cycle RISC-V processor using Verilog HDL in the Vivado software.
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Строгонов, А. В., А. Винокуров, and А. И. Строгонов. "ПРИМЕР РЕАЛИЗАЦИИ ОДНОТАКТНОГО ПРОЦЕССОРНОГО ЯДРА RISC-V В САПР ALTERA QUARTUS II." ELECTRONICS: SCIENCE, TECHNOLOGY, BUSINESS 240, no. 9 (October 18, 2024): 70–79. https://doi.org/10.22184/1992-4178.2024.240.9.70.79.

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В России продолжается популяризация и развитие открытой архитектуры RISC-V. Сегодня разработкой проектов на базе открытой архитектуры RISC-V занимается ряд российских компаний и ведущих университетов. Например, микроконтроллер Hackee на базе ядра SCR1 (от российского разработчика Syntacore) был спроектирован совместно магистрантами НИУ «МИЭТ» и специалистами компании Yadro. «Микрон» представил микроконтроллер «MIK32 Амур» (К1948ВК018) на базе RISC-V и отладочную плату на его основе. Есть проекты и других российских компаний, действующих в рамках «Альянса RISC-V» [1]. Одним из направлений исследований в этой области является отработка прототипов процессоров на платформе ПЛИС. В статье рассмотрен пример реализации однотактного процессорного ядра RISC-V в базисе ПЛИС Cyclone V с применением САПР Altera Quartus II.
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10

P, Pavan, Kamal P S, Govardhan G, and Suresh Kumar V. "Basic RISC-V Instruction Set Architecture: Design and Validation." International Journal for Research in Applied Science and Engineering Technology 11, no. 5 (May 31, 2023): 2845–50. http://dx.doi.org/10.22214/ijraset.2023.52205.

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Abstract: This project's primary goal is to design and implement a simple RISC V instruction set architecture. This paper offers insights into the architecture of the risc v instruction set. This system employs the RISC V R-type (register) type instruction format. Using this format, we designed the fundamental isa and tested its functionality using verilog code. There is no licence fee for using RISC V, an open source isa that is available to everyone. Reduced instruction set (RISC) computers are created to make the individual instructions given to computers to perform various tasks more manageable. Most instruction set architectures, or isas, are proprietary and cannot be used or modified without permission from the companies; as a result, an isa that is free and open source, which is provided by risc v, will help in increasing the speed and lowering system costs by using these instruction set formats, and we are designing 32 bit isa architecture. instruction formats for the risc v instruction set architecture
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11

Yoo, Taeho, and Byoung Wook Choi. "Real-Time Performance Benchmarking of RISC-V Architecture: Implementation and Verification on an EtherCAT-Based Robotic Control System." Electronics 13, no. 4 (February 11, 2024): 733. http://dx.doi.org/10.3390/electronics13040733.

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RISC-V offers a modular technical approach combined with an open, royalty-free instruction set architecture (ISA). However, despite its advantages as a fundamental building block for many embedded systems, the escalating complexity and functional demands of real-time applications have made adhering to response time deadlines challenging. For real-time applications of RISC-V, real-time performance analysis is required for various ISAs. In this paper, we analyze the real-time performance of RISC-V through two real-time approaches based on processor architectures. For real-time operating system (RTOS) applications, we adopted FreeRTOS and evaluated its performance on HiFive1 Rev B (RISC-V) and STM3240G-EVAL (ARM M). For real-time Linux, we utilized Linux with the Preempt-RT patch and tested its performance on VisionFive 2 (RISC-V), MIO5272 (x86-64), and Raspberry Pi 4 B (ARM A). Through these experiments, we examined the response times on the real-time mechanisms of each operating system. Additionally, in the Preempt-RT experiments, scheduling latencies were evaluated by means of the cyclictest. These are very important parameters for implementing real-time applications comprised of multi-tasking. Finally, in order to show the real-time capabilities of RISC-V practically, we implemented motion control of a six-axis collaborative robot, which was performed on the VisionFive 2. This implementation provided a comparative result of RISC-V’s performance against the x86-64 architecture. Ultimately, the results indicated that the real-time performance of RISC-V for real-time applications was feasible. A noticeable achievement of this research is its first implementation of an EtherCAT master on RISC-V designed for real-time applications. The successful implementation of the EtherCAT master on RISC-V shows real-time capabilities for a wide range of real-time applications.
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12

Pitcher, Graham. "RISC-V Powers IoT Apps Processor." New Electronics 51, no. 4 (February 27, 2018): 7. http://dx.doi.org/10.12968/s0047-9624(23)60141-5.

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13

Tan, Zhangxi, Lin Zhang, David Patterson, and Yi Li. "PicoRio: An open-source, RISC-V small-board computer to elevate the RISC-V software ecosystem." Tsinghua Science and Technology 26, no. 3 (June 2021): 384–86. http://dx.doi.org/10.26599/tst.2020.9010037.

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14

Coluccio, Andrea, Antonia Ieva, Fabrizio Riente, Massimo Ruo Roch, Marco Ottavi, and Marco Vacca. "RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures." Electronics 11, no. 19 (September 21, 2022): 2990. http://dx.doi.org/10.3390/electronics11192990.

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Most modern CPU architectures are based on the von Neumann principle, where memory and processing units are separate entities. Although processing unit performance has improved over the years, memory capacity has not followed the same trend, creating a performance gap between them. This problem is known as the "memory wall" and severely limits the performance of a microprocessor. One of the most promising solutions is the "logic-in-memory" approach. It consists of merging memory and logic units, enabling data to be processed directly inside the memory itself. Here we propose an RISC-V framework that supports logic-in-memory operations. We substitute data memory with a circuit capable of storing data and of performing in-memory computation. The framework is based on a standard memory interface, so different logic-in-memory architectures can be inserted inside the microprocessor, based both on CMOS and emerging technologies. The main advantage of this framework is the possibility of comparing the performance of different logic-in-memory solutions on code execution. We demonstrate the effectiveness of the framework using a CMOS volatile memory and a memory based on a new emerging technology, racetrack logic. The results demonstrate an improvement in algorithm execution speed and a reduction in energy consumption.
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Tiwari, Sugandha, Neel Gala, Chester Rebeiro, and V. Kamakoti. "PERI." ACM Transactions on Architecture and Code Optimization 18, no. 3 (June 2021): 1–26. http://dx.doi.org/10.1145/3446210.

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Owing to the failure of Dennard’s scaling, the past decade has seen a steep growth of prominent new paradigms leveraging opportunities in computer architecture. Two technologies of interest are Posit and RISC-V. Posit was introduced in mid-2017 as a viable alternative to IEEE-754, and RISC-V provides a commercial-grade open source Instruction Set Architecture (ISA). In this article, we bring these two technologies together and propose a Configurable Posit Enabled RISC-V Core called PERI. The article provides insights on how the Single-Precision Floating Point (“F”) extension of RISC-V can be leveraged to support posit arithmetic. We also present the implementation details of a parameterized and feature-complete posit Floating Point Unit (FPU). The configurability and the parameterization features of this unit generate optimal hardware, which caters to the accuracy and energy/area tradeoffs imposed by the applications, a feature not possible with IEEE-754 implementation. The posit FPU has been integrated with the RISC-V compliant SHAKTI C-class core as an execution unit. To further leverage the potential of posit , we enhance our posit FPU to support two different exponent sizes (with posit-size being 32-bits), thereby enabling multiple-precision at runtime. To enable the compilation and execution of C programs on PERI, we have made minimal modifications to the GNU C Compiler (GCC), targeting the “F” extension of the RISC-V. We compare posit with IEEE-754 in terms of hardware area, application accuracy, and runtime. We also present an alternate methodology of integrating the posit FPU with the RISC-V core as an accelerator using the custom opcode space of RISC-V.
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Xiang, Mingxi, Rui Ding, Haijun Liu, and Xichuan Zhou. "Latency-Constrained Neural Architecture Search Method for Efficient Model Deployment on RISC-V Devices." Electronics 13, no. 4 (February 8, 2024): 692. http://dx.doi.org/10.3390/electronics13040692.

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The rapid development of the RISC-V instruction set architecture (ISA) has garnered significant attention in the realm of deep neural network applications. While hardware-aware neural architecture search (NAS) methods for ARM, X86, and GPUs have been extensively explored, research specifically targeting RISC-V remains limited. In light of this, we propose a latency-constrained NAS (LC-NAS) method specifically designed for RISC-V. This method enables efficient network searches without the requirement of network training. Concretely, in the training-free NAS framework, we introduce an RISC-V latency evaluation module that includes two implementations: a lookup table and a latency predictor based on a deep neural network. To obtain real latency data, we have designed a specialized data collection pipeline for RISC-V devices, which allows for precise end-to-end hardware latency measurements. We validate the effectiveness of our method in the NAS-Bench-201 search space. Experimental results demonstrate that our method can efficiently search for latency-constrained networks for RISC-V devices within seconds while maintaining high accuracy. Additionally, our method can easily integrate with existing training-free NAS approaches.
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Gomes, Tiago, Pedro Sousa, Miguel Silva, Mongkol Ekpanyapong, and Sandro Pinto. "FAC-V: An FPGA-Based AES Coprocessor for RISC-V." Journal of Low Power Electronics and Applications 12, no. 4 (September 27, 2022): 50. http://dx.doi.org/10.3390/jlpea12040050.

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In the new Internet of Things (IoT) era, embedded Field-Programmable Gate Array (FPGA) technology is enabling the deployment of custom-tailored embedded IoT solutions for handling different application requirements and workloads. Combined with the open RISC-V Instruction Set Architecture (ISA), the FPGA technology provides endless opportunities to create reconfigurable IoT devices with different accelerators and coprocessors tightly and loosely coupled with the processor. When connecting IoT devices to the Internet, secure communications and data exchange are major concerns. However, adding security features requires extra capabilities from the already resource-constrained IoT devices. This article presents the FAC-V coprocessor, which is an FPGA-based solution for an RISC-V processor that can be deployed following two different coupling styles. FAC-V implements in hardware the Advanced Encryption Standard (AES), one of the most widely used cryptographic algorithms in IoT low-end devices, at the cost of few FPGA resources. The conducted experiments demonstrate that FAC-V can achieve performance improvements of several orders of magnitude when compared to the software-only AES implementation; e.g., encrypting a message of 16 bytes with AES-256 can reach a performance gain of around 8000× with an energy consumption of 0.1 μJ.
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Строгонов, А. В., О. Бордюжа, and А. И. Строгонов. "МЕЖДУНАРОДНЫЙ ОПЫТ РАЗРАБОТКИ ПРОЦЕССОРНЫХ ЯДЕР RISC-V И ПРОГРАММНЫЕ ИНСТРУМЕНТЫ С ОТКРЫТЫМ КОДОМ ДЛЯ ИХ ПРОЕКТИРОВАНИЯ." ELECTRONICS: SCIENCE, TECHNOLOGY, BUSINESS 238, no. 7 (August 12, 2024): 156–64. https://doi.org/10.22184/1992-4178.2024.238.7.156.164.

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В России и Китае большой интерес проявляют к процессорной архитектуре RISC-V. В сентябре 2022 года в России была создана ассоциация независимых разработчиков ПО и вычислительной техники на основе RISC-V, которая получила название «Альянс RISC-V». В него вошли производитель серверов и систем хранения данных Yadro («КНС групп»), разработчик процессоров «Байкал Электроникс», разработчик ОС Astra Linux группа «Астра», разработчик технологической программно- аппаратной платформы Vostok и НИУ «Московский институт электронной техники». В статье рассмотрен опыт разработки процессорных ядер RISC-V коммерческого применения на примере процессоров компаний MIPS, SiFive, Alibaba Cloud Intelligence, а также академические проекты Rocket Chip Калифорнийского университета в Беркли и XiangShan Китайской академии наук.
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Michel Deves de Souza, Eduardo, Nathalia Nathalia Adriana de Oliveira, Douglas Almeida dos Santos Almeida dos Santos, and Douglas Rossi de Melo. "RVSH - Um processador RISC-V para fins didáticos." Anais do Computer on the Beach 14 (May 3, 2023): 450–52. http://dx.doi.org/10.14210/cotb.v14.p450-452.

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ABSTRACTEmbedded systems constitute the class of computers that presentthe most significant volume and are increasingly present ineveryday life. The main element of these systems is the processor,which can be found in discrete form, represented by a physicalcomponent, or cores, as used in programmable logic devices.Processors of the same architecture share the same instructionset but may differ in the organization’s implementation. RISC(Reduced Instruction Set Computer) is the class of architecturesthat favors a simple, reduced instruction set. RISC-V is an exampleof such architecture, which consists of an initiative by academiaand industry to be open and free, aiming for easy and optimizedimplementations. However, due to the recent disclosure of itsfeatures and specifications, RISC-V needs more reference materialfor digital and embedded system designs. This work proposesthe RVSH, a simple RISC-V processor for teaching and researchactivities. The implementation aims to allow the adoption of thisarchitecture in topics such as digital systems, computer architecture,microcontrollers, and embedded systems design.
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Uzuner, Hakan, and Elif Bilge Kavun. "NLU-V: A Family of Instruction Set Extensions for Efficient Symmetric Cryptography on RISC-V." Cryptography 8, no. 1 (February 29, 2024): 9. http://dx.doi.org/10.3390/cryptography8010009.

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Cryptographic primitives nowadays are not only implemented in high-performance systems but also in small-scale systems, which are increasingly powered by open-source processors, such as RISC-V. In this work, we leverage RISC-V’s modular base instruction set and architecture to propose a generic instruction set extension (ISE) for symmetric cryptography. We adapt the work from Engels et al. in ARITH’13, the non-linear/linear instruction set extension (NLU), which presents a generic hardware/software co-design solution for efficient symmetric crypto implementations through a hardware unit extending the 8-bit AVR instruction set. These new instructions realize non-linear and linear layers, which are widely used to implement the block ciphers in symmetric cryptography. Our proposal modifies and extends the NLU instructions to a 32-bit RISC-V architecture; hence, we call the proposed ISE ‘NLU-V’. The proposed architecture is integrated into the open-source RISC-V implementation ‘Icicle’ and synthesized on a Xilinx Kintex-7 XC7K160T FPGA. The area overhead for the proposed NLU-V ISE is 1088 slice registers and 4520 LUTs. As case studies, the PRESENT and AES block ciphers are implemented using the new ISE on RISC-V in assembly. Our evaluation metric to showcase the performance gain, Z ‘time-area-product (TAP)’ (the execution time in clock cycles times code memory consumption), reflects the impact of the proposed family of instructions on the performance of the cipher implementations. The simulations show that the NLU-V achieves 89% gain for PRESENT and 68% gain for AES. Further, the NLU-V requires 44% less lines of code for the PRESENT and 23% less for the AES implementation.
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Lippett, Mark. "Versatility, Variety, Value." New Electronics 56, no. 2 (February 2023): 40–41. http://dx.doi.org/10.12968/s0047-9624(23)60522-x.

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Jung, Hyun Mi, and Ki Moon Jeong. "Design of a debugger architecture for parallel programming in a heterogeneous environment from a co-design point of view." Korean Institute of Smart Media 13, no. 12 (December 31, 2024): 109–15. https://doi.org/10.30693/smj.2024.13.12.109.

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This paper presents the case of H/W and S/W co-design development for heterogeneous environments through the development of OpenCL debugger for RISC-V chip with accelerator function for parallel programming. The aim of the debugger development is to debug OpenCL applications running on the chip and host based on LLDB (Low-Level Debugger). The chip consists of RISC-V cores, supports FP64 data types, is a matrix/vector arithmetic accelerator with new instructions, and includes a basic RISC-V debug subsystem. We performed a targeted analysis of the RISC-V debug subsystem for debugging OpenCL applications running on the device to derive device development requirements. We also designed the debugger architecture by analysing the programming execution model.
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Tyler, Neil. "Microchip Looks to Leverage RISC-V ISA." New Electronics 53, no. 16 (September 22, 2020): 7. http://dx.doi.org/10.12968/s0047-9624(22)61384-1.

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Kovacevic, Nikola. "Implementacija vektorskog procesora baziranog na RISC-V setu instrukcija." Zbornik radova Fakulteta tehničkih nauka u Novom Sadu 35, no. 11 (November 5, 2020): 2034–37. http://dx.doi.org/10.24867/10be45kovacevic.

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U ovom radu prezentovan je 32-bitni vektorski procesor baziran na RISC-V setu instrukcija. Sistem je implementiran pomoću VHDL jezika za opis hardvera i namenjen je za soft-core primenu na FPGA platformama. Procesor je podeljen na dve celine, skalarno jezgro koje implementira RISC-V integer set instrukcija i vektorsko jezgro koje implementira RISC-V vektorski set instrukcija. Vektorsko jezgro je parametrizovano promenljivim brojem vektorskih linija, što omogućava korisniku da bira između performansi i ukupnog zauzeća resursa. Sistem je testiran na Zybo razvojnoj ploči, pri čemu je Vivado alat korišćen za njeno programiranje, analizu performansi i analizu utrošenih resursa.
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Zaytseva, Ksenia Alexeyevna, Valeria Valentinovna Puzikova, and Andrey Dmitrievich Sokolov. "On Problems in OpenBLAS Library Usage in Productized Code on RISC-V." Proceedings of the Institute for System Programming of the RAS 35, no. 5 (2023): 91–106. http://dx.doi.org/10.15514/ispras-2022-35(5)-7.

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The boundary element method usage for the numerical simulation in continuum mechanics problems leads to the need to solve a system of linear algebraic equations with a dense matrix. The de facto standards for the interface of functions over dense matrices and vectors software implementations are BLAS/LAPACK. Among the optimized open-source BLAS/LAPACK implementations, only the OpenBLAS library includes optimizations for the widest range of hardware platforms. This library is optimized for Intel, AMD, ARM and RISC-V architectures. The open RISC-V architecture ecosystem is currently actively developing. European supercomputing centers have opened RISC-V competence centers as part of the government's EuroHPC grant support, since solutions based on the ARM architecture are not recognized as part of the European initiative to develop its own technological independence. Currently, companies included in the international RISC-V consortium are developing not only high-performance RISC-V processors, but also AI accelerators, as well as video cards based on RISC-V architecture. OpenBLAS is actively supported and optimized for emerging RISC-V hardware and extensions. However, libraries used in product code are traditionally subject to strict requirements for stability and reliability in order to minimize possible errors and failures in the product. As it turned out, from this point of view, OpenBLAS has a number of problems that we had to solve in order to productize this library. In this article the OpenBLAS test system is described, the problems of testing the LAPACK functionality of the library and ways to solve them are discussed. In addition, the test coverage of the BLAS functionality is analyzed and the results achieved in increasing it are presented. It is planned to contribute the described changes to the OpenBLAS project.
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Zhang, Jipeng, Yuxing Yan, Junhao Huang, and Çetin Kaya Koç. "Optimized Software Implementation of Keccak, Kyber, and Dilithium on RV{32,64}IM{B}{V}." IACR Transactions on Cryptographic Hardware and Embedded Systems 2025, no. 1 (December 9, 2024): 632–55. https://doi.org/10.46586/tches.v2025.i1.632-655.

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With the standardization of NIST post-quantum cryptographic (PQC) schemes, optimizing these PQC schemes across various platforms presents significant research value. While most existing software implementation efforts have concentrated on ARM platforms, research on PQC implementations utilizing various RISC-V instruction set architectures (ISAs) remains limited. In light of this gap, this paper proposes comprehensive and efficient optimizations of Keccak, Kyber, and Dilithium on RV{32,64}IM{B}{V}. We thoroughly optimize these implementations for dual-issue CPUs, believing that our work on various RISC-V ISAs will provide valuable insights for future PQC deployments.Specifically, for Keccak, we revisit a range of optimization techniques, including bit interleaving, lane complementing, in-place processing, and hybrid vector/scalar implementations. We construct an optimal combination of methods aimed at achieving peak performance on dual-issue CPUs for various RISC-V ISAs. For the NTT implementations of Kyber and Dilithium, we deliver optimized solutions based on Plantard and Montgomery arithmetic for diverse RISC-V ISAs, incorporating extensive dual-issue enhancements. Additionally, we improve the signed Plantard multiplication algorithm proposed by Akoi et al. Ultimately, our testing demonstrates that our implementations of Keccak and NTT across various ISAs achieve new performance records. More importantly, they significantly enrich the PQC software ecosystem for RISC-V.
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Da Silva, Rafael, Vin´ıcius dos Santos, F´abio Petkowicz, Rafael Calc¸ada, and Ricardo Reis. "Synthesis of Steel-ASIC, a RISC-V Core." Journal of Integrated Circuits and Systems 17, no. 2 (September 17, 2022): 1–8. http://dx.doi.org/10.29292/jics.v17i2.548.

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It is presented the design flow of an ASIC version of STEEL, a RISC-V microprocessor developed at UFRGS. The microprocessor core called STEEL implements the RV32I and Zicsr instruction sets of the RISC-V specifications. The whole process entails logical and physical synthesis, using the X-Fab 180 nm, which relies on the Cadence EDA framework. The ASIC circuit operates with a maximum frequency of 19.61 MHz and the estimates obtained from the physical synthesis indicates a power consumption of 10.09 mW.
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Jamieson, Peter, Huan Le, Nathan Martin, Tyler McGrew, Yicheng Qian, Eric Schonauer, Alan Ehret, and Michel A. Kinsy. "Computer Engineering Education Experiences with RISC-V Architectures—From Computer Architecture to Microcontrollers." Journal of Low Power Electronics and Applications 12, no. 3 (August 9, 2022): 45. http://dx.doi.org/10.3390/jlpea12030045.

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With the growing popularity of RISC-V and various open-source released RISC-V processors, it is now possible for computer engineers students to explore this simple and relevant architecture, and also, these students can explore and design a microcontroller at a low-level using real tool-flows and implement and test their hardware. In this work, we describe our experiences with undergraduate engineers building RISC-V architectures on an FPGA and then extending their experiences to implement an Arduino-like RISC-V tool-flow and the respective hardware and software to handle input-output ports, interrupts, hardware timers, and communication protocols. The microcontroller is implemented on an FPGA as a Senior Design project to test the viability of such efforts. In this work, we will explain how undergraduates can achieve these experiences including preparation for these projects, the tool-flows they use, the challenges in understanding and extending a RISC-V processor with microcontroller functionality, and a suggestion of how to integrate this learning into an existing curriculum, including a discussion on if we should include these deeper experiences in the Computer Engineering undergraduate curriculum.
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Mišeljić, Đorđe, and Vuk Vranjkovic. "IMPLEMENTACIJA PODSISTEMA SKRIVENE MEMROIJE ZA RISC-V PROCESOR." Zbornik radova Fakulteta tehničkih nauka u Novom Sadu 35, no. 11 (November 5, 2020): 2030–33. http://dx.doi.org/10.24867/10be44miseljic.

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U ovom radu je modelovan podsistem skrivene (keš, eng. cache) memorije za RISC-V procesor. Model je pisan u VHDL jeziku te je ciljan za soft-core primenu na FPGA uređajima. Model se sastoji iz dva nivoa keš hijerarhije: prvi nivo je direktno preslikan i razdeljen, dok je drugi N-smerno set asocijativan i unificiran. Model je parametrizovan, te korisnik ima mogućnost da bira kapacitet memorija kao i asocijativnost. Sistem je zajedno sa jednostavnim RISC-V procesorom prvo simuliran pomoću Vivado alata a zatim upakovan u IP jezgro, implementiran i testiran na Zybo razvojnoj ploči.
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Kalapothas, Stavros, Manolis Galetakis, Georgios Flamis, Fotis Plessas, and Paris Kitsos. "A Survey on RISC-V-Based Machine Learning Ecosystem." Information 14, no. 2 (January 21, 2023): 64. http://dx.doi.org/10.3390/info14020064.

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In recent years, the advancements in specialized hardware architectures have supported the industry and the research community to address the computation power needed for more enhanced and compute intensive artificial intelligence (AI) algorithms and applications that have already reached a substantial growth, such as in natural language processing (NLP) and computer vision (CV). The developments of open-source hardware (OSH) and the contribution towards the creation of hardware-based accelerators with implication mainly in machine learning (ML), has also been significant. In particular, the reduced instruction-set computer-five (RISC-V) open standard architecture has been widely adopted by a community of researchers and commercial users, worldwide, in numerous openly available implementations. The selection through a plethora of RISC-V processor cores and the mix of architectures and configurations combined with the proliferation of ML software frameworks for ML workloads, is not trivial. In order to facilitate this process, this paper presents a survey focused on the assessment of the ecosystem that entails RISC-V based hardware for creating a classification of system-on-chip (SoC) and CPU cores, along with an inclusive arrangement of the latest released frameworks that have supported open hardware integration for ML applications. Moreover, part of this work is devoted to the challenges that are concerned, such as power efficiency and reliability, when designing and building application with OSH in the AI/ML domain. This study presents a quantitative taxonomy of RISC-V SoC and reveals the opportunities in future research in machine learning with RISC-V open-source hardware architectures.
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de Assumpção, Jecel Mattos, Oswaldo Hideo Ando, Hugo Puertas de Araújo, and Mario Gazziro. "An Educational RISC-V-Based 16-Bit Processor." Chips 3, no. 4 (November 30, 2024): 395–407. https://doi.org/10.3390/chips3040020.

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This work introduces a novel custom-designed 16-bit RISC-V processor, intended for educational purposes and for use in low-resource equipment. The implementation, despite providing registers of 16 bits, is based on RV32E RISC-V ISA, but with some key differences like a reduced instruction set that is optimized for embedded systems, the removal of floating-point instructions, reduced register count, and modified data types. These changes enable the processor to operate efficiently in resource-constrained environments while still maintaining assembly-level compatibility with the standard RISC-V architecture. The educational aspects of this project are also a key focus. By working on this project, students can gain hands-on experience with digital logic design, Verilog programming, and computer architecture. The project also includes tools and scripts to help students transform assembly code into binary format, making it easier for them to test and verify their designs. Additionally, the project’s open-source nature allows for collaboration and the sharing of knowledge among students and researchers worldwide.
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Popovici, Cosmin-Andrei, and Andrei Stan. "Real-Time RISC-V-Based CAN-FD Bus Diagnosis Tool." Micromachines 14, no. 1 (January 12, 2023): 196. http://dx.doi.org/10.3390/mi14010196.

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Network Diagnosis Tools with industrial-grade quality are not widely available for common users such as researchers and students. This kind of tool enables users to develop Distributed Embedded Systems using low-cost and reliable setups. In the context of RISC-V Extensions and Domain-Specific Architecture, this paper proposes a Real-Time RISC-V-based CAN-FD Bus Diagnosis Tool, named RiscDiag CanFd, as an open-source alternative. The RISC-V Core extension is a CAN-FD Communication Unit controlled by a dedicated ISA Extension. Besides the extended RISC-V core, the proposed SoC provides UDP Communication via Ethernet for connecting the proposed solution to a PC. Additionally, a GUI application was developed for accessing and using the hardware solution deployed in an FPGA. The proposed solution is evaluated by measuring the lost frame rate, the precision of captured frames timestamps and the latency of preparing data for Ethernet communication. Measurements revealed a 0% frame loss rate, a timestamp error under 0.001% and an acquisition cycle jitter under 10 ns.
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Xue, Wang, Liu, Lv, Wang, and Zeng. "An RISC-V Processor with Area-Efficient Memristor-Based In-Memory Computing for Hash Algorithm in Blockchain Applications." Micromachines 10, no. 8 (August 16, 2019): 541. http://dx.doi.org/10.3390/mi10080541.

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Blockchain technology is increasingly being used in Internet of things (IoT) devices for information security and data integrity. However, it is challenging to implement complex hash algorithms with limited resources in IoT devices owing to large energy consumption and a long processing time. This paper proposes an RISC-V processor with memristor-based in-memory computing (IMC) for blockchain technology in IoT applications. The IMC-adapted instructions were designed for the Keccak hash algorithm by virtue of the extendibility of the RISC-V instruction set architecture (ISA). Then, an RISC-V processor with area-efficient memristor-based IMC was developed based on an open-source core for IoT applications, Hummingbird E200. The general compiling policy with the data allocation method is also disclosed for the IMC implementation of the Keccak hash algorithm. An evaluation shows that >70% improvements in both performance and energy saving were achieved with limited area overhead after introducing IMC in the RISC-V processor.
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Pieper, Pascal, Vladimir Herdt, and Rolf Drechsler. "Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype." Journal of Low Power Electronics and Applications 12, no. 4 (September 29, 2022): 52. http://dx.doi.org/10.3390/jlpea12040052.

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RISC-V is a modern Instruction Set Architecture (ISA) that, by its open nature in combination with a clean and modular design, has enormous potential to become a game changer in the Internet of Things (IoT) era. Recently, SystemC-based Virtual Prototypes (VPs) have been introduced into the RISC-V ecosystem to lay the foundation for advanced industry-proven system-level use-cases. However, VP-driven environment modeling and interaction have mostly been neglected in the RISC-V context. In this paper, we propose such an extension to broaden the application domain for virtual prototyping in the RISC-V context. As a foundation, we built upon the open source RISC-V VP available at GitHub. For a visualization of the environment purposes, we designed a Graphical User Interface (GUI) and designed appropriate libraries to offer hardware communication interfaces such as GPIO and SPI from the VP to an interactive environment model. Our approach is designed to be integrated with SystemC-based VPs that leverage a Transaction-Level Modeling (TLM) communication system to prefer a speed-optimized simulation. To show the practicability of an environment model, we provide a set of building blocks such as buttons, LEDs and an OLED display and configured them in two demonstration environments. Moreover, for rapid prototyping purposes, we provide a modeling layer that leverages the dynamic Lua scripting language to design components and integrate them with the VP-based simulation. Our evaluation with two different case-studies demonstrates the applicability of our approach in building virtual environments effectively and correctly when matching the real physical systems. To advance the RISC-V community and stimulate further research, we provide our extended VP platform with the environment configuration and visualization toolbox, as well as both case-studies as open source on GitHub.
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Lodea, Nicolas, Willian Nunes, Vitor Zanini, Marcos Sartori, Luciano Ost, Ney Calazans, Rafael Garibotti, and Cesar Marcon. "Early Soft Error Reliability Analysis on RISC-V." IEEE Latin America Transactions 20, no. 9 (September 2022): 2139–45. http://dx.doi.org/10.1109/tla.2022.9878169.

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36

ISLAM, Md Ashraful, and Kenji KISE. "An Efficient Resource Shared RISC-V Multicore Architecture." IEICE Transactions on Information and Systems E105.D, no. 9 (September 1, 2022): 1506–15. http://dx.doi.org/10.1587/transinf.2021edp7248.

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37

Gamino del Río, Iván, Agustín Martínez Hellín, Óscar R. Polo, Miguel Jiménez Arribas, Pablo Parra, Antonio da Silva, Jonatan Sánchez, and Sebastián Sánchez. "A RISC-V Processor Design for Transparent Tracing." Electronics 9, no. 11 (November 7, 2020): 1873. http://dx.doi.org/10.3390/electronics9111873.

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Code instrumentation enables the observability of an embedded software system during its execution. A usage example of code instrumentation is the estimation of “worst-case execution time” using hybrid analysis. This analysis combines static code analysis with measurements of the execution time on the deployment platform. Static analysis of source code determines where to insert the tracing instructions, so that later, the execution time can be captured using a logic analyser. The main drawback of this technique is the overhead introduced by the execution of trace instructions. This paper proposes a modification of the architecture of a RISC pipelined processor that eliminates the execution time overhead introduced by the code instrumentation. In this way, it allows the tracing to be non-intrusive, since the sequence and execution times of the program under analysis are not modified by the introduction of traces. As a use case of the proposed solution, a processor, based on RISC-V architecture, was implemented using VHDL language. The processor, synthesized on a FPGA, was used to execute and evaluate a set of examples of instrumented code generated by a “worst-case execution time” estimation tool. The results validate that the proposed architecture executes the instrumented code without overhead.
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Hongsheng, Zhang, Zekun Jiang, and Yong Li. "Design of a dual-issue RISC-V processor." Journal of Physics: Conference Series 1693 (December 2020): 012192. http://dx.doi.org/10.1088/1742-6596/1693/1/012192.

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39

Lee, Yunsup, Andrew Waterman, Henry Cook, Brian Zimmer, Ben Keller, Alberto Puggelli, Jaehwa Kwak, et al. "An Agile Approach to Building RISC-V Microprocessors." IEEE Micro 36, no. 2 (March 2016): 8–20. http://dx.doi.org/10.1109/mm.2016.11.

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40

Helbig, Tobias. "Quelloffene RISC-V-Systeme als Chance für Europa." ATZelektronik 18, no. 11 (November 2023): 66. http://dx.doi.org/10.1007/s35658-023-1539-4.

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41

潘, 越. "Research on Formal Verification Method of RISC-V Microcontroller." Computer Science and Application 10, no. 06 (2020): 1252–58. http://dx.doi.org/10.12677/csa.2020.106129.

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Yu, Hongjiang, Guoshun Yuan, Dewei Kong, and Chuhuai Chen. "An Optimized Implementation of Activation Instruction Based on RISC-V." Electronics 12, no. 9 (April 24, 2023): 1986. http://dx.doi.org/10.3390/electronics12091986.

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Activation is an important component of the neural network, and the standard instructions of RISC-V are difficult to use to effectively handle the activation of the array. In this paper, we propose an optimized implementation of activation instruction based on RISC-V. Based on the opensource RISC-V processor Hummingbird E203, we designed a special instruction for the implementation of activation functions. A single instruction is chosen to implement the entire activation operation, including data loading, data arithmetic and data write-back. At the hardware level, we designed a method of alternate reading and writing that only needs a small hardware storage unit to meet the requirements of the activation operation for long arrays without affecting the activation efficiency. In addition, we added the length of the array as a new parameter to instruct our designed hardware to adapt to any length of arrays. Finally, the scheduling method of some instructions in the activation process was optimized in accordance with the law of instructions, which improves the execution efficiency of instructions. Considering an activation process with an array length of 15, our design demonstrates a 4.89-fold increase in speed compared to RISC-V standard instructions while consuming only 7.78% of the energy.
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43

Hayashi, Victor Takashi, and Wilson Vicente Ruggiero. "Hardware Trojan Dataset of RISC-V and Web3 Generated with ChatGPT-4." Data 9, no. 6 (June 19, 2024): 82. http://dx.doi.org/10.3390/data9060082.

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Although hardware trojans impose a relevant threat to the hardware security of RISC-V and Web3 applications, existing datasets have a limited set of examples, as the most famous hardware trojan dataset TrustHub has 106 different trojans. RISC-V specifically has study cases of three and four different hardware trojans, and no research was found regarding Web3 hardware trojans in modules such as a hardware wallet. This research presents a dataset of 290 Verilog examples generated with ChatGPT-4 Large Language Model (LLM) based on 29 golden models and the TrustHub taxonomy. It is expected that this dataset supports future research endeavors regarding defense mechanisms against hardware trojans in RISC-V, hardware wallet, and hardware Proof of Work (PoW) miner.
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Wang, Tengfei, Chi Zhang, Xiaolin Zhang, Dawu Gu, and Pei Cao. "Optimized Hardware-Software Co-Design for Kyber and Dilithium on RISC-V SoC FPGA." IACR Transactions on Cryptographic Hardware and Embedded Systems 2024, no. 3 (July 18, 2024): 99–135. http://dx.doi.org/10.46586/tches.v2024.i3.99-135.

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Kyber and Dilithium are both lattice-based post-quantum cryptography (PQC) algorithms that have been selected for standardization by the American National Institute of Standards and Technology (NIST). NIST recommends them as two primary algorithms to be implemented for most use cases. As the applications of RISC-V processors move from specialized scenarios to general scenarios, efficient implementations of PQC algorithms on general-purpose RISC-V platforms are required. In this work, we present an optimized hardware-software co-design for Kyber and Dilithium on the industry’s first RISC-V System-on-Chip (SoC) Field Programmable Gate Array (FPGA) platform. The performance of both algorithms is enhanced through the utilization of hardware acceleration and software optimization, while a certain level of flexibility is still maintained. The polynomial arithmetic operations in Kyber and Dilithium are accelerated by the customized accelerators. We employ a unified high-level architecture to depict their shared characteristics and design dedicated underlying modular multipliers to explore their distinctive features. The hashing functions are optimized using RISC-V assembly instructions, resulting in improved performance and reduced code size without additional hardware resources. For other operations involving matrices and vectors, we present a multi-core acceleration scheme based on the multi-core RISC-V Microprocessor Sub-System (MSS). Combining these acceleration and optimization methods, experimental results show that the overall performance of Kyber and Dilithium across different security levels improves by 3 to 5 times, while the utilized FPGA resources account for less than 5% of the total resources provided by the platform.
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Строгонов, А. В., О. Бордюжа, and А. И. Строгонов. "ЭФФЕКТИВНЫЙ ПОДХОД В РАЗРАБОТКЕ УПРАВЛЯЮЩИХ АВТОМАТОВ МИКРОПРОЦЕССОРНЫХ ЯДЕР." ELECTRONICS: SCIENCE, TECHNOLOGY, BUSINESS 232, no. 1 (February 5, 2024): 78–86. http://dx.doi.org/10.22184/1992-4178.2024.232.1.78.86.

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В России при участии НИУ МИЭТ организована Ассоциация вузов ЭКБ, решающих в том числе задачу подготовки специалистов для работы с архитектурой процессоров RISC-V, а также создана Школа синтеза цифровых схем на базе курса MIT в Сколково для быстрого освоения современных подходов к проектированию цифровых БИС. Архитектура RISC-V является дальнейшим развитием архитектуры MIPS, разработанной компанией MIPS Computer Systems. На архитектуре MIPS32 построен ряд российских процессоров, таких как Baikal- T от «Байкал Электроникс», «Мультикор» от АО НПЦ «ЭЛВИС» и КОМДИВ от НИИСИ РАН. Процессоры на базе RISC-V разрабатывают несколько российских компаний, в том числе Syntacore и CloudBEAR. В статье рассмотрен эффективный подход к разработке управляющего автомата микропроцессорного ядра с применением системы визуально- имитационного моделирования Matlab / Simulink и последующей генерацией VHDL-кода для разработки проекта в САПР Quartus II.
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Deng, Lifu. "Design a 5-stage pipeline RISC-V CPU and optimise its ALU." Applied and Computational Engineering 34, no. 1 (January 22, 2024): 237–44. http://dx.doi.org/10.54254/2755-2721/34/20230334.

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The RISC-V instruction set has advanced and expanded significantly in recent years. It is an open instruction set architecture (ISA) based on the concept of Reduced Instruction Set Computing (RISC). This article uses Verilog to design a 5-stage pipeline CPU based on RISC-V architecture in Vivado 2022.2. The CPU can execute 38 instructions and optimises its arithmetic logic unit (ALU) by optimising adders, shifters, and multipliers. Next, write a testbench in the simulation software to verify the functionality of the CPU. RTL diagrams and reports are then generated to verify the design structure and evaluate resource allocation. Finally, the CPU successfully executes the instruction and obtains the correct operation result, and the occupation of LUT resources in the shifter part is reduced. This work serves as an important reference for system-on-chip (SoC) and computer design in general. It not only highlights the potential of the RISC-V architecture but also demonstrates the success of optimisation efforts. This paves the way for more powerful and efficient computing systems.
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Marques, Ivo, Cristiano Rodrigues, Adriano Tavares, Sandro Pinto, and Tiago Gomes. "Lock-V: A heterogeneous fault tolerance architecture based on Arm and RISC-V." Microelectronics Reliability 120 (May 2021): 114120. http://dx.doi.org/10.1016/j.microrel.2021.114120.

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Chisnall, David. "How to Design an ISA." Queue 21, no. 6 (December 31, 2023): 27–46. http://dx.doi.org/10.1145/3639445.

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Over the past decade I've been involved in several projects that have designed either ISA (instruction set architecture) extensions or clean-slate ISAs for various kinds of processors (you'll even find my name in the acknowledgments for the RISC-V spec, right back to the first public version). When I started, I had very little idea about what makes a good ISA, and, as far as I can tell, this isn't formally taught anywhere. With the rise of RISC-V as an open base for custom instruction sets, however, the barrier to entry has become much lower and the number of people trying to design some or all of an instruction set has grown immeasurably.
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Cococcioni, Marco, Federico Rossi, Emanuele Ruffaldi, and Sergio Saponara. "Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE." Neural Computing and Applications 33, no. 16 (February 28, 2021): 10575–85. http://dx.doi.org/10.1007/s00521-021-05814-0.

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AbstractWith the arrival of the open-source RISC-V processor architecture, there is the chance to rethink Deep Neural Networks (DNNs) and information representation and processing. In this work, we will exploit the following ideas: i) reduce the number of bits needed to represent the weights of the DNNs using our recent findings and implementation of the posit number system, ii) exploit RISC-V vectorization as much as possible to speed up the format encoding/decoding, the evaluation of activations functions (using only arithmetic and logic operations, exploiting approximated formulas) and the computation of core DNNs matrix-vector operations. The comparison with the well-established architecture ARM Scalable Vector Extension is natural and challenging due to its closedness and mature nature. The results show how it is possible to vectorize posit operations on RISC-V, gaining a substantial speed-up on all the operations involved. Furthermore, the experimental outcomes highlight how the new architecture can catch up, in terms of performance, with the more mature ARM architecture. Towards this end, the present study is important because it anticipates the results that we expect to achieve when we will have an open RISC-V hardware co-processor capable to operate natively with posits.
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Джонсон, Д. "ИСПОЛЬЗОВАНИЕ RISC-V ДЛЯ УПРОЩЕНИЯ РЕГИСТРАЦИИ ДАННЫХ В КОСМОСЕ." ELECTRONICS: SCIENCE, TECHNOLOGY, BUSINESS 200, no. 9 (November 11, 2020): 118–20. http://dx.doi.org/10.22184/1992-4178.2020.200.9.118.120.

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Рассмотрено применение процессоров RISC-V и радиационно-­стойких интегральных схем для регистрации данных в космосе. Отмечено, что использование таких устройств значительно упрощает регистрацию данных, а также резко снижает общий размер и вес подсистемы сбора телеметрии, одновременно повышая ее надежность.
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