Relevant bibliographies by topics / Risk microprocessor

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Risk microprocessor'

Author: Grafiati
Published: 7 June 2025
Last updated: 2 August 2025

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Journal articles on the topic "Risk microprocessor"

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Приходько, Д. И. "Basic typing of multibit microprocessor in the structure of modern microprocessors." Vestnik of Russian New University. Series «Complex systems: models, analysis, management», no. 2 (July 8, 2023): 203–9. http://dx.doi.org/10.18137/rnu.v9187.23.02.p.203.

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Рассматриваются мультиразрядные микропроцессы – особый класс значительно улучшенных микропроцессоров, в которые встроены механизмы, отвечающие за повышение надежности работы программного обеспечения, запускаемого на данном микропроцессоре, – табличная структура регистров и система резервного копирования. Рассматривается месторасположение указанного микропроцессора и основные характеристики модельного ряда: система команд (самые популярные типы CISC и RISK), тип организации стэка (Неймана – Лебедева, гарвардская архитектура), тип распределения команд (статический или динамический). В качестве п
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Aggarwal, K. K., and Suresh Sharma. "Microprocessor based redundancy designer." Reliability Engineering & System Safety 31, no. 3 (1991): 391–98. http://dx.doi.org/10.1016/0951-8320(91)90079-m.

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Wangsong, Xie. "The Default Risk of Bank Customers Based on Embedded Microprocessor Wireless Communication under the Internet Finance Background." Mobile Information Systems 2022 (July 31, 2022): 1–15. http://dx.doi.org/10.1155/2022/8019033.

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Internet finance refers to a new financial business model in which traditional financial institutions and Internet enterprises use Internet technology and information and communication technology to achieve capital financing, payment, investment, and information intermediary services. Embedded microprocessors have more than 32-bit processors with high performance. And it is small in size, light in weight, and low in cost. This article aims to explore the default risk of bank customers based on embedded microprocessor wireless communication under the background of Internet finance and how to co
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G.W.A.D. "Microprocessor interfacing." Microelectronics Reliability 31, no. 1 (1991): 191. http://dx.doi.org/10.1016/0026-2714(91)90366-f.

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Sharma, Suresh, and K. K. Aggarwal. "Symbolic reliability evaluation using a microprocessor." Reliability Engineering & System Safety 24, no. 1 (1989): 51–67. http://dx.doi.org/10.1016/0951-8320(89)90054-9.

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Garrett, C. M. E., and D. A. Fletcher. "MICROPROCESSOR-BASED ORCHARD ENVIRONMENT MONITORS AND FIRE BLIGHT RISK ASSESSMENT." Acta Horticulturae, no. 273 (June 1990): 185–88. http://dx.doi.org/10.17660/actahortic.1990.273.23.

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Touati, A., A. Bosio, P. Girard, A. Virazel, P. Bernardi, and M. Sonza Reorda. "Microprocessor Testing: Functional Meets Structural Test." Journal of Circuits, Systems and Computers 26, no. 08 (2017): 1740007. http://dx.doi.org/10.1142/s0218126617400072.

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Structural test is widely adopted to ensure high quality for a given product. The availability of many commercial tools and the use of fault models make it very easy to generate and to evaluate. Despite its efficiency, structural test is also known for the risk of over-testing that may lead to yield loss. This problem is mainly due to the fact that structural test does not take into account the functionality of the circuit under test. On the other hand, functional test guarantees that the circuit is tested under normal conditions, thus avoiding any over- as well as under-testing issues. More i
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Zhang, Haiyan, Zhe Guo, and Yingying Sun. "Analysis of Bank Customer Default Risk Based on Embedded Microprocessor Wireless Communication." Security and Communication Networks 2022 (March 17, 2022): 1–11. http://dx.doi.org/10.1155/2022/5635152.

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Bank personal credit is affected by factors such as inadequate management and lagging risk information management system. Bank default risk analysis is needed to improve the ability of bank credit risk management. Therefore, a bank customer default risk analysis based on embedded microprocessor wireless communication is proposed. Firstly, it analyzes the risk assessment parameter evaluation system of personal credit, constructs the quantitative analysis model of personal credit risk, calculates the grade gradient value in the bank’s personal credit risk standard, carries out the mathematical m
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Wang, Huibo. "Enterprise Financial Asset Risk Measurement Based on Embedded Microprocessor Security Analysis." Wireless Communications and Mobile Computing 2022 (January 18, 2022): 1–13. http://dx.doi.org/10.1155/2022/8382504.

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As the volatility of financial markets continues to increase, the risk structure involved in financial derivatives has become more and more complex. The harmful effects of financial risks can put the company in trouble. Only by understanding the correlation between financial assets can we more accurately measure the risk of a company’s financial assets. This article is aimed at studying the company’s financial asset risk measurement method based on integrated microprocessor security analysis, so that enterprises can effectively manage the risk of financial assets. This paper randomly selects 1
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Mundell, Benjamin, Hilal Maradit Kremers, Sue Visscher, Kurtis Hoppe, and Kenton Kaufman. "Direct medical costs of accidental falls for adults with transfemoral amputations." Prosthetics and Orthotics International 41, no. 6 (2017): 564–70. http://dx.doi.org/10.1177/0309364617704804.

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Background: Active individuals with transfemoral amputations are provided a microprocessor-controlled knee with the belief that the prosthesis reduces their risk of falling. However, these prostheses are expensive and the cost-effectiveness is unknown with regard to falls in the transfemoral amputation population. The direct medical costs of falls in adults with transfemoral amputations need to be determined in order to assess the incremental costs and benefits of microprocessor-controlled prosthetic knees. Objective: We describe the direct medical costs of falls in adults with a transfemoral
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Dissertations / Theses on the topic "Risk microprocessor"

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Howe, Jonathan E. (Jonathan Emerson) 1973. "Minimizing the risk qualification test wafers have on the manufacturing readings of a new microprocessor fabrication site through data processes." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/84226.

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Thesis (S.M.)--Massachusetts Institute of Technology, Sloan School of Management; and, (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2001.<br>Includes bibliographical references (p. 73).<br>by Jonathan E. Howe.<br>S.M.
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Pittman, Richard Neil. "Extensible microprocessor without interlocked pipeline stages (emips), the reconfigurable microprocessor." Thesis, Texas A&M University, 2003. http://hdl.handle.net/1969.1/5976.

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In this thesis we propose to realize the performance benefits of applicationspecific hardware optimizations in a general-purpose, multi-user system environment using a dynamically extensible microprocessor architecture. We have called our dynamically extensible microprocessor design the Extensible Microprocessor without Interlocked Pipeline Stages, or eMIPS. The eMIPS architecture uses the interaction of fixed and configurable logic available in modern Field Programmable Gate Array (FPGA). This interaction is used to address the limitations of
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Junqueira, Alexandre Ambrozi. "Risco : microprocessador RISC CMOS de 32 bits." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 1993. http://hdl.handle.net/10183/21530.

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Este trabalho apresenta o estudo, a definição e a simulação elétrica e lógica de um microprocessador CMOS de 32 bits, com arquitetura tipo RISC - o Risco. Dentre as principais características do Risco destacam-se: dados, instruções e endereços são palavras de 32 bits; a unidade de endereçamento é a palavra, permitindo um acesso a 4 Giga palavras (16 Gbytes); a comunição com a memória é feita por um barramento multiplexado de 32 bits para dados e endereços; possui 32 registradores de 32 bits, incluídos nestes o contador de programa, o apontador de pilha, a palavra de status do processador e um
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Olufsen, Eskil Viksand. "Processing Core for Compressing Wireless Data : The Enhancement of a RISC Microprocessor." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2006. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-10067.

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<p>This thesis explores the ability of the proprietary Texas Instruments embedded 16 bits RISC microprocessor, NanoRisc, to process common lossless compression algorithms, and propose extensions in order to increase its performance on this task. In order to measure performance of the NanoRisc microprocessor, the existing software tool chain was enhanced for profiling and simulating the improvements, and three fundamentally different adaptive data compression algorithms with different supporting data structures were implemented in the NanoRisc assembly language. On the background of profiling
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Wang, Wei. "An improved instruction-level power and energy model for RISC microprocessors." Thesis, University of Southampton, 2017. https://eprints.soton.ac.uk/410308/.

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Recently, the power and energy consumed by a chip has become a primary design constraint for embedded systems and is largely aaffected by software. Because aims vary with the application domain, the best program is sometimes the most power or energy efficient one rather than the fastest. However, there is a gap between software and hardware that makes it hard to predict which code consumes the least power without measurement. Therefore, it is vital to discover which factors can affect a program's power and energy consumption. In this thesis we present an instruction level model to estimate the
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Nash, Sean Tyrer Harry W. "MizzouSMP." Diss., Columbia, Mo. : University of Missouri--Columbia, 2009. http://hdl.handle.net/10355/6484.

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Title from PDF of title page (University of Missouri--Columbia, viewed on Feb 18, 2010). The entire thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file; a non-technical public abstract appears in the public.pdf file. Thesis advisor: Dr. Harry Tyrer. Includes bibliographical references.
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DELORME, VINCENT. "Le microprocesseur f-risc : architecture haut niveau et environnement de programmation." Paris 6, 1994. http://www.theses.fr/1994PA066547.

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Une nouvelle architecture modulaire de type risc est developpee sur la base d'un jeu d'instructions a faible contenu semantique. Les specifications d'un premier microprocesseur issu de cette architecture et destine aux applications embarquees conduisent a la conception d'un circuit de complexite moderee. Ce processeur d'architecture externe de type harvard se compose en interne d'une unite centrale couplee a un processeur flottant simple precision par l'intermediaire d'un bus normalise. Le cur de type risc 32 bits muni d'un pipeline d'instructions a trois etages offre une architecture interne
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Fuchs, Franz Anton. "Analysis of Transient-Execution Attacks on the out-of-order CHERI-RISC-V Microprocessor Toooba." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-291743.

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Transient-execution attacks have been deemed a large threat for microarchitectures through research in recent years. In this work, I reproduce and develop transient-execution attacks against RISC-V and CHERI-RISC-V microarchitectures. CHERI is an instruction set architecture (ISA) security extension that provides fine-grained memory protection and compartmentalisation. I conduct transient-execution experiments for this work on Toooba – a superscalar out-of-order processor implementing CHERI-RISC-V. I present a new subclass of transient-execution attacks dubbed Meltdown-CF(Capability Forgery).
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Mikulis, Mindaugas. "Procesorinio komponento bendrinimo tyrimas: analizės aspektai." Master's thesis, Lithuanian Academic Libraries Network (LABT), 2007. http://vddb.library.lt/obj/LT-eLABa-0001:E.02~2007~D_20070816_143457-92440.

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Mikroelektronikos technologinėms galimybėms stipriai lenkiant projektavimo galimybes, projektavimo etapas reikalauja naujų metodų. Vienas iš problemos sprendimų būdų yra atkartojimo technologija. Pirmoje dalyje yra analizuojama literatūra. Apžvelgiamas atkartojimo technologijos objektas. Remiantis literatūra, pateikiamas platus ir siauras atkartojimo technologijos apibrėžimas. Pateikiami komponento apibrėžimai, komponento pakartotinio panaudojimo sąvokos ir metodai. Taip pat apžvelgiami mikroprocesoriai, mikroprocesorių architektūros. Antroje dalyje išanalizuojamas pateiktas mikroprocesorius,
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Bjäreholt, Johan. "RISC-V Compiler Performance:A Comparison between GCC and LLVM/clang." Thesis, Blekinge Tekniska Högskola, Institutionen för programvaruteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-14659.

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RISC-V is a new open-source instruction set architecture (ISA) that in De-cember 2016 manufactured its rst mass-produced processors. It focuses onboth eciency and performance and diers from other open-source architec-tures by not having a copyleft license permitting vendors to freely design,manufacture and sell RISC-V chips without any fees nor having to sharetheir modications on the reference implementations of the architecture.The goal of this thesis is to evaluate the performance of the GCC andLLVM/clang compilers support for the RISC-V target and their ability tooptimize for the architectu
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Books on the topic "Risk microprocessor"

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1955-, Chow Paul, ed. The MIPS-X RISC microprocessor. Kluwer Academic Publishers, 1989.

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Corporation, Integrated Circuit Engineering, ed. NEC VR4400MC RISC Microprocessor: Construction analysis. Integrated Circuit Engineering Corp., 1995.

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Incorporated, Advanced Micro Devices. Three-bus RISC microprocessor memory design: Handbook for Am29000, Am29005, and Am29050 microprocessors. Advanced Micro Devices Inc., 1994.

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Chow, Paul, ed. The MIPS-X RISC Microprocessor. Springer US, 1989. http://dx.doi.org/10.1007/978-1-4757-6762-9.

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inc, Motorola, ed. MC88100 risc microprocessor user's manual. 2nd ed. Prentice Hall, 1990.

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Chow, Paul. The MIPS-X RISC Microprocessor. Springer US, 1989.

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Michael, Slater, ed. A Guide to RISC microprocessors. Academic Press, 1992.

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Mann, Daniel. Programming the 29K RISC Family. Prentice-Hall, 1994.

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Inc, Motorola. PowerPC 601 RISC microprocessor user's manual. Motorola., 1993.

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(Firm), Motorola. PowerPC 602: Risc microprocessor user's manual. Motorola, 1995.

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Book chapters on the topic "Risk microprocessor"

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Malone, Michael S. "A Calculating Risk." In The Microprocessor. Springer New York, 1995. http://dx.doi.org/10.1007/978-1-4613-8433-5_1.

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Chow, Paul. "Introduction." In The MIPS-X RISC Microprocessor. Springer US, 1989. http://dx.doi.org/10.1007/978-1-4757-6762-9_1.

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Chow, Paul. "Architecture." In The MIPS-X RISC Microprocessor. Springer US, 1989. http://dx.doi.org/10.1007/978-1-4757-6762-9_2.

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Chow, Paul. "The Compiler System." In The MIPS-X RISC Microprocessor. Springer US, 1989. http://dx.doi.org/10.1007/978-1-4757-6762-9_3.

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Chow, Paul. "A Hardware Overview." In The MIPS-X RISC Microprocessor. Springer US, 1989. http://dx.doi.org/10.1007/978-1-4757-6762-9_4.

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Chow, Paul. "The Execute Engine." In The MIPS-X RISC Microprocessor. Springer US, 1989. http://dx.doi.org/10.1007/978-1-4757-6762-9_5.

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Chow, Paul. "Instruction Fetch Hardware." In The MIPS-X RISC Microprocessor. Springer US, 1989. http://dx.doi.org/10.1007/978-1-4757-6762-9_6.

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Chow, Paul. "The External Interface." In The MIPS-X RISC Microprocessor. Springer US, 1989. http://dx.doi.org/10.1007/978-1-4757-6762-9_7.

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Rafiquzzaman, Mohamed. "RISC Microprocessors: Intel 80960, Motorola MC88100 and PowerPC." In MICROPROCESSORS and MICROCOMPUTER-BASED SYSTEM DESIGN, 2nd ed. CRC Press, 2021. http://dx.doi.org/10.1201/9781003068143-8.

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Namjoo, Masood, and Anant Agrawal. "Implementing SPARC: A High-Performance 32-Bit RISC Microprocessor." In Sun Technical Reference Library. Springer New York, 1991. http://dx.doi.org/10.1007/978-1-4612-3192-9_13.

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Conference papers on the topic "Risk microprocessor"

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Mbamalu, J. E., and F. O. Edeko. "Integrity Assessment of Pipeline Networks through Close-Interval Potential Survey." In CORROSION 2004. NACE International, 2004. https://doi.org/10.5006/c2004-04192.

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Abstract This work involves a close-interval potential (CIP) data survey on approximately 154Km of Crude Oil/Gas pipeline networks. The CIP was carried out at 5-meter intervals along pipeline right of way (ROW) with a microprocessor controlled data collector (data logger) and a Cu/CuSO4 reference half-cell. The survey runs from Makaraba, Utonana, Abiteye, Dibi, Olero Creek, Opuekeba, and terminating at the Escravos Tank Farm of the western swamp facilities. This study therefore seeks to generate corrosion data with a view to determining weak sections of the pipelines/flowlines. The CIP survey
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Varbov, Ilian, Petar Minev, Matyo Dinev, and Valentina Kukenska. "Modeling a microprocessor with RISC architecture." In 2024 International Conference Automatics and Informatics (ICAI). IEEE, 2024. https://doi.org/10.1109/icai63388.2024.10851508.

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Schank, Troy, and Kynn Schulte. "A Smart Position Sensor for Articulated Rotors." In Vertical Flight Society 71st Annual Forum & Technology Display. The Vertical Flight Society, 2015. http://dx.doi.org/10.4050/f-0071-2015-10190.

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Modern articulated rotors utilize an elastomeric bearing on the root of each blade to allow multi-axis articulation through a single component. The bearing forms a spherical joint that makes measuring angular displacements in specific blade axes both coupled and difficult to measure. A smart sensing concept is developed to uncouple and separately measure the blade flapping, feathering, and lead-lag position. The sensor concept projects a magnetic field from the blade root to the rotor hub such that flap, lag and pitch displacements can be derived from a hub mounted pickup array. The device uti
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La Gala, Andrea, Matteo Chiariello, Mirco Malanchini, Mattia Tambaro, and Marcello De Matteis. "Design and Test-Verification of a Single-Cycle RISC-V Microprocessor on FPGA." In 2024 31st IEEE International Conference on Electronics, Circuits and Systems (ICECS). IEEE, 2024. https://doi.org/10.1109/icecs61496.2024.10848919.

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Omaña, M., A. Manfredi, C. Metra, R. Locatelli, M. Chiavacci, and S. Petrucci. "Silent Data Corruption and Reliability Risks due to Faults Affecting High Performance Microprocessors’ Caches*." In 2024 IEEE 30th International Symposium on On-Line Testing and Robust System Design (IOLTS). IEEE, 2024. http://dx.doi.org/10.1109/iolts60994.2024.10616059.

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Hiemstra, David M., and Nelson Hu. "Single Event Upset Characterization of the Polarfire® SoC RISC-V Microprocessor SubSystem Using Proton Irradiation." In 2024 RADECS Data Workshop. IEEE, 2024. https://doi.org/10.1109/radecs61975.2024.11017548.

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Alepko, Andrey, Tagir Abdullin, Evgenii A. Semenishchev, Ilia Khamidullin, and Prohor Karlov. "Payload stabilization system of manipulator with flexible links based on RISC-V microprocessor and stereo camera system." In Optoelectronic Imaging and Multimedia Technology XI, edited by Zhenrong Zheng and Jinli Suo. SPIE, 2024. http://dx.doi.org/10.1117/12.3039003.

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Grossi, Marco, Simone Manoni, Emanuele Parisi, et al. "A PCI Express Based Data Acquisition System for the Monitoring of Code Traces of RISC-V Microprocessors." In 2024 8th International Conference on System Reliability and Safety (ICSRS). IEEE, 2024. https://doi.org/10.1109/icsrs63046.2024.10927509.

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Yang, Zhiyuan, and Chee-Wooi Ten. "Cyber-Induced Risk Modeling for Microprocessor-Based Relays in Substations." In 2018 IEEE Innovative Smart Grid Technologies - Asia (ISGT Asia). IEEE, 2018. http://dx.doi.org/10.1109/isgt-asia.2018.8467972.

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Hartong, Mark W., and Olga K. Cataldi. "Regulatory Risk Evaluation of Positive Train Control Systems." In ASME/IEEE 2007 Joint Rail Conference and Internal Combustion Engine Division Spring Technical Conference. ASMEDC, 2007. http://dx.doi.org/10.1115/jrc/ice2007-40021.

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In February of 2005, the Federal Railroad Administration of the U.S. Department of Transportation issued a set of new performance-based regulations governing the development and use of microprocessor-based signal and train control systems. The new standard, effective March 2005, requires that replacement systems be at least as safe as the existing condition. Among the key elements used in evaluating the compliance of products to the new performance standard are quantitative and qualitative risk assessments. This paper explains the performance standard that must be followed, the regulatory back
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Reports on the topic "Risk microprocessor"

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Brown, Richard B. Design Optimization of a GaAs RISC Microprocessor with Area-Interconnect MCM Packaging. Defense Technical Information Center, 1999. http://dx.doi.org/10.21236/ada379011.

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